arch/sh/kernel/cpu/sh4a/setup-sh7785.c

   1 /*
   2  * SH7785 Setup
   3  *
   4  *  Copyright (C) 2007  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/io.h>
  15 #include <linux/mm.h>
  16 #include <linux/sh_dma.h>
  17 #include <linux/sh_timer.h>
  18 #include <linux/sh_intc.h>
  19 #include <asm/mmzone.h>
  20 #include <cpu/dma-register.h>
  21
  22 static struct plat_sci_port scif0_platform_data = {
  23         .flags          = UPF_BOOT_AUTOCONF,
  24         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  25         .type           = PORT_SCIF,
  26         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  27 };
  28
  29 static struct resource scif0_resources[] = {
  30         DEFINE_RES_MEM(0xffea0000, 0x100),
  31         DEFINE_RES_IRQ(evt2irq(0x700)),
  32 };
  33
  34 static struct platform_device scif0_device = {
  35         .name           = "sh-sci",
  36         .id             = 0,
  37         .resource       = scif0_resources,
  38         .num_resources  = ARRAY_SIZE(scif0_resources),
  39         .dev            = {
  40                 .platform_data  = &scif0_platform_data,
  41         },
  42 };
  43
  44 static struct plat_sci_port scif1_platform_data = {
  45         .flags          = UPF_BOOT_AUTOCONF,
  46         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  47         .type           = PORT_SCIF,
  48         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  49 };
  50
  51 static struct resource scif1_resources[] = {
  52         DEFINE_RES_MEM(0xffeb0000, 0x100),
  53         DEFINE_RES_IRQ(evt2irq(0x780)),
  54 };
  55
  56 static struct platform_device scif1_device = {
  57         .name           = "sh-sci",
  58         .id             = 1,
  59         .resource       = scif1_resources,
  60         .num_resources  = ARRAY_SIZE(scif1_resources),
  61         .dev            = {
  62                 .platform_data  = &scif1_platform_data,
  63         },
  64 };
  65
  66 static struct plat_sci_port scif2_platform_data = {
  67         .flags          = UPF_BOOT_AUTOCONF,
  68         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  69         .type           = PORT_SCIF,
  70         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  71 };
  72
  73 static struct resource scif2_resources[] = {
  74         DEFINE_RES_MEM(0xffec0000, 0x100),
  75         DEFINE_RES_IRQ(evt2irq(0x980)),
  76 };
  77
  78 static struct platform_device scif2_device = {
  79         .name           = "sh-sci",
  80         .id             = 2,
  81         .resource       = scif2_resources,
  82         .num_resources  = ARRAY_SIZE(scif2_resources),
  83         .dev            = {
  84                 .platform_data  = &scif2_platform_data,
  85         },
  86 };
  87
  88 static struct plat_sci_port scif3_platform_data = {
  89         .flags          = UPF_BOOT_AUTOCONF,
  90         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  91         .type           = PORT_SCIF,
  92         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  93 };
  94
  95 static struct resource scif3_resources[] = {
  96         DEFINE_RES_MEM(0xffed0000, 0x100),
  97         DEFINE_RES_IRQ(evt2irq(0x9a0)),
  98 };
  99
 100 static struct platform_device scif3_device = {
 101         .name           = "sh-sci",
 102         .id             = 3,
 103         .resource       = scif3_resources,
 104         .num_resources  = ARRAY_SIZE(scif3_resources),
 105         .dev            = {
 106                 .platform_data  = &scif3_platform_data,
 107         },
 108 };
 109
 110 static struct plat_sci_port scif4_platform_data = {
 111         .flags          = UPF_BOOT_AUTOCONF,
 112         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 113         .type           = PORT_SCIF,
 114         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 115 };
 116
 117 static struct resource scif4_resources[] = {
 118         DEFINE_RES_MEM(0xffee0000, 0x100),
 119         DEFINE_RES_IRQ(evt2irq(0x9c0)),
 120 };
 121
 122 static struct platform_device scif4_device = {
 123         .name           = "sh-sci",
 124         .id             = 4,
 125         .resource       = scif4_resources,
 126         .num_resources  = ARRAY_SIZE(scif4_resources),
 127         .dev            = {
 128                 .platform_data  = &scif4_platform_data,
 129         },
 130 };
 131
 132 static struct plat_sci_port scif5_platform_data = {
 133         .flags          = UPF_BOOT_AUTOCONF,
 134         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 135         .type           = PORT_SCIF,
 136         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 137 };
 138
 139 static struct resource scif5_resources[] = {
 140         DEFINE_RES_MEM(0xffef0000, 0x100),
 141         DEFINE_RES_IRQ(evt2irq(0x9e0)),
 142 };
 143
 144 static struct platform_device scif5_device = {
 145         .name           = "sh-sci",
 146         .id             = 5,
 147         .resource       = scif5_resources,
 148         .num_resources  = ARRAY_SIZE(scif5_resources),
 149         .dev            = {
 150                 .platform_data  = &scif5_platform_data,
 151         },
 152 };
 153
 154 static struct sh_timer_config tmu0_platform_data = {
 155         .channels_mask = 7,
 156 };
 157
 158 static struct resource tmu0_resources[] = {
 159         DEFINE_RES_MEM(0xffd80000, 0x30),
 160         DEFINE_RES_IRQ(evt2irq(0x580)),
 161         DEFINE_RES_IRQ(evt2irq(0x5a0)),
 162         DEFINE_RES_IRQ(evt2irq(0x5c0)),
 163 };
 164
 165 static struct platform_device tmu0_device = {
 166         .name           = "sh-tmu",
 167         .id             = 0,
 168         .dev = {
 169                 .platform_data  = &tmu0_platform_data,
 170         },
 171         .resource       = tmu0_resources,
 172         .num_resources  = ARRAY_SIZE(tmu0_resources),
 173 };
 174
 175 static struct sh_timer_config tmu1_platform_data = {
 176         .channels_mask = 7,
 177 };
 178
 179 static struct resource tmu1_resources[] = {
 180         DEFINE_RES_MEM(0xffdc0000, 0x2c),
 181         DEFINE_RES_IRQ(evt2irq(0xe00)),
 182         DEFINE_RES_IRQ(evt2irq(0xe20)),
 183         DEFINE_RES_IRQ(evt2irq(0xe40)),
 184 };
 185
 186 static struct platform_device tmu1_device = {
 187         .name           = "sh-tmu",
 188         .id             = 1,
 189         .dev = {
 190                 .platform_data  = &tmu1_platform_data,
 191         },
 192         .resource       = tmu1_resources,
 193         .num_resources  = ARRAY_SIZE(tmu1_resources),
 194 };
 195
 196 /* DMA */
 197 static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
 198         {
 199                 .offset = 0,
 200                 .dmars = 0,
 201                 .dmars_bit = 0,
 202         }, {
 203                 .offset = 0x10,
 204                 .dmars = 0,
 205                 .dmars_bit = 8,
 206         }, {
 207                 .offset = 0x20,
 208                 .dmars = 4,
 209                 .dmars_bit = 0,
 210         }, {
 211                 .offset = 0x30,
 212                 .dmars = 4,
 213                 .dmars_bit = 8,
 214         }, {
 215                 .offset = 0x50,
 216                 .dmars = 8,
 217                 .dmars_bit = 0,
 218         }, {
 219                 .offset = 0x60,
 220                 .dmars = 8,
 221                 .dmars_bit = 8,
 222         }
 223 };
 224
 225 static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
 226         {
 227                 .offset = 0,
 228         }, {
 229                 .offset = 0x10,
 230         }, {
 231                 .offset = 0x20,
 232         }, {
 233                 .offset = 0x30,
 234         }, {
 235                 .offset = 0x50,
 236         }, {
 237                 .offset = 0x60,
 238         }
 239 };
 240
 241 static const unsigned int ts_shift[] = TS_SHIFT;
 242
 243 static struct sh_dmae_pdata dma0_platform_data = {
 244         .channel        = sh7785_dmae0_channels,
 245         .channel_num    = ARRAY_SIZE(sh7785_dmae0_channels),
 246         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 247         .ts_low_mask    = CHCR_TS_LOW_MASK,
 248         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 249         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 250         .ts_shift       = ts_shift,
 251         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 252         .dmaor_init     = DMAOR_INIT,
 253 };
 254
 255 static struct sh_dmae_pdata dma1_platform_data = {
 256         .channel        = sh7785_dmae1_channels,
 257         .channel_num    = ARRAY_SIZE(sh7785_dmae1_channels),
 258         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 259         .ts_low_mask    = CHCR_TS_LOW_MASK,
 260         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 261         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 262         .ts_shift       = ts_shift,
 263         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 264         .dmaor_init     = DMAOR_INIT,
 265 };
 266
 267 static struct resource sh7785_dmae0_resources[] = {
 268         [0] = {
 269                 /* Channel registers and DMAOR */
 270                 .start  = 0xfc808020,
 271                 .end    = 0xfc80808f,
 272                 .flags  = IORESOURCE_MEM,
 273         },
 274         [1] = {
 275                 /* DMARSx */
 276                 .start  = 0xfc809000,
 277                 .end    = 0xfc80900b,
 278                 .flags  = IORESOURCE_MEM,
 279         },
 280         {
 281                 /*
 282                  * Real DMA error vector is 0x6e0, and channel
 283                  * vectors are 0x620-0x6c0
 284                  */
 285                 .name   = "error_irq",
 286                 .start  = evt2irq(0x620),
 287                 .end    = evt2irq(0x620),
 288                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 289         },
 290 };
 291
 292 static struct resource sh7785_dmae1_resources[] = {
 293         [0] = {
 294                 /* Channel registers and DMAOR */
 295                 .start  = 0xfcc08020,
 296                 .end    = 0xfcc0808f,
 297                 .flags  = IORESOURCE_MEM,
 298         },
 299         /* DMAC1 has no DMARS */
 300         {
 301                 /*
 302                  * Real DMA error vector is 0x940, and channel
 303                  * vectors are 0x880-0x920
 304                  */
 305                 .name   = "error_irq",
 306                 .start  = evt2irq(0x880),
 307                 .end    = evt2irq(0x880),
 308                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 309         },
 310 };
 311
 312 static struct platform_device dma0_device = {
 313         .name           = "sh-dma-engine",
 314         .id             = 0,
 315         .resource       = sh7785_dmae0_resources,
 316         .num_resources  = ARRAY_SIZE(sh7785_dmae0_resources),
 317         .dev            = {
 318                 .platform_data  = &dma0_platform_data,
 319         },
 320 };
 321
 322 static struct platform_device dma1_device = {
 323         .name           = "sh-dma-engine",
 324         .id             = 1,
 325         .resource       = sh7785_dmae1_resources,
 326         .num_resources  = ARRAY_SIZE(sh7785_dmae1_resources),
 327         .dev            = {
 328                 .platform_data  = &dma1_platform_data,
 329         },
 330 };
 331
 332 static struct platform_device *sh7785_devices[] __initdata = {
 333         &scif0_device,
 334         &scif1_device,
 335         &scif2_device,
 336         &scif3_device,
 337         &scif4_device,
 338         &scif5_device,
 339         &tmu0_device,
 340         &tmu1_device,
 341         &dma0_device,
 342         &dma1_device,
 343 };
 344
 345 static int __init sh7785_devices_setup(void)
 346 {
 347         return platform_add_devices(sh7785_devices,
 348                                     ARRAY_SIZE(sh7785_devices));
 349 }
 350 arch_initcall(sh7785_devices_setup);
 351
 352 static struct platform_device *sh7785_early_devices[] __initdata = {
 353         &scif0_device,
 354         &scif1_device,
 355         &scif2_device,
 356         &scif3_device,
 357         &scif4_device,
 358         &scif5_device,
 359         &tmu0_device,
 360         &tmu1_device,
 361 };
 362
 363 void __init plat_early_device_setup(void)
 364 {
 365         early_platform_add_devices(sh7785_early_devices,
 366                                    ARRAY_SIZE(sh7785_early_devices));
 367 }
 368
 369 enum {
 370         UNUSED = 0,
 371
 372         /* interrupt sources */
 373
 374         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 375         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 376         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 377         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 378
 379         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 380         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 381         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 382         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 383
 384         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 385         WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 386         HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
 387         SCIF2, SCIF3, SCIF4, SCIF5,
 388         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 389         SIOF, MMCIF, DU, GDTA,
 390         TMU3, TMU4, TMU5,
 391         SSI0, SSI1,
 392         HAC0, HAC1,
 393         FLCTL, GPIO,
 394
 395         /* interrupt groups */
 396
 397         TMU012, TMU345
 398 };
 399
 400 static struct intc_vect vectors[] __initdata = {
 401         INTC_VECT(WDT, 0x560),
 402         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 403         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 404         INTC_VECT(HUDI, 0x600),
 405         INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
 406         INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
 407         INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
 408         INTC_VECT(DMAC0, 0x6e0),
 409         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 410         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 411         INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
 412         INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
 413         INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
 414         INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
 415         INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
 416         INTC_VECT(DMAC1, 0x940),
 417         INTC_VECT(HSPI, 0x960),
 418         INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
 419         INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
 420         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 421         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 422         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 423         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 424         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 425         INTC_VECT(SIOF, 0xc00),
 426         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 427         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 428         INTC_VECT(DU, 0xd80),
 429         INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
 430         INTC_VECT(GDTA, 0xde0),
 431         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 432         INTC_VECT(TMU5, 0xe40),
 433         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 434         INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
 435         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
 436         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
 437         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 438         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 439 };
 440
 441 static struct intc_group groups[] __initdata = {
 442         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 443         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 444 };
 445
 446 static struct intc_mask_reg mask_registers[] __initdata = {
 447         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 448           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 449
 450         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 451           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 452             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 453             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 454             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 455             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 456             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 457             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 458             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 459
 460         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 461           { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
 462             FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 463             PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
 464             SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
 465 };
 466
 467 static struct intc_prio_reg prio_registers[] __initdata = {
 468         { 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 469                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 470         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 471                                                  TMU2, TMU2_TICPI } },
 472         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
 473         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
 474                                                  SCIF2, SCIF3 } },
 475         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
 476         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
 477         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
 478                                                  PCISERR, PCIINTA } },
 479         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
 480                                                  PCIINTD, PCIC5 } },
 481         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
 482         { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
 483         { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
 484 };
 485
 486 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
 487                          mask_registers, prio_registers, NULL);
 488
 489 /* Support for external interrupt pins in IRQ mode */
 490
 491 static struct intc_vect vectors_irq0123[] __initdata = {
 492         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 493         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 494 };
 495
 496 static struct intc_vect vectors_irq4567[] __initdata = {
 497         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 498         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 499 };
 500
 501 static struct intc_sense_reg sense_registers[] __initdata = {
 502         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 503                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 504 };
 505
 506 static struct intc_mask_reg ack_registers[] __initdata = {
 507         { 0xffd00024, 0, 32, /* INTREQ */
 508           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 509 };
 510
 511 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
 512                              vectors_irq0123, NULL, mask_registers,
 513                              prio_registers, sense_registers, ack_registers);
 514
 515 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
 516                              vectors_irq4567, NULL, mask_registers,
 517                              prio_registers, sense_registers, ack_registers);
 518
 519 /* External interrupt pins in IRL mode */
 520
 521 static struct intc_vect vectors_irl0123[] __initdata = {
 522         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 523         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 524         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 525         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 526         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 527         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 528         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 529         INTC_VECT(IRL0_HHHL, 0x3c0),
 530 };
 531
 532 static struct intc_vect vectors_irl4567[] __initdata = {
 533         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 534         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 535         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 536         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 537         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 538         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 539         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 540         INTC_VECT(IRL4_HHHL, 0xcc0),
 541 };
 542
 543 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
 544                          NULL, mask_registers, NULL, NULL);
 545
 546 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 547                          NULL, mask_registers, NULL, NULL);
 548
 549 #define INTC_ICR0       0xffd00000
 550 #define INTC_INTMSK0    0xffd00044
 551 #define INTC_INTMSK1    0xffd00048
 552 #define INTC_INTMSK2    0xffd40080
 553 #define INTC_INTMSKCLR1 0xffd00068
 554 #define INTC_INTMSKCLR2 0xffd40084
 555
 556 void __init plat_irq_setup(void)
 557 {
 558         /* disable IRQ3-0 + IRQ7-4 */
 559         __raw_writel(0xff000000, INTC_INTMSK0);
 560
 561         /* disable IRL3-0 + IRL7-4 */
 562         __raw_writel(0xc0000000, INTC_INTMSK1);
 563         __raw_writel(0xfffefffe, INTC_INTMSK2);
 564
 565         /* select IRL mode for IRL3-0 + IRL7-4 */
 566         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 567
 568         /* disable holding function, ie enable "SH-4 Mode" */
 569         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 570
 571         register_intc_controller(&intc_desc);
 572 }
 573
 574 void __init plat_irq_setup_pins(int mode)
 575 {
 576         switch (mode) {
 577         case IRQ_MODE_IRQ7654:
 578                 /* select IRQ mode for IRL7-4 */
 579                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 580                 register_intc_controller(&intc_desc_irq4567);
 581                 break;
 582         case IRQ_MODE_IRQ3210:
 583                 /* select IRQ mode for IRL3-0 */
 584                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 585                 register_intc_controller(&intc_desc_irq0123);
 586                 break;
 587         case IRQ_MODE_IRL7654:
 588                 /* enable IRL7-4 but don't provide any masking */
 589                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 590                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 591                 break;
 592         case IRQ_MODE_IRL3210:
 593                 /* enable IRL0-3 but don't provide any masking */
 594                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 595                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 596                 break;
 597         case IRQ_MODE_IRL7654_MASK:
 598                 /* enable IRL7-4 and mask using cpu intc controller */
 599                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 600                 register_intc_controller(&intc_desc_irl4567);
 601                 break;
 602         case IRQ_MODE_IRL3210_MASK:
 603                 /* enable IRL0-3 and mask using cpu intc controller */
 604                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 605                 register_intc_controller(&intc_desc_irl0123);
 606                 break;
 607         default:
 608                 BUG();
 609         }
 610 }
 611
 612 void __init plat_mem_setup(void)
 613 {
 614         /* Register the URAM space as Node 1 */
 615         setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
 616 }