arch/sh/kernel/cpu/sh4a/setup-sh7786.c

   1 /*
   2  * SH7786 Setup
   3  *
   4  * Copyright (C) 2009 - 2011  Renesas Solutions Corp.
   5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  * Paul Mundt <paul.mundt@renesas.com>
   7  *
   8  * Based on SH7785 Setup
   9  *
  10  *  Copyright (C) 2007  Paul Mundt
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file "COPYING" in the main directory of this archive
  14  * for more details.
  15  */
  16 #include <linux/platform_device.h>
  17 #include <linux/init.h>
  18 #include <linux/serial.h>
  19 #include <linux/serial_sci.h>
  20 #include <linux/io.h>
  21 #include <linux/mm.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/sh_timer.h>
  24 #include <linux/sh_dma.h>
  25 #include <linux/sh_intc.h>
  26 #include <linux/usb/ohci_pdriver.h>
  27 #include <cpu/dma-register.h>
  28 #include <asm/mmzone.h>
  29
  30 static struct plat_sci_port scif0_platform_data = {
  31         .flags          = UPF_BOOT_AUTOCONF,
  32         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  33         .type           = PORT_SCIF,
  34         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  35 };
  36
  37 static struct resource scif0_resources[] = {
  38         DEFINE_RES_MEM(0xffea0000, 0x100),
  39         DEFINE_RES_IRQ(evt2irq(0x700)),
  40         DEFINE_RES_IRQ(evt2irq(0x720)),
  41         DEFINE_RES_IRQ(evt2irq(0x760)),
  42         DEFINE_RES_IRQ(evt2irq(0x740)),
  43 };
  44
  45 static struct platform_device scif0_device = {
  46         .name           = "sh-sci",
  47         .id             = 0,
  48         .resource       = scif0_resources,
  49         .num_resources  = ARRAY_SIZE(scif0_resources),
  50         .dev            = {
  51                 .platform_data  = &scif0_platform_data,
  52         },
  53 };
  54
  55 /*
  56  * The rest of these all have multiplexed IRQs
  57  */
  58 static struct plat_sci_port scif1_platform_data = {
  59         .flags          = UPF_BOOT_AUTOCONF,
  60         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  61         .type           = PORT_SCIF,
  62         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  63 };
  64
  65 static struct resource scif1_resources[] = {
  66         DEFINE_RES_MEM(0xffeb0000, 0x100),
  67         DEFINE_RES_IRQ(evt2irq(0x780)),
  68 };
  69
  70 static struct resource scif1_demux_resources[] = {
  71         DEFINE_RES_MEM(0xffeb0000, 0x100),
  72         /* Placeholders, see sh7786_devices_setup() */
  73         DEFINE_RES_IRQ(0),
  74         DEFINE_RES_IRQ(0),
  75         DEFINE_RES_IRQ(0),
  76         DEFINE_RES_IRQ(0),
  77 };
  78
  79 static struct platform_device scif1_device = {
  80         .name           = "sh-sci",
  81         .id             = 1,
  82         .resource       = scif1_resources,
  83         .num_resources  = ARRAY_SIZE(scif1_resources),
  84         .dev            = {
  85                 .platform_data  = &scif1_platform_data,
  86         },
  87 };
  88
  89 static struct plat_sci_port scif2_platform_data = {
  90         .flags          = UPF_BOOT_AUTOCONF,
  91         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  92         .type           = PORT_SCIF,
  93         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  94 };
  95
  96 static struct resource scif2_resources[] = {
  97         DEFINE_RES_MEM(0xffec0000, 0x100),
  98         DEFINE_RES_IRQ(evt2irq(0x840)),
  99 };
 100
 101 static struct platform_device scif2_device = {
 102         .name           = "sh-sci",
 103         .id             = 2,
 104         .resource       = scif2_resources,
 105         .num_resources  = ARRAY_SIZE(scif2_resources),
 106         .dev            = {
 107                 .platform_data  = &scif2_platform_data,
 108         },
 109 };
 110
 111 static struct plat_sci_port scif3_platform_data = {
 112         .flags          = UPF_BOOT_AUTOCONF,
 113         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 114         .type           = PORT_SCIF,
 115         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 116 };
 117
 118 static struct resource scif3_resources[] = {
 119         DEFINE_RES_MEM(0xffed0000, 0x100),
 120         DEFINE_RES_IRQ(evt2irq(0x860)),
 121 };
 122
 123 static struct platform_device scif3_device = {
 124         .name           = "sh-sci",
 125         .id             = 3,
 126         .resource       = scif3_resources,
 127         .num_resources  = ARRAY_SIZE(scif3_resources),
 128         .dev            = {
 129                 .platform_data  = &scif3_platform_data,
 130         },
 131 };
 132
 133 static struct plat_sci_port scif4_platform_data = {
 134         .flags          = UPF_BOOT_AUTOCONF,
 135         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 136         .type           = PORT_SCIF,
 137         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 138 };
 139
 140 static struct resource scif4_resources[] = {
 141         DEFINE_RES_MEM(0xffee0000, 0x100),
 142         DEFINE_RES_IRQ(evt2irq(0x880)),
 143 };
 144
 145 static struct platform_device scif4_device = {
 146         .name           = "sh-sci",
 147         .id             = 4,
 148         .resource       = scif4_resources,
 149         .num_resources  = ARRAY_SIZE(scif4_resources),
 150         .dev            = {
 151                 .platform_data  = &scif4_platform_data,
 152         },
 153 };
 154
 155 static struct plat_sci_port scif5_platform_data = {
 156         .flags          = UPF_BOOT_AUTOCONF,
 157         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 158         .type           = PORT_SCIF,
 159         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 160 };
 161
 162 static struct resource scif5_resources[] = {
 163         DEFINE_RES_MEM(0xffef0000, 0x100),
 164         DEFINE_RES_IRQ(evt2irq(0x8a0)),
 165 };
 166
 167 static struct platform_device scif5_device = {
 168         .name           = "sh-sci",
 169         .id             = 5,
 170         .resource       = scif5_resources,
 171         .num_resources  = ARRAY_SIZE(scif5_resources),
 172         .dev            = {
 173                 .platform_data  = &scif5_platform_data,
 174         },
 175 };
 176
 177 static struct sh_timer_config tmu0_platform_data = {
 178         .channels_mask = 7,
 179 };
 180
 181 static struct resource tmu0_resources[] = {
 182         DEFINE_RES_MEM(0xffd80000, 0x30),
 183         DEFINE_RES_IRQ(evt2irq(0x400)),
 184         DEFINE_RES_IRQ(evt2irq(0x420)),
 185         DEFINE_RES_IRQ(evt2irq(0x440)),
 186 };
 187
 188 static struct platform_device tmu0_device = {
 189         .name           = "sh-tmu",
 190         .id             = 0,
 191         .dev = {
 192                 .platform_data  = &tmu0_platform_data,
 193         },
 194         .resource       = tmu0_resources,
 195         .num_resources  = ARRAY_SIZE(tmu0_resources),
 196 };
 197
 198 static struct sh_timer_config tmu1_platform_data = {
 199         .channels_mask = 7,
 200 };
 201
 202 static struct resource tmu1_resources[] = {
 203         DEFINE_RES_MEM(0xffda0000, 0x2c),
 204         DEFINE_RES_IRQ(evt2irq(0x480)),
 205         DEFINE_RES_IRQ(evt2irq(0x4a0)),
 206         DEFINE_RES_IRQ(evt2irq(0x4c0)),
 207 };
 208
 209 static struct platform_device tmu1_device = {
 210         .name           = "sh-tmu",
 211         .id             = 1,
 212         .dev = {
 213                 .platform_data  = &tmu1_platform_data,
 214         },
 215         .resource       = tmu1_resources,
 216         .num_resources  = ARRAY_SIZE(tmu1_resources),
 217 };
 218
 219 static struct sh_timer_config tmu2_platform_data = {
 220         .channels_mask = 7,
 221 };
 222
 223 static struct resource tmu2_resources[] = {
 224         DEFINE_RES_MEM(0xffdc0000, 0x2c),
 225         DEFINE_RES_IRQ(evt2irq(0x7a0)),
 226         DEFINE_RES_IRQ(evt2irq(0x7a0)),
 227         DEFINE_RES_IRQ(evt2irq(0x7a0)),
 228 };
 229
 230 static struct platform_device tmu2_device = {
 231         .name           = "sh-tmu",
 232         .id             = 2,
 233         .dev = {
 234                 .platform_data  = &tmu2_platform_data,
 235         },
 236         .resource       = tmu2_resources,
 237         .num_resources  = ARRAY_SIZE(tmu2_resources),
 238 };
 239
 240 static struct sh_timer_config tmu3_platform_data = {
 241         .channels_mask = 7,
 242 };
 243
 244 static struct resource tmu3_resources[] = {
 245         DEFINE_RES_MEM(0xffde0000, 0x2c),
 246         DEFINE_RES_IRQ(evt2irq(0x7c0)),
 247         DEFINE_RES_IRQ(evt2irq(0x7c0)),
 248         DEFINE_RES_IRQ(evt2irq(0x7c0)),
 249 };
 250
 251 static struct platform_device tmu3_device = {
 252         .name           = "sh-tmu",
 253         .id             = 3,
 254         .dev = {
 255                 .platform_data  = &tmu3_platform_data,
 256         },
 257         .resource       = tmu3_resources,
 258         .num_resources  = ARRAY_SIZE(tmu3_resources),
 259 };
 260
 261 static const struct sh_dmae_channel dmac0_channels[] = {
 262         {
 263                 .offset = 0,
 264                 .dmars = 0,
 265                 .dmars_bit = 0,
 266         }, {
 267                 .offset = 0x10,
 268                 .dmars = 0,
 269                 .dmars_bit = 8,
 270         }, {
 271                 .offset = 0x20,
 272                 .dmars = 4,
 273                 .dmars_bit = 0,
 274         }, {
 275                 .offset = 0x30,
 276                 .dmars = 4,
 277                 .dmars_bit = 8,
 278         }, {
 279                 .offset = 0x50,
 280                 .dmars = 8,
 281                 .dmars_bit = 0,
 282         }, {
 283                 .offset = 0x60,
 284                 .dmars = 8,
 285                 .dmars_bit = 8,
 286         }
 287 };
 288
 289 static const unsigned int ts_shift[] = TS_SHIFT;
 290
 291 static struct sh_dmae_pdata dma0_platform_data = {
 292         .channel        = dmac0_channels,
 293         .channel_num    = ARRAY_SIZE(dmac0_channels),
 294         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 295         .ts_low_mask    = CHCR_TS_LOW_MASK,
 296         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 297         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 298         .ts_shift       = ts_shift,
 299         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 300         .dmaor_init     = DMAOR_INIT,
 301 };
 302
 303 /* Resource order important! */
 304 static struct resource dmac0_resources[] = {
 305         {
 306                 /* Channel registers and DMAOR */
 307                 .start  = 0xfe008020,
 308                 .end    = 0xfe00808f,
 309                 .flags  = IORESOURCE_MEM,
 310         }, {
 311                 /* DMARSx */
 312                 .start  = 0xfe009000,
 313                 .end    = 0xfe00900b,
 314                 .flags  = IORESOURCE_MEM,
 315         }, {
 316                 .name   = "error_irq",
 317                 .start  = evt2irq(0x5c0),
 318                 .end    = evt2irq(0x5c0),
 319                 .flags  = IORESOURCE_IRQ,
 320         }, {
 321                 /* IRQ for channels 0-5 */
 322                 .start  = evt2irq(0x500),
 323                 .end    = evt2irq(0x5a0),
 324                 .flags  = IORESOURCE_IRQ,
 325         },
 326 };
 327
 328 static struct platform_device dma0_device = {
 329         .name           = "sh-dma-engine",
 330         .id             = 0,
 331         .resource       = dmac0_resources,
 332         .num_resources  = ARRAY_SIZE(dmac0_resources),
 333         .dev            = {
 334                 .platform_data  = &dma0_platform_data,
 335         },
 336 };
 337
 338 #define USB_EHCI_START 0xffe70000
 339 #define USB_OHCI_START 0xffe70400
 340
 341 static struct resource usb_ehci_resources[] = {
 342         [0] = {
 343                 .start  = USB_EHCI_START,
 344                 .end    = USB_EHCI_START + 0x3ff,
 345                 .flags  = IORESOURCE_MEM,
 346         },
 347         [1] = {
 348                 .start  = evt2irq(0xba0),
 349                 .end    = evt2irq(0xba0),
 350                 .flags  = IORESOURCE_IRQ,
 351         },
 352 };
 353
 354 static struct platform_device usb_ehci_device = {
 355         .name           = "sh_ehci",
 356         .id             = -1,
 357         .dev = {
 358                 .dma_mask               = &usb_ehci_device.dev.coherent_dma_mask,
 359                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 360         },
 361         .num_resources  = ARRAY_SIZE(usb_ehci_resources),
 362         .resource       = usb_ehci_resources,
 363 };
 364
 365 static struct resource usb_ohci_resources[] = {
 366         [0] = {
 367                 .start  = USB_OHCI_START,
 368                 .end    = USB_OHCI_START + 0x3ff,
 369                 .flags  = IORESOURCE_MEM,
 370         },
 371         [1] = {
 372                 .start  = evt2irq(0xba0),
 373                 .end    = evt2irq(0xba0),
 374                 .flags  = IORESOURCE_IRQ,
 375         },
 376 };
 377
 378 static struct usb_ohci_pdata usb_ohci_pdata;
 379
 380 static struct platform_device usb_ohci_device = {
 381         .name           = "ohci-platform",
 382         .id             = -1,
 383         .dev = {
 384                 .dma_mask               = &usb_ohci_device.dev.coherent_dma_mask,
 385                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 386                 .platform_data          = &usb_ohci_pdata,
 387         },
 388         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 389         .resource       = usb_ohci_resources,
 390 };
 391
 392 static struct platform_device *sh7786_early_devices[] __initdata = {
 393         &scif0_device,
 394         &scif1_device,
 395         &scif2_device,
 396         &scif3_device,
 397         &scif4_device,
 398         &scif5_device,
 399         &tmu0_device,
 400         &tmu1_device,
 401         &tmu2_device,
 402 };
 403
 404 static struct platform_device *sh7786_devices[] __initdata = {
 405         &dma0_device,
 406         &usb_ehci_device,
 407         &usb_ohci_device,
 408 };
 409
 410 /*
 411  * Please call this function if your platform board
 412  * use external clock for USB
 413  * */
 414 #define USBCTL0         0xffe70858
 415 #define CLOCK_MODE_MASK 0xffffff7f
 416 #define EXT_CLOCK_MODE  0x00000080
 417
 418 void __init sh7786_usb_use_exclock(void)
 419 {
 420         u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
 421         __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
 422 }
 423
 424 #define USBINITREG1     0xffe70094
 425 #define USBINITREG2     0xffe7009c
 426 #define USBINITVAL1     0x00ff0040
 427 #define USBINITVAL2     0x00000001
 428
 429 #define USBPCTL1        0xffe70804
 430 #define USBST           0xffe70808
 431 #define PHY_ENB         0x00000001
 432 #define PLL_ENB         0x00000002
 433 #define PHY_RST         0x00000004
 434 #define ACT_PLL_STATUS  0xc0000000
 435
 436 static void __init sh7786_usb_setup(void)
 437 {
 438         int i = 1000000;
 439
 440         /*
 441          * USB initial settings
 442          *
 443          * The following settings are necessary
 444          * for using the USB modules.
 445          *
 446          * see "USB Initial Settings" for detail
 447          */
 448         __raw_writel(USBINITVAL1, USBINITREG1);
 449         __raw_writel(USBINITVAL2, USBINITREG2);
 450
 451         /*
 452          * Set the PHY and PLL enable bit
 453          */
 454         __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
 455         while (i--) {
 456                 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
 457                         /* Set the PHY RST bit */
 458                         __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
 459                         printk(KERN_INFO "sh7786 usb setup done\n");
 460                         break;
 461                 }
 462                 cpu_relax();
 463         }
 464 }
 465
 466 enum {
 467         UNUSED = 0,
 468
 469         /* interrupt sources */
 470         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 471         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 472         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 473         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 474
 475         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 476         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 477         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 478         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 479
 480         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 481         WDT,
 482         TMU0_0, TMU0_1, TMU0_2, TMU0_3,
 483         TMU1_0, TMU1_1, TMU1_2,
 484         DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 485         HUDI1, HUDI0,
 486         DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 487         HPB_0, HPB_1, HPB_2,
 488         SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 489         SCIF1,
 490         TMU2, TMU3,
 491         SCIF2, SCIF3, SCIF4, SCIF5,
 492         Eth_0, Eth_1,
 493         PCIeC0_0, PCIeC0_1, PCIeC0_2,
 494         PCIeC1_0, PCIeC1_1, PCIeC1_2,
 495         USB,
 496         I2C0, I2C1,
 497         DU,
 498         SSI0, SSI1, SSI2, SSI3,
 499         PCIeC2_0, PCIeC2_1, PCIeC2_2,
 500         HAC0, HAC1,
 501         FLCTL,
 502         HSPI,
 503         GPIO0, GPIO1,
 504         Thermal,
 505         INTICI0, INTICI1, INTICI2, INTICI3,
 506         INTICI4, INTICI5, INTICI6, INTICI7,
 507
 508         /* Muxed sub-events */
 509         TXI1, BRI1, RXI1, ERI1,
 510 };
 511
 512 static struct intc_vect sh7786_vectors[] __initdata = {
 513         INTC_VECT(WDT, 0x3e0),
 514         INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
 515         INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
 516         INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
 517         INTC_VECT(TMU1_2, 0x4c0),
 518         INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
 519         INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
 520         INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
 521         INTC_VECT(DMAC0_6, 0x5c0),
 522         INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
 523         INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
 524         INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
 525         INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
 526         INTC_VECT(HPB_2, 0x6e0),
 527         INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
 528         INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
 529         INTC_VECT(SCIF1, 0x780),
 530         INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
 531         INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
 532         INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
 533         INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
 534         INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
 535         INTC_VECT(PCIeC0_2, 0xb20),
 536         INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
 537         INTC_VECT(PCIeC1_2, 0xb80),
 538         INTC_VECT(USB, 0xba0),
 539         INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
 540         INTC_VECT(DU, 0xd00),
 541         INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
 542         INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
 543         INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
 544         INTC_VECT(PCIeC2_2, 0xde0),
 545         INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
 546         INTC_VECT(FLCTL, 0xe40),
 547         INTC_VECT(HSPI, 0xe80),
 548         INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
 549         INTC_VECT(Thermal, 0xee0),
 550         INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
 551         INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
 552         INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
 553         INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
 554 };
 555
 556 #define CnINTMSK0       0xfe410030
 557 #define CnINTMSK1       0xfe410040
 558 #define CnINTMSKCLR0    0xfe410050
 559 #define CnINTMSKCLR1    0xfe410060
 560 #define CnINT2MSKR0     0xfe410a20
 561 #define CnINT2MSKR1     0xfe410a24
 562 #define CnINT2MSKR2     0xfe410a28
 563 #define CnINT2MSKR3     0xfe410a2c
 564 #define CnINT2MSKCR0    0xfe410a30
 565 #define CnINT2MSKCR1    0xfe410a34
 566 #define CnINT2MSKCR2    0xfe410a38
 567 #define CnINT2MSKCR3    0xfe410a3c
 568 #define INTMSK2         0xfe410068
 569 #define INTMSKCLR2      0xfe41006c
 570
 571 #define INTDISTCR0      0xfe4100b0
 572 #define INTDISTCR1      0xfe4100b4
 573 #define INT2DISTCR0     0xfe410900
 574 #define INT2DISTCR1     0xfe410904
 575 #define INT2DISTCR2     0xfe410908
 576 #define INT2DISTCR3     0xfe41090c
 577
 578 static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
 579         { CnINTMSK0, CnINTMSKCLR0, 32,
 580           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
 581             INTC_SMP_BALANCING(INTDISTCR0) },
 582         { INTMSK2, INTMSKCLR2, 32,
 583           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 584             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 585             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 586             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 587             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 588             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 589             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 590             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 591         { CnINT2MSKR0, CnINT2MSKCR0 , 32,
 592           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 593             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
 594             INTC_SMP_BALANCING(INT2DISTCR0) },
 595         { CnINT2MSKR1, CnINT2MSKCR1, 32,
 596           { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
 597             DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 598             HUDI1, HUDI0,
 599             DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 600             HPB_0, HPB_1, HPB_2,
 601             SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 602             SCIF1,
 603             TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
 604         { CnINT2MSKR2, CnINT2MSKCR2, 32,
 605           { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
 606             Eth_0, Eth_1,
 607             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 608             PCIeC0_0, PCIeC0_1, PCIeC0_2,
 609             PCIeC1_0, PCIeC1_1, PCIeC1_2,
 610             USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
 611         { CnINT2MSKR3, CnINT2MSKCR3, 32,
 612           { 0, 0, 0, 0, 0, 0,
 613             I2C0, I2C1,
 614             DU, SSI0, SSI1, SSI2, SSI3,
 615             PCIeC2_0, PCIeC2_1, PCIeC2_2,
 616             HAC0, HAC1,
 617             FLCTL, 0,
 618             HSPI, GPIO0, GPIO1, Thermal,
 619             0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
 620 };
 621
 622 static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
 623         { 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 624                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 625         { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
 626         { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
 627                                                  TMU0_2, TMU0_3 } },
 628         { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
 629                                                  TMU1_2, 0 } },
 630         { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
 631                                                  DMAC0_2, DMAC0_3 } },
 632         { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
 633                                                  DMAC0_6, HUDI1 } },
 634         { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
 635                                                  DMAC1_1, DMAC1_2 } },
 636         { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
 637                                                  HPB_1, HPB_2 } },
 638         { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
 639                                                  SCIF0_2, SCIF0_3 } },
 640         { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
 641         { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
 642         { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
 643                                                   Eth_0, Eth_1 } },
 644         { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
 645         { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
 646         { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
 647         { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
 648         { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
 649                                                   PCIeC1_0, PCIeC1_1 } },
 650         { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
 651         { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
 652         { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
 653         { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
 654         { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
 655                                                   PCIeC2_1, PCIeC2_2 } },
 656         { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
 657         { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
 658                                                   GPIO1, Thermal } },
 659         { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
 660         { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
 661         { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
 662           { INTICI7, INTICI6, INTICI5, INTICI4,
 663             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
 664 };
 665
 666 static struct intc_subgroup sh7786_subgroups[] __initdata = {
 667         { 0xfe410c20, 32, SCIF1,
 668           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 669             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
 670 };
 671
 672 static struct intc_desc sh7786_intc_desc __initdata = {
 673         .name           = "sh7786",
 674         .hw             = {
 675                 .vectors        = sh7786_vectors,
 676                 .nr_vectors     = ARRAY_SIZE(sh7786_vectors),
 677                 .mask_regs      = sh7786_mask_registers,
 678                 .nr_mask_regs   = ARRAY_SIZE(sh7786_mask_registers),
 679                 .subgroups      = sh7786_subgroups,
 680                 .nr_subgroups   = ARRAY_SIZE(sh7786_subgroups),
 681                 .prio_regs      = sh7786_prio_registers,
 682                 .nr_prio_regs   = ARRAY_SIZE(sh7786_prio_registers),
 683         },
 684 };
 685
 686 /* Support for external interrupt pins in IRQ mode */
 687 static struct intc_vect vectors_irq0123[] __initdata = {
 688         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
 689         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
 690 };
 691
 692 static struct intc_vect vectors_irq4567[] __initdata = {
 693         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
 694         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
 695 };
 696
 697 static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
 698         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 699                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 700 };
 701
 702 static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
 703         { 0xfe410024, 0, 32, /* INTREQ */
 704           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 705 };
 706
 707 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
 708                              vectors_irq0123, NULL, sh7786_mask_registers,
 709                              sh7786_prio_registers, sh7786_sense_registers,
 710                              sh7786_ack_registers);
 711
 712 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
 713                              vectors_irq4567, NULL, sh7786_mask_registers,
 714                              sh7786_prio_registers, sh7786_sense_registers,
 715                              sh7786_ack_registers);
 716
 717 /* External interrupt pins in IRL mode */
 718
 719 static struct intc_vect vectors_irl0123[] __initdata = {
 720         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 721         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 722         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 723         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 724         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 725         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 726         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 727         INTC_VECT(IRL0_HHHL, 0x3c0),
 728 };
 729
 730 static struct intc_vect vectors_irl4567[] __initdata = {
 731         INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
 732         INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
 733         INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
 734         INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
 735         INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
 736         INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
 737         INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
 738         INTC_VECT(IRL4_HHHL, 0xac0),
 739 };
 740
 741 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
 742                          NULL, sh7786_mask_registers, NULL, NULL);
 743
 744 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
 745                          NULL, sh7786_mask_registers, NULL, NULL);
 746
 747 #define INTC_ICR0       0xfe410000
 748 #define INTC_INTMSK0    CnINTMSK0
 749 #define INTC_INTMSK1    CnINTMSK1
 750 #define INTC_INTMSK2    INTMSK2
 751 #define INTC_INTMSKCLR1 CnINTMSKCLR1
 752 #define INTC_INTMSKCLR2 INTMSKCLR2
 753
 754 void __init plat_irq_setup(void)
 755 {
 756         /* disable IRQ3-0 + IRQ7-4 */
 757         __raw_writel(0xff000000, INTC_INTMSK0);
 758
 759         /* disable IRL3-0 + IRL7-4 */
 760         __raw_writel(0xc0000000, INTC_INTMSK1);
 761         __raw_writel(0xfffefffe, INTC_INTMSK2);
 762
 763         /* select IRL mode for IRL3-0 + IRL7-4 */
 764         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 765
 766         register_intc_controller(&sh7786_intc_desc);
 767 }
 768
 769 void __init plat_irq_setup_pins(int mode)
 770 {
 771         switch (mode) {
 772         case IRQ_MODE_IRQ7654:
 773                 /* select IRQ mode for IRL7-4 */
 774                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 775                 register_intc_controller(&intc_desc_irq4567);
 776                 break;
 777         case IRQ_MODE_IRQ3210:
 778                 /* select IRQ mode for IRL3-0 */
 779                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 780                 register_intc_controller(&intc_desc_irq0123);
 781                 break;
 782         case IRQ_MODE_IRL7654:
 783                 /* enable IRL7-4 but don't provide any masking */
 784                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 785                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 786                 break;
 787         case IRQ_MODE_IRL3210:
 788                 /* enable IRL0-3 but don't provide any masking */
 789                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 790                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 791                 break;
 792         case IRQ_MODE_IRL7654_MASK:
 793                 /* enable IRL7-4 and mask using cpu intc controller */
 794                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 795                 register_intc_controller(&intc_desc_irl4567);
 796                 break;
 797         case IRQ_MODE_IRL3210_MASK:
 798                 /* enable IRL0-3 and mask using cpu intc controller */
 799                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 800                 register_intc_controller(&intc_desc_irl0123);
 801                 break;
 802         default:
 803                 BUG();
 804         }
 805 }
 806
 807 void __init plat_mem_setup(void)
 808 {
 809 }
 810
 811 static int __init sh7786_devices_setup(void)
 812 {
 813         int ret, irq;
 814
 815         sh7786_usb_setup();
 816
 817         /*
 818          * De-mux SCIF1 IRQs if possible
 819          */
 820         irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
 821         if (irq > 0) {
 822                 scif1_demux_resources[1].start =
 823                         intc_irq_lookup(sh7786_intc_desc.name, ERI1);
 824                 scif1_demux_resources[2].start =
 825                         intc_irq_lookup(sh7786_intc_desc.name, RXI1);
 826                 scif1_demux_resources[3].start = irq;
 827                 scif1_demux_resources[4].start =
 828                         intc_irq_lookup(sh7786_intc_desc.name, BRI1);
 829
 830                 scif1_device.resource = scif1_demux_resources;
 831                 scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources);
 832         }
 833
 834         ret = platform_add_devices(sh7786_early_devices,
 835                                    ARRAY_SIZE(sh7786_early_devices));
 836         if (unlikely(ret != 0))
 837                 return ret;
 838
 839         return platform_add_devices(sh7786_devices,
 840                                     ARRAY_SIZE(sh7786_devices));
 841 }
 842 arch_initcall(sh7786_devices_setup);
 843
 844 void __init plat_early_device_setup(void)
 845 {
 846         early_platform_add_devices(sh7786_early_devices,
 847                                    ARRAY_SIZE(sh7786_early_devices));
 848 }