arch/sh/kernel/cpu/sh4a/setup-sh7763.c

   1 /*
   2  * SH7763 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2007  Yoshihiro Shimoda
   6  *  Copyright (C) 2008, 2009  Nobuhiro Iwamatsu
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/io.h>
  17 #include <linux/serial_sci.h>
  18
  19 static struct plat_sci_port scif0_platform_data = {
  20         .mapbase        = 0xffe00000,
  21         .flags          = UPF_BOOT_AUTOCONF,
  22         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  23         .scbrr_algo_id  = SCBRR_ALGO_2,
  24         .type           = PORT_SCIF,
  25         .irqs           = { 40, 40, 40, 40 },
  26 };
  27
  28 static struct platform_device scif0_device = {
  29         .name           = "sh-sci",
  30         .id             = 0,
  31         .dev            = {
  32                 .platform_data  = &scif0_platform_data,
  33         },
  34 };
  35
  36 static struct plat_sci_port scif1_platform_data = {
  37         .mapbase        = 0xffe08000,
  38         .flags          = UPF_BOOT_AUTOCONF,
  39         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  40         .scbrr_algo_id  = SCBRR_ALGO_2,
  41         .type           = PORT_SCIF,
  42         .irqs           = { 76, 76, 76, 76 },
  43 };
  44
  45 static struct platform_device scif1_device = {
  46         .name           = "sh-sci",
  47         .id             = 1,
  48         .dev            = {
  49                 .platform_data  = &scif1_platform_data,
  50         },
  51 };
  52
  53 static struct plat_sci_port scif2_platform_data = {
  54         .mapbase        = 0xffe10000,
  55         .flags          = UPF_BOOT_AUTOCONF,
  56         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  57         .scbrr_algo_id  = SCBRR_ALGO_2,
  58         .type           = PORT_SCIF,
  59         .irqs           = { 104, 104, 104, 104 },
  60 };
  61
  62 static struct platform_device scif2_device = {
  63         .name           = "sh-sci",
  64         .id             = 2,
  65         .dev            = {
  66                 .platform_data  = &scif2_platform_data,
  67         },
  68 };
  69
  70 static struct resource rtc_resources[] = {
  71         [0] = {
  72                 .start  = 0xffe80000,
  73                 .end    = 0xffe80000 + 0x58 - 1,
  74                 .flags  = IORESOURCE_IO,
  75         },
  76         [1] = {
  77                 /* Shared Period/Carry/Alarm IRQ */
  78                 .start  = 20,
  79                 .flags  = IORESOURCE_IRQ,
  80         },
  81 };
  82
  83 static struct platform_device rtc_device = {
  84         .name           = "sh-rtc",
  85         .id             = -1,
  86         .num_resources  = ARRAY_SIZE(rtc_resources),
  87         .resource       = rtc_resources,
  88 };
  89
  90 static struct resource usb_ohci_resources[] = {
  91         [0] = {
  92                 .start  = 0xffec8000,
  93                 .end    = 0xffec80ff,
  94                 .flags  = IORESOURCE_MEM,
  95         },
  96         [1] = {
  97                 .start  = 83,
  98                 .end    = 83,
  99                 .flags  = IORESOURCE_IRQ,
 100         },
 101 };
 102
 103 static u64 usb_ohci_dma_mask = 0xffffffffUL;
 104 static struct platform_device usb_ohci_device = {
 105         .name           = "sh_ohci",
 106         .id             = -1,
 107         .dev = {
 108                 .dma_mask               = &usb_ohci_dma_mask,
 109                 .coherent_dma_mask      = 0xffffffff,
 110         },
 111         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 112         .resource       = usb_ohci_resources,
 113 };
 114
 115 static struct resource usbf_resources[] = {
 116         [0] = {
 117                 .start  = 0xffec0000,
 118                 .end    = 0xffec00ff,
 119                 .flags  = IORESOURCE_MEM,
 120         },
 121         [1] = {
 122                 .start  = 84,
 123                 .end    = 84,
 124                 .flags  = IORESOURCE_IRQ,
 125         },
 126 };
 127
 128 static struct platform_device usbf_device = {
 129         .name           = "sh_udc",
 130         .id             = -1,
 131         .dev = {
 132                 .dma_mask               = NULL,
 133                 .coherent_dma_mask      = 0xffffffff,
 134         },
 135         .num_resources  = ARRAY_SIZE(usbf_resources),
 136         .resource       = usbf_resources,
 137 };
 138
 139 static struct sh_timer_config tmu0_platform_data = {
 140         .channel_offset = 0x04,
 141         .timer_bit = 0,
 142         .clockevent_rating = 200,
 143 };
 144
 145 static struct resource tmu0_resources[] = {
 146         [0] = {
 147                 .start  = 0xffd80008,
 148                 .end    = 0xffd80013,
 149                 .flags  = IORESOURCE_MEM,
 150         },
 151         [1] = {
 152                 .start  = 28,
 153                 .flags  = IORESOURCE_IRQ,
 154         },
 155 };
 156
 157 static struct platform_device tmu0_device = {
 158         .name           = "sh_tmu",
 159         .id             = 0,
 160         .dev = {
 161                 .platform_data  = &tmu0_platform_data,
 162         },
 163         .resource       = tmu0_resources,
 164         .num_resources  = ARRAY_SIZE(tmu0_resources),
 165 };
 166
 167 static struct sh_timer_config tmu1_platform_data = {
 168         .channel_offset = 0x10,
 169         .timer_bit = 1,
 170         .clocksource_rating = 200,
 171 };
 172
 173 static struct resource tmu1_resources[] = {
 174         [0] = {
 175                 .start  = 0xffd80014,
 176                 .end    = 0xffd8001f,
 177                 .flags  = IORESOURCE_MEM,
 178         },
 179         [1] = {
 180                 .start  = 29,
 181                 .flags  = IORESOURCE_IRQ,
 182         },
 183 };
 184
 185 static struct platform_device tmu1_device = {
 186         .name           = "sh_tmu",
 187         .id             = 1,
 188         .dev = {
 189                 .platform_data  = &tmu1_platform_data,
 190         },
 191         .resource       = tmu1_resources,
 192         .num_resources  = ARRAY_SIZE(tmu1_resources),
 193 };
 194
 195 static struct sh_timer_config tmu2_platform_data = {
 196         .channel_offset = 0x1c,
 197         .timer_bit = 2,
 198 };
 199
 200 static struct resource tmu2_resources[] = {
 201         [0] = {
 202                 .start  = 0xffd80020,
 203                 .end    = 0xffd8002f,
 204                 .flags  = IORESOURCE_MEM,
 205         },
 206         [1] = {
 207                 .start  = 30,
 208                 .flags  = IORESOURCE_IRQ,
 209         },
 210 };
 211
 212 static struct platform_device tmu2_device = {
 213         .name           = "sh_tmu",
 214         .id             = 2,
 215         .dev = {
 216                 .platform_data  = &tmu2_platform_data,
 217         },
 218         .resource       = tmu2_resources,
 219         .num_resources  = ARRAY_SIZE(tmu2_resources),
 220 };
 221
 222 static struct sh_timer_config tmu3_platform_data = {
 223         .channel_offset = 0x04,
 224         .timer_bit = 0,
 225 };
 226
 227 static struct resource tmu3_resources[] = {
 228         [0] = {
 229                 .start  = 0xffd88008,
 230                 .end    = 0xffd88013,
 231                 .flags  = IORESOURCE_MEM,
 232         },
 233         [1] = {
 234                 .start  = 96,
 235                 .flags  = IORESOURCE_IRQ,
 236         },
 237 };
 238
 239 static struct platform_device tmu3_device = {
 240         .name           = "sh_tmu",
 241         .id             = 3,
 242         .dev = {
 243                 .platform_data  = &tmu3_platform_data,
 244         },
 245         .resource       = tmu3_resources,
 246         .num_resources  = ARRAY_SIZE(tmu3_resources),
 247 };
 248
 249 static struct sh_timer_config tmu4_platform_data = {
 250         .channel_offset = 0x10,
 251         .timer_bit = 1,
 252 };
 253
 254 static struct resource tmu4_resources[] = {
 255         [0] = {
 256                 .start  = 0xffd88014,
 257                 .end    = 0xffd8801f,
 258                 .flags  = IORESOURCE_MEM,
 259         },
 260         [1] = {
 261                 .start  = 97,
 262                 .flags  = IORESOURCE_IRQ,
 263         },
 264 };
 265
 266 static struct platform_device tmu4_device = {
 267         .name           = "sh_tmu",
 268         .id             = 4,
 269         .dev = {
 270                 .platform_data  = &tmu4_platform_data,
 271         },
 272         .resource       = tmu4_resources,
 273         .num_resources  = ARRAY_SIZE(tmu4_resources),
 274 };
 275
 276 static struct sh_timer_config tmu5_platform_data = {
 277         .channel_offset = 0x1c,
 278         .timer_bit = 2,
 279 };
 280
 281 static struct resource tmu5_resources[] = {
 282         [0] = {
 283                 .start  = 0xffd88020,
 284                 .end    = 0xffd8802b,
 285                 .flags  = IORESOURCE_MEM,
 286         },
 287         [1] = {
 288                 .start  = 98,
 289                 .flags  = IORESOURCE_IRQ,
 290         },
 291 };
 292
 293 static struct platform_device tmu5_device = {
 294         .name           = "sh_tmu",
 295         .id             = 5,
 296         .dev = {
 297                 .platform_data  = &tmu5_platform_data,
 298         },
 299         .resource       = tmu5_resources,
 300         .num_resources  = ARRAY_SIZE(tmu5_resources),
 301 };
 302
 303 static struct platform_device *sh7763_devices[] __initdata = {
 304         &scif0_device,
 305         &scif1_device,
 306         &scif2_device,
 307         &tmu0_device,
 308         &tmu1_device,
 309         &tmu2_device,
 310         &tmu3_device,
 311         &tmu4_device,
 312         &tmu5_device,
 313         &rtc_device,
 314         &usb_ohci_device,
 315         &usbf_device,
 316 };
 317
 318 static int __init sh7763_devices_setup(void)
 319 {
 320         return platform_add_devices(sh7763_devices,
 321                                     ARRAY_SIZE(sh7763_devices));
 322 }
 323 arch_initcall(sh7763_devices_setup);
 324
 325 static struct platform_device *sh7763_early_devices[] __initdata = {
 326         &scif0_device,
 327         &scif1_device,
 328         &scif2_device,
 329         &tmu0_device,
 330         &tmu1_device,
 331         &tmu2_device,
 332         &tmu3_device,
 333         &tmu4_device,
 334         &tmu5_device,
 335 };
 336
 337 void __init plat_early_device_setup(void)
 338 {
 339         early_platform_add_devices(sh7763_early_devices,
 340                                    ARRAY_SIZE(sh7763_early_devices));
 341 }
 342
 343 enum {
 344         UNUSED = 0,
 345
 346         /* interrupt sources */
 347
 348         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 349         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 350         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 351         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 352
 353         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 354         RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 355         HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
 356         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 357         STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
 358         USBH, USBF, TPU, PCC, MMCIF, SIM,
 359         TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
 360         SCIF2, GPIO,
 361
 362         /* interrupt groups */
 363
 364         TMU012, TMU345,
 365 };
 366
 367 static struct intc_vect vectors[] __initdata = {
 368         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 369         INTC_VECT(RTC, 0x4c0),
 370         INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
 371         INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
 372         INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
 373         INTC_VECT(LCDC, 0x620),
 374         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 375         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 376         INTC_VECT(DMAC, 0x6c0),
 377         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 378         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 379         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 380         INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
 381         INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
 382         INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
 383         INTC_VECT(HAC, 0x980),
 384         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 385         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 386         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 387         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 388         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 389         INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
 390         INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
 391         INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
 392         INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
 393         INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
 394         INTC_VECT(USBF, 0xca0),
 395         INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
 396         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 397         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 398         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 399         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 400         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 401         INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
 402         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 403         INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
 404         INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
 405         INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
 406         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 407         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 408 };
 409
 410 static struct intc_group groups[] __initdata = {
 411         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 412         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 413 };
 414
 415 static struct intc_mask_reg mask_registers[] __initdata = {
 416         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 417           { 0, 0, 0, 0, 0, 0, GPIO, 0,
 418             SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 419             PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
 420             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 421         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 422           { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
 423             0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
 424             PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
 425             LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
 426 };
 427
 428 static struct intc_prio_reg prio_registers[] __initdata = {
 429         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 430                                                  TMU2, TMU2_TICPI } },
 431         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 432         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 433         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
 434         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 435                                                  PCISERR, PCIINTA } },
 436         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 437                                                  PCIINTD, PCIC5 } },
 438         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
 439         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
 440         { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
 441         { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
 442         { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
 443         { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
 444         { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
 445         { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
 446 };
 447
 448 static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
 449                          mask_registers, prio_registers, NULL);
 450
 451 /* Support for external interrupt pins in IRQ mode */
 452 static struct intc_vect irq_vectors[] __initdata = {
 453         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 454         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 455         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 456         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 457 };
 458
 459 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 460         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 461           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 462 };
 463
 464 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 465         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 466                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 467 };
 468
 469 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 470         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 471                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 472 };
 473
 474 static struct intc_mask_reg irq_ack_registers[] __initdata = {
 475         { 0xffd00024, 0, 32, /* INTREQ */
 476           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 477 };
 478
 479 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
 480                              NULL, irq_mask_registers, irq_prio_registers,
 481                              irq_sense_registers, irq_ack_registers);
 482
 483
 484 /* External interrupt pins in IRL mode */
 485 static struct intc_vect irl_vectors[] __initdata = {
 486         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 487         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 488         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 489         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 490         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 491         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 492         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 493         INTC_VECT(IRL_HHHL, 0x3c0),
 494 };
 495
 496 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 497         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 498           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 499             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 500             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 501             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 502 };
 503
 504 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 505         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 506           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 507             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 508             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 509             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 510             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 511 };
 512
 513 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
 514                         NULL, irl7654_mask_registers, NULL, NULL);
 515
 516 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
 517                         NULL, irl3210_mask_registers, NULL, NULL);
 518
 519 #define INTC_ICR0       0xffd00000
 520 #define INTC_INTMSK0    0xffd00044
 521 #define INTC_INTMSK1    0xffd00048
 522 #define INTC_INTMSK2    0xffd40080
 523 #define INTC_INTMSKCLR1 0xffd00068
 524 #define INTC_INTMSKCLR2 0xffd40084
 525
 526 void __init plat_irq_setup(void)
 527 {
 528         /* disable IRQ7-0 */
 529         __raw_writel(0xff000000, INTC_INTMSK0);
 530
 531         /* disable IRL3-0 + IRL7-4 */
 532         __raw_writel(0xc0000000, INTC_INTMSK1);
 533         __raw_writel(0xfffefffe, INTC_INTMSK2);
 534
 535         register_intc_controller(&intc_desc);
 536 }
 537
 538 void __init plat_irq_setup_pins(int mode)
 539 {
 540         switch (mode) {
 541         case IRQ_MODE_IRQ:
 542                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 543                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 544                 register_intc_controller(&intc_irq_desc);
 545                 break;
 546         case IRQ_MODE_IRL7654:
 547                 /* enable IRL7-4 but don't provide any masking */
 548                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 549                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 550                 break;
 551         case IRQ_MODE_IRL3210:
 552                 /* enable IRL0-3 but don't provide any masking */
 553                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 554                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 555                 break;
 556         case IRQ_MODE_IRL7654_MASK:
 557                 /* enable IRL7-4 and mask using cpu intc controller */
 558                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 559                 register_intc_controller(&intc_irl7654_desc);
 560                 break;
 561         case IRQ_MODE_IRL3210_MASK:
 562                 /* enable IRL0-3 and mask using cpu intc controller */
 563                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 564                 register_intc_controller(&intc_irl3210_desc);
 565                 break;
 566         default:
 567                 BUG();
 568         }
 569 }