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usb: gadget: r8a66597-udc: fix cannot connect after rmmod gadget driver
[linux/fpc-iii.git] / drivers / usb / gadget / ci13xxx_udc.c
blob1265a8502ea0fe90348bdcdfa41b2f4df337c02d
1 /*
2 * ci13xxx_udc.c - MIPS USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 /*
14 * Description: MIPS USB IP core family device controller
15 * Currently it only supports IP part number CI13412
16 *
17 * This driver is composed of several blocks:
18 * - HW: hardware interface
19 * - DBG: debug facilities (optional)
20 * - UTIL: utilities
21 * - ISR: interrupts handling
22 * - ENDPT: endpoint operations (Gadget API)
23 * - GADGET: gadget operations (Gadget API)
24 * - BUS: bus glue code, bus abstraction layer
25 *
26 * Compile Options
27 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
28 * - STALL_IN: non-empty bulk-in pipes cannot be halted
29 * if defined mass storage compliance succeeds but with warnings
30 * => case 4: Hi > Dn
31 * => case 5: Hi > Di
32 * => case 8: Hi <> Do
33 * if undefined usbtest 13 fails
34 * - TRACE: enable function tracing (depends on DEBUG)
35 *
36 * Main Features
37 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
38 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
39 * - Normal & LPM support
40 *
41 * USBTEST Report
42 * - OK: 0-12, 13 (STALL_IN defined) & 14
43 * - Not Supported: 15 & 16 (ISO)
44 *
45 * TODO List
46 * - OTG
47 * - Isochronous & Interrupt Traffic
48 * - Handle requests which spawns into several TDs
49 * - GET_STATUS(device) - always reports 0
50 * - Gadget API (majority of optional features)
51 * - Suspend & Remote Wakeup
52 */
53 #include <linux/delay.h>
54 #include <linux/device.h>
55 #include <linux/dmapool.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/init.h>
58 #include <linux/interrupt.h>
59 #include <linux/io.h>
60 #include <linux/irq.h>
61 #include <linux/kernel.h>
62 #include <linux/slab.h>
63 #include <linux/pm_runtime.h>
64 #include <linux/usb/ch9.h>
65 #include <linux/usb/gadget.h>
66 #include <linux/usb/otg.h>
67
68 #include "ci13xxx_udc.h"
69
70
71 /******************************************************************************
72 * DEFINE
73 *****************************************************************************/
74 /* ctrl register bank access */
75 static DEFINE_SPINLOCK(udc_lock);
76
77 /* control endpoint description */
78 static const struct usb_endpoint_descriptor
79 ctrl_endpt_out_desc = {
80 .bLength = USB_DT_ENDPOINT_SIZE,
81 .bDescriptorType = USB_DT_ENDPOINT,
82
83 .bEndpointAddress = USB_DIR_OUT,
84 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
85 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
86 };
87
88 static const struct usb_endpoint_descriptor
89 ctrl_endpt_in_desc = {
90 .bLength = USB_DT_ENDPOINT_SIZE,
91 .bDescriptorType = USB_DT_ENDPOINT,
92
93 .bEndpointAddress = USB_DIR_IN,
94 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
95 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
96 };
97
98 /* UDC descriptor */
99 static struct ci13xxx *_udc;
100
101 /* Interrupt statistics */
102 #define ISR_MASK 0x1F
103 static struct {
104 u32 test;
105 u32 ui;
106 u32 uei;
107 u32 pci;
108 u32 uri;
109 u32 sli;
110 u32 none;
111 struct {
112 u32 cnt;
113 u32 buf[ISR_MASK+1];
114 u32 idx;
115 } hndl;
116 } isr_statistics;
117
118 /**
119 * ffs_nr: find first (least significant) bit set
120 * @x: the word to search
121 *
122 * This function returns bit number (instead of position)
123 */
124 static int ffs_nr(u32 x)
125 {
126 int n = ffs(x);
127
128 return n ? n-1 : 32;
129 }
130
131 /******************************************************************************
132 * HW block
133 *****************************************************************************/
134 /* register bank descriptor */
135 static struct {
136 unsigned lpm; /* is LPM? */
137 void __iomem *abs; /* bus map offset */
138 void __iomem *cap; /* bus map offset + CAP offset + CAP data */
139 size_t size; /* bank size */
140 } hw_bank;
141
142 /* MSM specific */
143 #define ABS_AHBBURST (0x0090UL)
144 #define ABS_AHBMODE (0x0098UL)
145 /* UDC register map */
146 #define ABS_CAPLENGTH (0x100UL)
147 #define ABS_HCCPARAMS (0x108UL)
148 #define ABS_DCCPARAMS (0x124UL)
149 #define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
150 /* offset to CAPLENTGH (addr + data) */
151 #define CAP_USBCMD (0x000UL)
152 #define CAP_USBSTS (0x004UL)
153 #define CAP_USBINTR (0x008UL)
154 #define CAP_DEVICEADDR (0x014UL)
155 #define CAP_ENDPTLISTADDR (0x018UL)
156 #define CAP_PORTSC (0x044UL)
157 #define CAP_DEVLC (0x084UL)
158 #define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
159 #define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
160 #define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
161 #define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
162 #define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
163 #define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
164 #define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
165 #define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
166
167 /* maximum number of enpoints: valid only after hw_device_reset() */
168 static unsigned hw_ep_max;
169
170 /**
171 * hw_ep_bit: calculates the bit number
172 * @num: endpoint number
173 * @dir: endpoint direction
174 *
175 * This function returns bit number
176 */
177 static inline int hw_ep_bit(int num, int dir)
178 {
179 return num + (dir ? 16 : 0);
180 }
181
182 /**
183 * hw_aread: reads from register bitfield
184 * @addr: address relative to bus map
185 * @mask: bitfield mask
186 *
187 * This function returns register bitfield data
188 */
189 static u32 hw_aread(u32 addr, u32 mask)
190 {
191 return ioread32(addr + hw_bank.abs) & mask;
192 }
193
194 /**
195 * hw_awrite: writes to register bitfield
196 * @addr: address relative to bus map
197 * @mask: bitfield mask
198 * @data: new data
199 */
200 static void hw_awrite(u32 addr, u32 mask, u32 data)
201 {
202 iowrite32(hw_aread(addr, ~mask) | (data & mask),
203 addr + hw_bank.abs);
204 }
205
206 /**
207 * hw_cread: reads from register bitfield
208 * @addr: address relative to CAP offset plus content
209 * @mask: bitfield mask
210 *
211 * This function returns register bitfield data
212 */
213 static u32 hw_cread(u32 addr, u32 mask)
214 {
215 return ioread32(addr + hw_bank.cap) & mask;
216 }
217
218 /**
219 * hw_cwrite: writes to register bitfield
220 * @addr: address relative to CAP offset plus content
221 * @mask: bitfield mask
222 * @data: new data
223 */
224 static void hw_cwrite(u32 addr, u32 mask, u32 data)
225 {
226 iowrite32(hw_cread(addr, ~mask) | (data & mask),
227 addr + hw_bank.cap);
228 }
229
230 /**
231 * hw_ctest_and_clear: tests & clears register bitfield
232 * @addr: address relative to CAP offset plus content
233 * @mask: bitfield mask
234 *
235 * This function returns register bitfield data
236 */
237 static u32 hw_ctest_and_clear(u32 addr, u32 mask)
238 {
239 u32 reg = hw_cread(addr, mask);
240
241 iowrite32(reg, addr + hw_bank.cap);
242 return reg;
243 }
244
245 /**
246 * hw_ctest_and_write: tests & writes register bitfield
247 * @addr: address relative to CAP offset plus content
248 * @mask: bitfield mask
249 * @data: new data
250 *
251 * This function returns register bitfield data
252 */
253 static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
254 {
255 u32 reg = hw_cread(addr, ~0);
256
257 iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
258 return (reg & mask) >> ffs_nr(mask);
259 }
260
261 static int hw_device_init(void __iomem *base)
262 {
263 u32 reg;
264
265 /* bank is a module variable */
266 hw_bank.abs = base;
267
268 hw_bank.cap = hw_bank.abs;
269 hw_bank.cap += ABS_CAPLENGTH;
270 hw_bank.cap += ioread8(hw_bank.cap);
271
272 reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
273 hw_bank.lpm = reg;
274 hw_bank.size = hw_bank.cap - hw_bank.abs;
275 hw_bank.size += CAP_LAST;
276 hw_bank.size /= sizeof(u32);
277
278 reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
279 hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
280
281 if (hw_ep_max == 0 || hw_ep_max > ENDPT_MAX)
282 return -ENODEV;
283
284 /* setup lock mode ? */
285
286 /* ENDPTSETUPSTAT is '0' by default */
287
288 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
289
290 return 0;
291 }
292 /**
293 * hw_device_reset: resets chip (execute without interruption)
294 * @base: register base address
295 *
296 * This function returns an error code
297 */
298 static int hw_device_reset(struct ci13xxx *udc)
299 {
300 /* should flush & stop before reset */
301 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
302 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
303
304 hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
305 while (hw_cread(CAP_USBCMD, USBCMD_RST))
306 udelay(10); /* not RTOS friendly */
307
308
309 if (udc->udc_driver->notify_event)
310 udc->udc_driver->notify_event(udc,
311 CI13XXX_CONTROLLER_RESET_EVENT);
312
313 if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
314 hw_cwrite(CAP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
315
316 /* USBMODE should be configured step by step */
317 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
318 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
319 hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
320
321 if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
322 pr_err("cannot enter in device mode");
323 pr_err("lpm = %i", hw_bank.lpm);
324 return -ENODEV;
325 }
326
327 return 0;
328 }
329
330 /**
331 * hw_device_state: enables/disables interrupts & starts/stops device (execute
332 * without interruption)
333 * @dma: 0 => disable, !0 => enable and set dma engine
334 *
335 * This function returns an error code
336 */
337 static int hw_device_state(u32 dma)
338 {
339 if (dma) {
340 hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
341 /* interrupt, error, port change, reset, sleep/suspend */
342 hw_cwrite(CAP_USBINTR, ~0,
343 USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
344 hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
345 } else {
346 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
347 hw_cwrite(CAP_USBINTR, ~0, 0);
348 }
349 return 0;
350 }
351
352 /**
353 * hw_ep_flush: flush endpoint fifo (execute without interruption)
354 * @num: endpoint number
355 * @dir: endpoint direction
356 *
357 * This function returns an error code
358 */
359 static int hw_ep_flush(int num, int dir)
360 {
361 int n = hw_ep_bit(num, dir);
362
363 do {
364 /* flush any pending transfer */
365 hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
366 while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
367 cpu_relax();
368 } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
369
370 return 0;
371 }
372
373 /**
374 * hw_ep_disable: disables endpoint (execute without interruption)
375 * @num: endpoint number
376 * @dir: endpoint direction
377 *
378 * This function returns an error code
379 */
380 static int hw_ep_disable(int num, int dir)
381 {
382 hw_ep_flush(num, dir);
383 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
384 dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
385 return 0;
386 }
387
388 /**
389 * hw_ep_enable: enables endpoint (execute without interruption)
390 * @num: endpoint number
391 * @dir: endpoint direction
392 * @type: endpoint type
393 *
394 * This function returns an error code
395 */
396 static int hw_ep_enable(int num, int dir, int type)
397 {
398 u32 mask, data;
399
400 if (dir) {
401 mask = ENDPTCTRL_TXT; /* type */
402 data = type << ffs_nr(mask);
403
404 mask |= ENDPTCTRL_TXS; /* unstall */
405 mask |= ENDPTCTRL_TXR; /* reset data toggle */
406 data |= ENDPTCTRL_TXR;
407 mask |= ENDPTCTRL_TXE; /* enable */
408 data |= ENDPTCTRL_TXE;
409 } else {
410 mask = ENDPTCTRL_RXT; /* type */
411 data = type << ffs_nr(mask);
412
413 mask |= ENDPTCTRL_RXS; /* unstall */
414 mask |= ENDPTCTRL_RXR; /* reset data toggle */
415 data |= ENDPTCTRL_RXR;
416 mask |= ENDPTCTRL_RXE; /* enable */
417 data |= ENDPTCTRL_RXE;
418 }
419 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
420 return 0;
421 }
422
423 /**
424 * hw_ep_get_halt: return endpoint halt status
425 * @num: endpoint number
426 * @dir: endpoint direction
427 *
428 * This function returns 1 if endpoint halted
429 */
430 static int hw_ep_get_halt(int num, int dir)
431 {
432 u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
433
434 return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
435 }
436
437 /**
438 * hw_test_and_clear_setup_status: test & clear setup status (execute without
439 * interruption)
440 * @n: bit number (endpoint)
441 *
442 * This function returns setup status
443 */
444 static int hw_test_and_clear_setup_status(int n)
445 {
446 return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
447 }
448
449 /**
450 * hw_ep_prime: primes endpoint (execute without interruption)
451 * @num: endpoint number
452 * @dir: endpoint direction
453 * @is_ctrl: true if control endpoint
454 *
455 * This function returns an error code
456 */
457 static int hw_ep_prime(int num, int dir, int is_ctrl)
458 {
459 int n = hw_ep_bit(num, dir);
460
461 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
462 return -EAGAIN;
463
464 hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
465
466 while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
467 cpu_relax();
468 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
469 return -EAGAIN;
470
471 /* status shoult be tested according with manual but it doesn't work */
472 return 0;
473 }
474
475 /**
476 * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
477 * without interruption)
478 * @num: endpoint number
479 * @dir: endpoint direction
480 * @value: true => stall, false => unstall
481 *
482 * This function returns an error code
483 */
484 static int hw_ep_set_halt(int num, int dir, int value)
485 {
486 if (value != 0 && value != 1)
487 return -EINVAL;
488
489 do {
490 u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
491 u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
492 u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
493
494 /* data toggle - reserved for EP0 but it's in ESS */
495 hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
496
497 } while (value != hw_ep_get_halt(num, dir));
498
499 return 0;
500 }
501
502 /**
503 * hw_intr_clear: disables interrupt & clears interrupt status (execute without
504 * interruption)
505 * @n: interrupt bit
506 *
507 * This function returns an error code
508 */
509 static int hw_intr_clear(int n)
510 {
511 if (n >= REG_BITS)
512 return -EINVAL;
513
514 hw_cwrite(CAP_USBINTR, BIT(n), 0);
515 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
516 return 0;
517 }
518
519 /**
520 * hw_intr_force: enables interrupt & forces interrupt status (execute without
521 * interruption)
522 * @n: interrupt bit
523 *
524 * This function returns an error code
525 */
526 static int hw_intr_force(int n)
527 {
528 if (n >= REG_BITS)
529 return -EINVAL;
530
531 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
532 hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
533 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
534 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
535 return 0;
536 }
537
538 /**
539 * hw_is_port_high_speed: test if port is high speed
540 *
541 * This function returns true if high speed port
542 */
543 static int hw_port_is_high_speed(void)
544 {
545 return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
546 hw_cread(CAP_PORTSC, PORTSC_HSP);
547 }
548
549 /**
550 * hw_port_test_get: reads port test mode value
551 *
552 * This function returns port test mode value
553 */
554 static u8 hw_port_test_get(void)
555 {
556 return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
557 }
558
559 /**
560 * hw_port_test_set: writes port test mode (execute without interruption)
561 * @mode: new value
562 *
563 * This function returns an error code
564 */
565 static int hw_port_test_set(u8 mode)
566 {
567 const u8 TEST_MODE_MAX = 7;
568
569 if (mode > TEST_MODE_MAX)
570 return -EINVAL;
571
572 hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
573 return 0;
574 }
575
576 /**
577 * hw_read_intr_enable: returns interrupt enable register
578 *
579 * This function returns register data
580 */
581 static u32 hw_read_intr_enable(void)
582 {
583 return hw_cread(CAP_USBINTR, ~0);
584 }
585
586 /**
587 * hw_read_intr_status: returns interrupt status register
588 *
589 * This function returns register data
590 */
591 static u32 hw_read_intr_status(void)
592 {
593 return hw_cread(CAP_USBSTS, ~0);
594 }
595
596 /**
597 * hw_register_read: reads all device registers (execute without interruption)
598 * @buf: destination buffer
599 * @size: buffer size
600 *
601 * This function returns number of registers read
602 */
603 static size_t hw_register_read(u32 *buf, size_t size)
604 {
605 unsigned i;
606
607 if (size > hw_bank.size)
608 size = hw_bank.size;
609
610 for (i = 0; i < size; i++)
611 buf[i] = hw_aread(i * sizeof(u32), ~0);
612
613 return size;
614 }
615
616 /**
617 * hw_register_write: writes to register
618 * @addr: register address
619 * @data: register value
620 *
621 * This function returns an error code
622 */
623 static int hw_register_write(u16 addr, u32 data)
624 {
625 /* align */
626 addr /= sizeof(u32);
627
628 if (addr >= hw_bank.size)
629 return -EINVAL;
630
631 /* align */
632 addr *= sizeof(u32);
633
634 hw_awrite(addr, ~0, data);
635 return 0;
636 }
637
638 /**
639 * hw_test_and_clear_complete: test & clear complete status (execute without
640 * interruption)
641 * @n: bit number (endpoint)
642 *
643 * This function returns complete status
644 */
645 static int hw_test_and_clear_complete(int n)
646 {
647 return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
648 }
649
650 /**
651 * hw_test_and_clear_intr_active: test & clear active interrupts (execute
652 * without interruption)
653 *
654 * This function returns active interrutps
655 */
656 static u32 hw_test_and_clear_intr_active(void)
657 {
658 u32 reg = hw_read_intr_status() & hw_read_intr_enable();
659
660 hw_cwrite(CAP_USBSTS, ~0, reg);
661 return reg;
662 }
663
664 /**
665 * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
666 * interruption)
667 *
668 * This function returns guard value
669 */
670 static int hw_test_and_clear_setup_guard(void)
671 {
672 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
673 }
674
675 /**
676 * hw_test_and_set_setup_guard: test & set setup guard (execute without
677 * interruption)
678 *
679 * This function returns guard value
680 */
681 static int hw_test_and_set_setup_guard(void)
682 {
683 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
684 }
685
686 /**
687 * hw_usb_set_address: configures USB address (execute without interruption)
688 * @value: new USB address
689 *
690 * This function returns an error code
691 */
692 static int hw_usb_set_address(u8 value)
693 {
694 /* advance */
695 hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
696 value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
697 return 0;
698 }
699
700 /**
701 * hw_usb_reset: restart device after a bus reset (execute without
702 * interruption)
703 *
704 * This function returns an error code
705 */
706 static int hw_usb_reset(void)
707 {
708 hw_usb_set_address(0);
709
710 /* ESS flushes only at end?!? */
711 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
712
713 /* clear setup token semaphores */
714 hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
715
716 /* clear complete status */
717 hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
718
719 /* wait until all bits cleared */
720 while (hw_cread(CAP_ENDPTPRIME, ~0))
721 udelay(10); /* not RTOS friendly */
722
723 /* reset all endpoints ? */
724
725 /* reset internal status and wait for further instructions
726 no need to verify the port reset status (ESS does it) */
727
728 return 0;
729 }
730
731 /******************************************************************************
732 * DBG block
733 *****************************************************************************/
734 /**
735 * show_device: prints information about device capabilities and status
736 *
737 * Check "device.h" for details
738 */
739 static ssize_t show_device(struct device *dev, struct device_attribute *attr,
740 char *buf)
741 {
742 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
743 struct usb_gadget *gadget = &udc->gadget;
744 int n = 0;
745
746 dbg_trace("[%s] %p\n", __func__, buf);
747 if (attr == NULL || buf == NULL) {
748 dev_err(dev, "[%s] EINVAL\n", __func__);
749 return 0;
750 }
751
752 n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
753 gadget->speed);
754 n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
755 gadget->is_dualspeed);
756 n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
757 gadget->is_otg);
758 n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
759 gadget->is_a_peripheral);
760 n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
761 gadget->b_hnp_enable);
762 n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
763 gadget->a_hnp_support);
764 n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
765 gadget->a_alt_hnp_support);
766 n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
767 (gadget->name ? gadget->name : ""));
768
769 return n;
770 }
771 static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
772
773 /**
774 * show_driver: prints information about attached gadget (if any)
775 *
776 * Check "device.h" for details
777 */
778 static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
779 char *buf)
780 {
781 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
782 struct usb_gadget_driver *driver = udc->driver;
783 int n = 0;
784
785 dbg_trace("[%s] %p\n", __func__, buf);
786 if (attr == NULL || buf == NULL) {
787 dev_err(dev, "[%s] EINVAL\n", __func__);
788 return 0;
789 }
790
791 if (driver == NULL)
792 return scnprintf(buf, PAGE_SIZE,
793 "There is no gadget attached!\n");
794
795 n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
796 (driver->function ? driver->function : ""));
797 n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
798 driver->speed);
799
800 return n;
801 }
802 static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
803
804 /* Maximum event message length */
805 #define DBG_DATA_MSG 64UL
806
807 /* Maximum event messages */
808 #define DBG_DATA_MAX 128UL
809
810 /* Event buffer descriptor */
811 static struct {
812 char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
813 unsigned idx; /* index */
814 unsigned tty; /* print to console? */
815 rwlock_t lck; /* lock */
816 } dbg_data = {
817 .idx = 0,
818 .tty = 0,
819 .lck = __RW_LOCK_UNLOCKED(lck)
820 };
821
822 /**
823 * dbg_dec: decrements debug event index
824 * @idx: buffer index
825 */
826 static void dbg_dec(unsigned *idx)
827 {
828 *idx = (*idx - 1) & (DBG_DATA_MAX-1);
829 }
830
831 /**
832 * dbg_inc: increments debug event index
833 * @idx: buffer index
834 */
835 static void dbg_inc(unsigned *idx)
836 {
837 *idx = (*idx + 1) & (DBG_DATA_MAX-1);
838 }
839
840 /**
841 * dbg_print: prints the common part of the event
842 * @addr: endpoint address
843 * @name: event name
844 * @status: status
845 * @extra: extra information
846 */
847 static void dbg_print(u8 addr, const char *name, int status, const char *extra)
848 {
849 struct timeval tval;
850 unsigned int stamp;
851 unsigned long flags;
852
853 write_lock_irqsave(&dbg_data.lck, flags);
854
855 do_gettimeofday(&tval);
856 stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
857 stamp = stamp * 1000000 + tval.tv_usec;
858
859 scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
860 "%04X\t? %02X %-7.7s %4i ?\t%s\n",
861 stamp, addr, name, status, extra);
862
863 dbg_inc(&dbg_data.idx);
864
865 write_unlock_irqrestore(&dbg_data.lck, flags);
866
867 if (dbg_data.tty != 0)
868 pr_notice("%04X\t? %02X %-7.7s %4i ?\t%s\n",
869 stamp, addr, name, status, extra);
870 }
871
872 /**
873 * dbg_done: prints a DONE event
874 * @addr: endpoint address
875 * @td: transfer descriptor
876 * @status: status
877 */
878 static void dbg_done(u8 addr, const u32 token, int status)
879 {
880 char msg[DBG_DATA_MSG];
881
882 scnprintf(msg, sizeof(msg), "%d %02X",
883 (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
884 (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
885 dbg_print(addr, "DONE", status, msg);
886 }
887
888 /**
889 * dbg_event: prints a generic event
890 * @addr: endpoint address
891 * @name: event name
892 * @status: status
893 */
894 static void dbg_event(u8 addr, const char *name, int status)
895 {
896 if (name != NULL)
897 dbg_print(addr, name, status, "");
898 }
899
900 /*
901 * dbg_queue: prints a QUEUE event
902 * @addr: endpoint address
903 * @req: USB request
904 * @status: status
905 */
906 static void dbg_queue(u8 addr, const struct usb_request *req, int status)
907 {
908 char msg[DBG_DATA_MSG];
909
910 if (req != NULL) {
911 scnprintf(msg, sizeof(msg),
912 "%d %d", !req->no_interrupt, req->length);
913 dbg_print(addr, "QUEUE", status, msg);
914 }
915 }
916
917 /**
918 * dbg_setup: prints a SETUP event
919 * @addr: endpoint address
920 * @req: setup request
921 */
922 static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
923 {
924 char msg[DBG_DATA_MSG];
925
926 if (req != NULL) {
927 scnprintf(msg, sizeof(msg),
928 "%02X %02X %04X %04X %d", req->bRequestType,
929 req->bRequest, le16_to_cpu(req->wValue),
930 le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
931 dbg_print(addr, "SETUP", 0, msg);
932 }
933 }
934
935 /**
936 * show_events: displays the event buffer
937 *
938 * Check "device.h" for details
939 */
940 static ssize_t show_events(struct device *dev, struct device_attribute *attr,
941 char *buf)
942 {
943 unsigned long flags;
944 unsigned i, j, n = 0;
945
946 dbg_trace("[%s] %p\n", __func__, buf);
947 if (attr == NULL || buf == NULL) {
948 dev_err(dev, "[%s] EINVAL\n", __func__);
949 return 0;
950 }
951
952 read_lock_irqsave(&dbg_data.lck, flags);
953
954 i = dbg_data.idx;
955 for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
956 n += strlen(dbg_data.buf[i]);
957 if (n >= PAGE_SIZE) {
958 n -= strlen(dbg_data.buf[i]);
959 break;
960 }
961 }
962 for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
963 j += scnprintf(buf + j, PAGE_SIZE - j,
964 "%s", dbg_data.buf[i]);
965
966 read_unlock_irqrestore(&dbg_data.lck, flags);
967
968 return n;
969 }
970
971 /**
972 * store_events: configure if events are going to be also printed to console
973 *
974 * Check "device.h" for details
975 */
976 static ssize_t store_events(struct device *dev, struct device_attribute *attr,
977 const char *buf, size_t count)
978 {
979 unsigned tty;
980
981 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
982 if (attr == NULL || buf == NULL) {
983 dev_err(dev, "[%s] EINVAL\n", __func__);
984 goto done;
985 }
986
987 if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
988 dev_err(dev, "<1|0>: enable|disable console log\n");
989 goto done;
990 }
991
992 dbg_data.tty = tty;
993 dev_info(dev, "tty = %u", dbg_data.tty);
994
995 done:
996 return count;
997 }
998 static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
999
1000 /**
1001 * show_inters: interrupt status, enable status and historic
1002 *
1003 * Check "device.h" for details
1004 */
1005 static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
1006 char *buf)
1007 {
1008 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1009 unsigned long flags;
1010 u32 intr;
1011 unsigned i, j, n = 0;
1012
1013 dbg_trace("[%s] %p\n", __func__, buf);
1014 if (attr == NULL || buf == NULL) {
1015 dev_err(dev, "[%s] EINVAL\n", __func__);
1016 return 0;
1017 }
1018
1019 spin_lock_irqsave(udc->lock, flags);
1020
1021 n += scnprintf(buf + n, PAGE_SIZE - n,
1022 "status = %08x\n", hw_read_intr_status());
1023 n += scnprintf(buf + n, PAGE_SIZE - n,
1024 "enable = %08x\n", hw_read_intr_enable());
1025
1026 n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
1027 isr_statistics.test);
1028 n += scnprintf(buf + n, PAGE_SIZE - n, "? ui = %d\n",
1029 isr_statistics.ui);
1030 n += scnprintf(buf + n, PAGE_SIZE - n, "? uei = %d\n",
1031 isr_statistics.uei);
1032 n += scnprintf(buf + n, PAGE_SIZE - n, "? pci = %d\n",
1033 isr_statistics.pci);
1034 n += scnprintf(buf + n, PAGE_SIZE - n, "? uri = %d\n",
1035 isr_statistics.uri);
1036 n += scnprintf(buf + n, PAGE_SIZE - n, "? sli = %d\n",
1037 isr_statistics.sli);
1038 n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
1039 isr_statistics.none);
1040 n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
1041 isr_statistics.hndl.cnt);
1042
1043 for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
1044 i &= ISR_MASK;
1045 intr = isr_statistics.hndl.buf[i];
1046
1047 if (USBi_UI & intr)
1048 n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
1049 intr &= ~USBi_UI;
1050 if (USBi_UEI & intr)
1051 n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
1052 intr &= ~USBi_UEI;
1053 if (USBi_PCI & intr)
1054 n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
1055 intr &= ~USBi_PCI;
1056 if (USBi_URI & intr)
1057 n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
1058 intr &= ~USBi_URI;
1059 if (USBi_SLI & intr)
1060 n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
1061 intr &= ~USBi_SLI;
1062 if (intr)
1063 n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
1064 if (isr_statistics.hndl.buf[i])
1065 n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
1066 }
1067
1068 spin_unlock_irqrestore(udc->lock, flags);
1069
1070 return n;
1071 }
1072
1073 /**
1074 * store_inters: enable & force or disable an individual interrutps
1075 * (to be used for test purposes only)
1076 *
1077 * Check "device.h" for details
1078 */
1079 static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
1080 const char *buf, size_t count)
1081 {
1082 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1083 unsigned long flags;
1084 unsigned en, bit;
1085
1086 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1087 if (attr == NULL || buf == NULL) {
1088 dev_err(dev, "[%s] EINVAL\n", __func__);
1089 goto done;
1090 }
1091
1092 if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
1093 dev_err(dev, "<1|0> <bit>: enable|disable interrupt");
1094 goto done;
1095 }
1096
1097 spin_lock_irqsave(udc->lock, flags);
1098 if (en) {
1099 if (hw_intr_force(bit))
1100 dev_err(dev, "invalid bit number\n");
1101 else
1102 isr_statistics.test++;
1103 } else {
1104 if (hw_intr_clear(bit))
1105 dev_err(dev, "invalid bit number\n");
1106 }
1107 spin_unlock_irqrestore(udc->lock, flags);
1108
1109 done:
1110 return count;
1111 }
1112 static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
1113
1114 /**
1115 * show_port_test: reads port test mode
1116 *
1117 * Check "device.h" for details
1118 */
1119 static ssize_t show_port_test(struct device *dev,
1120 struct device_attribute *attr, char *buf)
1121 {
1122 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1123 unsigned long flags;
1124 unsigned mode;
1125
1126 dbg_trace("[%s] %p\n", __func__, buf);
1127 if (attr == NULL || buf == NULL) {
1128 dev_err(dev, "[%s] EINVAL\n", __func__);
1129 return 0;
1130 }
1131
1132 spin_lock_irqsave(udc->lock, flags);
1133 mode = hw_port_test_get();
1134 spin_unlock_irqrestore(udc->lock, flags);
1135
1136 return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
1137 }
1138
1139 /**
1140 * store_port_test: writes port test mode
1141 *
1142 * Check "device.h" for details
1143 */
1144 static ssize_t store_port_test(struct device *dev,
1145 struct device_attribute *attr,
1146 const char *buf, size_t count)
1147 {
1148 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1149 unsigned long flags;
1150 unsigned mode;
1151
1152 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1153 if (attr == NULL || buf == NULL) {
1154 dev_err(dev, "[%s] EINVAL\n", __func__);
1155 goto done;
1156 }
1157
1158 if (sscanf(buf, "%u", &mode) != 1) {
1159 dev_err(dev, "<mode>: set port test mode");
1160 goto done;
1161 }
1162
1163 spin_lock_irqsave(udc->lock, flags);
1164 if (hw_port_test_set(mode))
1165 dev_err(dev, "invalid mode\n");
1166 spin_unlock_irqrestore(udc->lock, flags);
1167
1168 done:
1169 return count;
1170 }
1171 static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
1172 show_port_test, store_port_test);
1173
1174 /**
1175 * show_qheads: DMA contents of all queue heads
1176 *
1177 * Check "device.h" for details
1178 */
1179 static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
1180 char *buf)
1181 {
1182 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1183 unsigned long flags;
1184 unsigned i, j, n = 0;
1185
1186 dbg_trace("[%s] %p\n", __func__, buf);
1187 if (attr == NULL || buf == NULL) {
1188 dev_err(dev, "[%s] EINVAL\n", __func__);
1189 return 0;
1190 }
1191
1192 spin_lock_irqsave(udc->lock, flags);
1193 for (i = 0; i < hw_ep_max/2; i++) {
1194 struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
1195 struct ci13xxx_ep *mEpTx = &udc->ci13xxx_ep[i + hw_ep_max/2];
1196 n += scnprintf(buf + n, PAGE_SIZE - n,
1197 "EP=%02i: RX=%08X TX=%08X\n",
1198 i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
1199 for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
1200 n += scnprintf(buf + n, PAGE_SIZE - n,
1201 " %04X: %08X %08X\n", j,
1202 *((u32 *)mEpRx->qh.ptr + j),
1203 *((u32 *)mEpTx->qh.ptr + j));
1204 }
1205 }
1206 spin_unlock_irqrestore(udc->lock, flags);
1207
1208 return n;
1209 }
1210 static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
1211
1212 /**
1213 * show_registers: dumps all registers
1214 *
1215 * Check "device.h" for details
1216 */
1217 #define DUMP_ENTRIES 512
1218 static ssize_t show_registers(struct device *dev,
1219 struct device_attribute *attr, char *buf)
1220 {
1221 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1222 unsigned long flags;
1223 u32 *dump;
1224 unsigned i, k, n = 0;
1225
1226 dbg_trace("[%s] %p\n", __func__, buf);
1227 if (attr == NULL || buf == NULL) {
1228 dev_err(dev, "[%s] EINVAL\n", __func__);
1229 return 0;
1230 }
1231
1232 dump = kmalloc(sizeof(u32) * DUMP_ENTRIES, GFP_KERNEL);
1233 if (!dump) {
1234 dev_err(dev, "%s: out of memory\n", __func__);
1235 return 0;
1236 }
1237
1238 spin_lock_irqsave(udc->lock, flags);
1239 k = hw_register_read(dump, DUMP_ENTRIES);
1240 spin_unlock_irqrestore(udc->lock, flags);
1241
1242 for (i = 0; i < k; i++) {
1243 n += scnprintf(buf + n, PAGE_SIZE - n,
1244 "reg[0x%04X] = 0x%08X\n",
1245 i * (unsigned)sizeof(u32), dump[i]);
1246 }
1247 kfree(dump);
1248
1249 return n;
1250 }
1251
1252 /**
1253 * store_registers: writes value to register address
1254 *
1255 * Check "device.h" for details
1256 */
1257 static ssize_t store_registers(struct device *dev,
1258 struct device_attribute *attr,
1259 const char *buf, size_t count)
1260 {
1261 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1262 unsigned long addr, data, flags;
1263
1264 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1265 if (attr == NULL || buf == NULL) {
1266 dev_err(dev, "[%s] EINVAL\n", __func__);
1267 goto done;
1268 }
1269
1270 if (sscanf(buf, "%li %li", &addr, &data) != 2) {
1271 dev_err(dev, "<addr> <data>: write data to register address");
1272 goto done;
1273 }
1274
1275 spin_lock_irqsave(udc->lock, flags);
1276 if (hw_register_write(addr, data))
1277 dev_err(dev, "invalid address range\n");
1278 spin_unlock_irqrestore(udc->lock, flags);
1279
1280 done:
1281 return count;
1282 }
1283 static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
1284 show_registers, store_registers);
1285
1286 /**
1287 * show_requests: DMA contents of all requests currently queued (all endpts)
1288 *
1289 * Check "device.h" for details
1290 */
1291 static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
1292 char *buf)
1293 {
1294 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1295 unsigned long flags;
1296 struct list_head *ptr = NULL;
1297 struct ci13xxx_req *req = NULL;
1298 unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
1299
1300 dbg_trace("[%s] %p\n", __func__, buf);
1301 if (attr == NULL || buf == NULL) {
1302 dev_err(dev, "[%s] EINVAL\n", __func__);
1303 return 0;
1304 }
1305
1306 spin_lock_irqsave(udc->lock, flags);
1307 for (i = 0; i < hw_ep_max; i++)
1308 list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
1309 {
1310 req = list_entry(ptr, struct ci13xxx_req, queue);
1311
1312 n += scnprintf(buf + n, PAGE_SIZE - n,
1313 "EP=%02i: TD=%08X %s\n",
1314 i % hw_ep_max/2, (u32)req->dma,
1315 ((i < hw_ep_max/2) ? "RX" : "TX"));
1316
1317 for (j = 0; j < qSize; j++)
1318 n += scnprintf(buf + n, PAGE_SIZE - n,
1319 " %04X: %08X\n", j,
1320 *((u32 *)req->ptr + j));
1321 }
1322 spin_unlock_irqrestore(udc->lock, flags);
1323
1324 return n;
1325 }
1326 static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
1327
1328 /**
1329 * dbg_create_files: initializes the attribute interface
1330 * @dev: device
1331 *
1332 * This function returns an error code
1333 */
1334 __maybe_unused static int dbg_create_files(struct device *dev)
1335 {
1336 int retval = 0;
1337
1338 if (dev == NULL)
1339 return -EINVAL;
1340 retval = device_create_file(dev, &dev_attr_device);
1341 if (retval)
1342 goto done;
1343 retval = device_create_file(dev, &dev_attr_driver);
1344 if (retval)
1345 goto rm_device;
1346 retval = device_create_file(dev, &dev_attr_events);
1347 if (retval)
1348 goto rm_driver;
1349 retval = device_create_file(dev, &dev_attr_inters);
1350 if (retval)
1351 goto rm_events;
1352 retval = device_create_file(dev, &dev_attr_port_test);
1353 if (retval)
1354 goto rm_inters;
1355 retval = device_create_file(dev, &dev_attr_qheads);
1356 if (retval)
1357 goto rm_port_test;
1358 retval = device_create_file(dev, &dev_attr_registers);
1359 if (retval)
1360 goto rm_qheads;
1361 retval = device_create_file(dev, &dev_attr_requests);
1362 if (retval)
1363 goto rm_registers;
1364 return 0;
1365
1366 rm_registers:
1367 device_remove_file(dev, &dev_attr_registers);
1368 rm_qheads:
1369 device_remove_file(dev, &dev_attr_qheads);
1370 rm_port_test:
1371 device_remove_file(dev, &dev_attr_port_test);
1372 rm_inters:
1373 device_remove_file(dev, &dev_attr_inters);
1374 rm_events:
1375 device_remove_file(dev, &dev_attr_events);
1376 rm_driver:
1377 device_remove_file(dev, &dev_attr_driver);
1378 rm_device:
1379 device_remove_file(dev, &dev_attr_device);
1380 done:
1381 return retval;
1382 }
1383
1384 /**
1385 * dbg_remove_files: destroys the attribute interface
1386 * @dev: device
1387 *
1388 * This function returns an error code
1389 */
1390 __maybe_unused static int dbg_remove_files(struct device *dev)
1391 {
1392 if (dev == NULL)
1393 return -EINVAL;
1394 device_remove_file(dev, &dev_attr_requests);
1395 device_remove_file(dev, &dev_attr_registers);
1396 device_remove_file(dev, &dev_attr_qheads);
1397 device_remove_file(dev, &dev_attr_port_test);
1398 device_remove_file(dev, &dev_attr_inters);
1399 device_remove_file(dev, &dev_attr_events);
1400 device_remove_file(dev, &dev_attr_driver);
1401 device_remove_file(dev, &dev_attr_device);
1402 return 0;
1403 }
1404
1405 /******************************************************************************
1406 * UTIL block
1407 *****************************************************************************/
1408 /**
1409 * _usb_addr: calculates endpoint address from direction & number
1410 * @ep: endpoint
1411 */
1412 static inline u8 _usb_addr(struct ci13xxx_ep *ep)
1413 {
1414 return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
1415 }
1416
1417 /**
1418 * _hardware_queue: configures a request at hardware level
1419 * @gadget: gadget
1420 * @mEp: endpoint
1421 *
1422 * This function returns an error code
1423 */
1424 static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1425 {
1426 unsigned i;
1427 int ret = 0;
1428 unsigned length = mReq->req.length;
1429
1430 trace("%p, %p", mEp, mReq);
1431
1432 /* don't queue twice */
1433 if (mReq->req.status == -EALREADY)
1434 return -EALREADY;
1435
1436 mReq->req.status = -EALREADY;
1437 if (length && !mReq->req.dma) {
1438 mReq->req.dma = \
1439 dma_map_single(mEp->device, mReq->req.buf,
1440 length, mEp->dir ? DMA_TO_DEVICE :
1441 DMA_FROM_DEVICE);
1442 if (mReq->req.dma == 0)
1443 return -ENOMEM;
1444
1445 mReq->map = 1;
1446 }
1447
1448 if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
1449 mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
1450 &mReq->zdma);
1451 if (mReq->zptr == NULL) {
1452 if (mReq->map) {
1453 dma_unmap_single(mEp->device, mReq->req.dma,
1454 length, mEp->dir ? DMA_TO_DEVICE :
1455 DMA_FROM_DEVICE);
1456 mReq->req.dma = 0;
1457 mReq->map = 0;
1458 }
1459 return -ENOMEM;
1460 }
1461 memset(mReq->zptr, 0, sizeof(*mReq->zptr));
1462 mReq->zptr->next = TD_TERMINATE;
1463 mReq->zptr->token = TD_STATUS_ACTIVE;
1464 if (!mReq->req.no_interrupt)
1465 mReq->zptr->token |= TD_IOC;
1466 }
1467 /*
1468 * TD configuration
1469 * TODO - handle requests which spawns into several TDs
1470 */
1471 memset(mReq->ptr, 0, sizeof(*mReq->ptr));
1472 mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
1473 mReq->ptr->token &= TD_TOTAL_BYTES;
1474 mReq->ptr->token |= TD_STATUS_ACTIVE;
1475 if (mReq->zptr) {
1476 mReq->ptr->next = mReq->zdma;
1477 } else {
1478 mReq->ptr->next = TD_TERMINATE;
1479 if (!mReq->req.no_interrupt)
1480 mReq->ptr->token |= TD_IOC;
1481 }
1482 mReq->ptr->page[0] = mReq->req.dma;
1483 for (i = 1; i < 5; i++)
1484 mReq->ptr->page[i] =
1485 (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
1486
1487 if (!list_empty(&mEp->qh.queue)) {
1488 struct ci13xxx_req *mReqPrev;
1489 int n = hw_ep_bit(mEp->num, mEp->dir);
1490 int tmp_stat;
1491
1492 mReqPrev = list_entry(mEp->qh.queue.prev,
1493 struct ci13xxx_req, queue);
1494 if (mReqPrev->zptr)
1495 mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
1496 else
1497 mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
1498 wmb();
1499 if (hw_cread(CAP_ENDPTPRIME, BIT(n)))
1500 goto done;
1501 do {
1502 hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
1503 tmp_stat = hw_cread(CAP_ENDPTSTAT, BIT(n));
1504 } while (!hw_cread(CAP_USBCMD, USBCMD_ATDTW));
1505 hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, 0);
1506 if (tmp_stat)
1507 goto done;
1508 }
1509
1510 /* QH configuration */
1511 mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
1512 mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
1513 mEp->qh.ptr->cap |= QH_ZLT;
1514
1515 wmb(); /* synchronize before ep prime */
1516
1517 ret = hw_ep_prime(mEp->num, mEp->dir,
1518 mEp->type == USB_ENDPOINT_XFER_CONTROL);
1519 done:
1520 return ret;
1521 }
1522
1523 /**
1524 * _hardware_dequeue: handles a request at hardware level
1525 * @gadget: gadget
1526 * @mEp: endpoint
1527 *
1528 * This function returns an error code
1529 */
1530 static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1531 {
1532 trace("%p, %p", mEp, mReq);
1533
1534 if (mReq->req.status != -EALREADY)
1535 return -EINVAL;
1536
1537 if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
1538 return -EBUSY;
1539
1540 if (mReq->zptr) {
1541 if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
1542 return -EBUSY;
1543 dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
1544 mReq->zptr = NULL;
1545 }
1546
1547 mReq->req.status = 0;
1548
1549 if (mReq->map) {
1550 dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
1551 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1552 mReq->req.dma = 0;
1553 mReq->map = 0;
1554 }
1555
1556 mReq->req.status = mReq->ptr->token & TD_STATUS;
1557 if ((TD_STATUS_HALTED & mReq->req.status) != 0)
1558 mReq->req.status = -1;
1559 else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
1560 mReq->req.status = -1;
1561 else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
1562 mReq->req.status = -1;
1563
1564 mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
1565 mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
1566 mReq->req.actual = mReq->req.length - mReq->req.actual;
1567 mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
1568
1569 return mReq->req.actual;
1570 }
1571
1572 /**
1573 * _ep_nuke: dequeues all endpoint requests
1574 * @mEp: endpoint
1575 *
1576 * This function returns an error code
1577 * Caller must hold lock
1578 */
1579 static int _ep_nuke(struct ci13xxx_ep *mEp)
1580 __releases(mEp->lock)
1581 __acquires(mEp->lock)
1582 {
1583 trace("%p", mEp);
1584
1585 if (mEp == NULL)
1586 return -EINVAL;
1587
1588 hw_ep_flush(mEp->num, mEp->dir);
1589
1590 while (!list_empty(&mEp->qh.queue)) {
1591
1592 /* pop oldest request */
1593 struct ci13xxx_req *mReq = \
1594 list_entry(mEp->qh.queue.next,
1595 struct ci13xxx_req, queue);
1596 list_del_init(&mReq->queue);
1597 mReq->req.status = -ESHUTDOWN;
1598
1599 if (mReq->req.complete != NULL) {
1600 spin_unlock(mEp->lock);
1601 mReq->req.complete(&mEp->ep, &mReq->req);
1602 spin_lock(mEp->lock);
1603 }
1604 }
1605 return 0;
1606 }
1607
1608 /**
1609 * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
1610 * @gadget: gadget
1611 *
1612 * This function returns an error code
1613 * Caller must hold lock
1614 */
1615 static int _gadget_stop_activity(struct usb_gadget *gadget)
1616 {
1617 struct usb_ep *ep;
1618 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
1619 unsigned long flags;
1620
1621 trace("%p", gadget);
1622
1623 if (gadget == NULL)
1624 return -EINVAL;
1625
1626 spin_lock_irqsave(udc->lock, flags);
1627 udc->gadget.speed = USB_SPEED_UNKNOWN;
1628 udc->remote_wakeup = 0;
1629 udc->suspended = 0;
1630 spin_unlock_irqrestore(udc->lock, flags);
1631
1632 /* flush all endpoints */
1633 gadget_for_each_ep(ep, gadget) {
1634 usb_ep_fifo_flush(ep);
1635 }
1636 usb_ep_fifo_flush(&udc->ep0out.ep);
1637 usb_ep_fifo_flush(&udc->ep0in.ep);
1638
1639 udc->driver->disconnect(gadget);
1640
1641 /* make sure to disable all endpoints */
1642 gadget_for_each_ep(ep, gadget) {
1643 usb_ep_disable(ep);
1644 }
1645
1646 if (udc->status != NULL) {
1647 usb_ep_free_request(&udc->ep0in.ep, udc->status);
1648 udc->status = NULL;
1649 }
1650
1651 return 0;
1652 }
1653
1654 /******************************************************************************
1655 * ISR block
1656 *****************************************************************************/
1657 /**
1658 * isr_reset_handler: USB reset interrupt handler
1659 * @udc: UDC device
1660 *
1661 * This function resets USB engine after a bus reset occurred
1662 */
1663 static void isr_reset_handler(struct ci13xxx *udc)
1664 __releases(udc->lock)
1665 __acquires(udc->lock)
1666 {
1667 int retval;
1668
1669 trace("%p", udc);
1670
1671 if (udc == NULL) {
1672 err("EINVAL");
1673 return;
1674 }
1675
1676 dbg_event(0xFF, "BUS RST", 0);
1677
1678 spin_unlock(udc->lock);
1679 retval = _gadget_stop_activity(&udc->gadget);
1680 if (retval)
1681 goto done;
1682
1683 retval = hw_usb_reset();
1684 if (retval)
1685 goto done;
1686
1687 udc->status = usb_ep_alloc_request(&udc->ep0in.ep, GFP_ATOMIC);
1688 if (udc->status == NULL)
1689 retval = -ENOMEM;
1690
1691 spin_lock(udc->lock);
1692
1693 done:
1694 if (retval)
1695 err("error: %i", retval);
1696 }
1697
1698 /**
1699 * isr_get_status_complete: get_status request complete function
1700 * @ep: endpoint
1701 * @req: request handled
1702 *
1703 * Caller must release lock
1704 */
1705 static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
1706 {
1707 trace("%p, %p", ep, req);
1708
1709 if (ep == NULL || req == NULL) {
1710 err("EINVAL");
1711 return;
1712 }
1713
1714 kfree(req->buf);
1715 usb_ep_free_request(ep, req);
1716 }
1717
1718 /**
1719 * isr_get_status_response: get_status request response
1720 * @udc: udc struct
1721 * @setup: setup request packet
1722 *
1723 * This function returns an error code
1724 */
1725 static int isr_get_status_response(struct ci13xxx *udc,
1726 struct usb_ctrlrequest *setup)
1727 __releases(mEp->lock)
1728 __acquires(mEp->lock)
1729 {
1730 struct ci13xxx_ep *mEp = &udc->ep0in;
1731 struct usb_request *req = NULL;
1732 gfp_t gfp_flags = GFP_ATOMIC;
1733 int dir, num, retval;
1734
1735 trace("%p, %p", mEp, setup);
1736
1737 if (mEp == NULL || setup == NULL)
1738 return -EINVAL;
1739
1740 spin_unlock(mEp->lock);
1741 req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
1742 spin_lock(mEp->lock);
1743 if (req == NULL)
1744 return -ENOMEM;
1745
1746 req->complete = isr_get_status_complete;
1747 req->length = 2;
1748 req->buf = kzalloc(req->length, gfp_flags);
1749 if (req->buf == NULL) {
1750 retval = -ENOMEM;
1751 goto err_free_req;
1752 }
1753
1754 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1755 /* Assume that device is bus powered for now. */
1756 *((u16 *)req->buf) = _udc->remote_wakeup << 1;
1757 retval = 0;
1758 } else if ((setup->bRequestType & USB_RECIP_MASK) \
1759 == USB_RECIP_ENDPOINT) {
1760 dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
1761 TX : RX;
1762 num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
1763 *((u16 *)req->buf) = hw_ep_get_halt(num, dir);
1764 }
1765 /* else do nothing; reserved for future use */
1766
1767 spin_unlock(mEp->lock);
1768 retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
1769 spin_lock(mEp->lock);
1770 if (retval)
1771 goto err_free_buf;
1772
1773 return 0;
1774
1775 err_free_buf:
1776 kfree(req->buf);
1777 err_free_req:
1778 spin_unlock(mEp->lock);
1779 usb_ep_free_request(&mEp->ep, req);
1780 spin_lock(mEp->lock);
1781 return retval;
1782 }
1783
1784 /**
1785 * isr_setup_status_complete: setup_status request complete function
1786 * @ep: endpoint
1787 * @req: request handled
1788 *
1789 * Caller must release lock. Put the port in test mode if test mode
1790 * feature is selected.
1791 */
1792 static void
1793 isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
1794 {
1795 struct ci13xxx *udc = req->context;
1796 unsigned long flags;
1797
1798 trace("%p, %p", ep, req);
1799
1800 spin_lock_irqsave(udc->lock, flags);
1801 if (udc->test_mode)
1802 hw_port_test_set(udc->test_mode);
1803 spin_unlock_irqrestore(udc->lock, flags);
1804 }
1805
1806 /**
1807 * isr_setup_status_phase: queues the status phase of a setup transation
1808 * @udc: udc struct
1809 *
1810 * This function returns an error code
1811 */
1812 static int isr_setup_status_phase(struct ci13xxx *udc)
1813 __releases(mEp->lock)
1814 __acquires(mEp->lock)
1815 {
1816 int retval;
1817 struct ci13xxx_ep *mEp;
1818
1819 trace("%p", udc);
1820
1821 mEp = (udc->ep0_dir == TX) ? &udc->ep0out : &udc->ep0in;
1822 udc->status->context = udc;
1823 udc->status->complete = isr_setup_status_complete;
1824
1825 spin_unlock(mEp->lock);
1826 retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
1827 spin_lock(mEp->lock);
1828
1829 return retval;
1830 }
1831
1832 /**
1833 * isr_tr_complete_low: transaction complete low level handler
1834 * @mEp: endpoint
1835 *
1836 * This function returns an error code
1837 * Caller must hold lock
1838 */
1839 static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
1840 __releases(mEp->lock)
1841 __acquires(mEp->lock)
1842 {
1843 struct ci13xxx_req *mReq, *mReqTemp;
1844 struct ci13xxx_ep *mEpTemp = mEp;
1845 int uninitialized_var(retval);
1846
1847 trace("%p", mEp);
1848
1849 if (list_empty(&mEp->qh.queue))
1850 return -EINVAL;
1851
1852 list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
1853 queue) {
1854 retval = _hardware_dequeue(mEp, mReq);
1855 if (retval < 0)
1856 break;
1857 list_del_init(&mReq->queue);
1858 dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
1859 if (mReq->req.complete != NULL) {
1860 spin_unlock(mEp->lock);
1861 if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
1862 mReq->req.length)
1863 mEpTemp = &_udc->ep0in;
1864 mReq->req.complete(&mEpTemp->ep, &mReq->req);
1865 spin_lock(mEp->lock);
1866 }
1867 }
1868
1869 if (retval == -EBUSY)
1870 retval = 0;
1871 if (retval < 0)
1872 dbg_event(_usb_addr(mEp), "DONE", retval);
1873
1874 return retval;
1875 }
1876
1877 /**
1878 * isr_tr_complete_handler: transaction complete interrupt handler
1879 * @udc: UDC descriptor
1880 *
1881 * This function handles traffic events
1882 */
1883 static void isr_tr_complete_handler(struct ci13xxx *udc)
1884 __releases(udc->lock)
1885 __acquires(udc->lock)
1886 {
1887 unsigned i;
1888 u8 tmode = 0;
1889
1890 trace("%p", udc);
1891
1892 if (udc == NULL) {
1893 err("EINVAL");
1894 return;
1895 }
1896
1897 for (i = 0; i < hw_ep_max; i++) {
1898 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
1899 int type, num, dir, err = -EINVAL;
1900 struct usb_ctrlrequest req;
1901
1902 if (mEp->desc == NULL)
1903 continue; /* not configured */
1904
1905 if (hw_test_and_clear_complete(i)) {
1906 err = isr_tr_complete_low(mEp);
1907 if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
1908 if (err > 0) /* needs status phase */
1909 err = isr_setup_status_phase(udc);
1910 if (err < 0) {
1911 dbg_event(_usb_addr(mEp),
1912 "ERROR", err);
1913 spin_unlock(udc->lock);
1914 if (usb_ep_set_halt(&mEp->ep))
1915 err("error: ep_set_halt");
1916 spin_lock(udc->lock);
1917 }
1918 }
1919 }
1920
1921 if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
1922 !hw_test_and_clear_setup_status(i))
1923 continue;
1924
1925 if (i != 0) {
1926 warn("ctrl traffic received at endpoint");
1927 continue;
1928 }
1929
1930 /*
1931 * Flush data and handshake transactions of previous
1932 * setup packet.
1933 */
1934 _ep_nuke(&udc->ep0out);
1935 _ep_nuke(&udc->ep0in);
1936
1937 /* read_setup_packet */
1938 do {
1939 hw_test_and_set_setup_guard();
1940 memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
1941 } while (!hw_test_and_clear_setup_guard());
1942
1943 type = req.bRequestType;
1944
1945 udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
1946
1947 dbg_setup(_usb_addr(mEp), &req);
1948
1949 switch (req.bRequest) {
1950 case USB_REQ_CLEAR_FEATURE:
1951 if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
1952 le16_to_cpu(req.wValue) ==
1953 USB_ENDPOINT_HALT) {
1954 if (req.wLength != 0)
1955 break;
1956 num = le16_to_cpu(req.wIndex);
1957 dir = num & USB_ENDPOINT_DIR_MASK;
1958 num &= USB_ENDPOINT_NUMBER_MASK;
1959 if (dir) /* TX */
1960 num += hw_ep_max/2;
1961 if (!udc->ci13xxx_ep[num].wedge) {
1962 spin_unlock(udc->lock);
1963 err = usb_ep_clear_halt(
1964 &udc->ci13xxx_ep[num].ep);
1965 spin_lock(udc->lock);
1966 if (err)
1967 break;
1968 }
1969 err = isr_setup_status_phase(udc);
1970 } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
1971 le16_to_cpu(req.wValue) ==
1972 USB_DEVICE_REMOTE_WAKEUP) {
1973 if (req.wLength != 0)
1974 break;
1975 udc->remote_wakeup = 0;
1976 err = isr_setup_status_phase(udc);
1977 } else {
1978 goto delegate;
1979 }
1980 break;
1981 case USB_REQ_GET_STATUS:
1982 if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
1983 type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
1984 type != (USB_DIR_IN|USB_RECIP_INTERFACE))
1985 goto delegate;
1986 if (le16_to_cpu(req.wLength) != 2 ||
1987 le16_to_cpu(req.wValue) != 0)
1988 break;
1989 err = isr_get_status_response(udc, &req);
1990 break;
1991 case USB_REQ_SET_ADDRESS:
1992 if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
1993 goto delegate;
1994 if (le16_to_cpu(req.wLength) != 0 ||
1995 le16_to_cpu(req.wIndex) != 0)
1996 break;
1997 err = hw_usb_set_address((u8)le16_to_cpu(req.wValue));
1998 if (err)
1999 break;
2000 err = isr_setup_status_phase(udc);
2001 break;
2002 case USB_REQ_SET_FEATURE:
2003 if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
2004 le16_to_cpu(req.wValue) ==
2005 USB_ENDPOINT_HALT) {
2006 if (req.wLength != 0)
2007 break;
2008 num = le16_to_cpu(req.wIndex);
2009 dir = num & USB_ENDPOINT_DIR_MASK;
2010 num &= USB_ENDPOINT_NUMBER_MASK;
2011 if (dir) /* TX */
2012 num += hw_ep_max/2;
2013
2014 spin_unlock(udc->lock);
2015 err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
2016 spin_lock(udc->lock);
2017 if (!err)
2018 isr_setup_status_phase(udc);
2019 } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
2020 if (req.wLength != 0)
2021 break;
2022 switch (le16_to_cpu(req.wValue)) {
2023 case USB_DEVICE_REMOTE_WAKEUP:
2024 udc->remote_wakeup = 1;
2025 err = isr_setup_status_phase(udc);
2026 break;
2027 case USB_DEVICE_TEST_MODE:
2028 tmode = le16_to_cpu(req.wIndex) >> 8;
2029 switch (tmode) {
2030 case TEST_J:
2031 case TEST_K:
2032 case TEST_SE0_NAK:
2033 case TEST_PACKET:
2034 case TEST_FORCE_EN:
2035 udc->test_mode = tmode;
2036 err = isr_setup_status_phase(
2037 udc);
2038 break;
2039 default:
2040 break;
2041 }
2042 default:
2043 goto delegate;
2044 }
2045 } else {
2046 goto delegate;
2047 }
2048 break;
2049 default:
2050 delegate:
2051 if (req.wLength == 0) /* no data phase */
2052 udc->ep0_dir = TX;
2053
2054 spin_unlock(udc->lock);
2055 err = udc->driver->setup(&udc->gadget, &req);
2056 spin_lock(udc->lock);
2057 break;
2058 }
2059
2060 if (err < 0) {
2061 dbg_event(_usb_addr(mEp), "ERROR", err);
2062
2063 spin_unlock(udc->lock);
2064 if (usb_ep_set_halt(&mEp->ep))
2065 err("error: ep_set_halt");
2066 spin_lock(udc->lock);
2067 }
2068 }
2069 }
2070
2071 /******************************************************************************
2072 * ENDPT block
2073 *****************************************************************************/
2074 /**
2075 * ep_enable: configure endpoint, making it usable
2076 *
2077 * Check usb_ep_enable() at "usb_gadget.h" for details
2078 */
2079 static int ep_enable(struct usb_ep *ep,
2080 const struct usb_endpoint_descriptor *desc)
2081 {
2082 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2083 int retval = 0;
2084 unsigned long flags;
2085
2086 trace("%p, %p", ep, desc);
2087
2088 if (ep == NULL || desc == NULL)
2089 return -EINVAL;
2090
2091 spin_lock_irqsave(mEp->lock, flags);
2092
2093 /* only internal SW should enable ctrl endpts */
2094
2095 mEp->desc = desc;
2096
2097 if (!list_empty(&mEp->qh.queue))
2098 warn("enabling a non-empty endpoint!");
2099
2100 mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
2101 mEp->num = usb_endpoint_num(desc);
2102 mEp->type = usb_endpoint_type(desc);
2103
2104 mEp->ep.maxpacket = __constant_le16_to_cpu(desc->wMaxPacketSize);
2105
2106 dbg_event(_usb_addr(mEp), "ENABLE", 0);
2107
2108 mEp->qh.ptr->cap = 0;
2109
2110 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2111 mEp->qh.ptr->cap |= QH_IOS;
2112 else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
2113 mEp->qh.ptr->cap &= ~QH_MULT;
2114 else
2115 mEp->qh.ptr->cap &= ~QH_ZLT;
2116
2117 mEp->qh.ptr->cap |=
2118 (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
2119 mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
2120
2121 /*
2122 * Enable endpoints in the HW other than ep0 as ep0
2123 * is always enabled
2124 */
2125 if (mEp->num)
2126 retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
2127
2128 spin_unlock_irqrestore(mEp->lock, flags);
2129 return retval;
2130 }
2131
2132 /**
2133 * ep_disable: endpoint is no longer usable
2134 *
2135 * Check usb_ep_disable() at "usb_gadget.h" for details
2136 */
2137 static int ep_disable(struct usb_ep *ep)
2138 {
2139 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2140 int direction, retval = 0;
2141 unsigned long flags;
2142
2143 trace("%p", ep);
2144
2145 if (ep == NULL)
2146 return -EINVAL;
2147 else if (mEp->desc == NULL)
2148 return -EBUSY;
2149
2150 spin_lock_irqsave(mEp->lock, flags);
2151
2152 /* only internal SW should disable ctrl endpts */
2153
2154 direction = mEp->dir;
2155 do {
2156 dbg_event(_usb_addr(mEp), "DISABLE", 0);
2157
2158 retval |= _ep_nuke(mEp);
2159 retval |= hw_ep_disable(mEp->num, mEp->dir);
2160
2161 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2162 mEp->dir = (mEp->dir == TX) ? RX : TX;
2163
2164 } while (mEp->dir != direction);
2165
2166 mEp->desc = NULL;
2167
2168 spin_unlock_irqrestore(mEp->lock, flags);
2169 return retval;
2170 }
2171
2172 /**
2173 * ep_alloc_request: allocate a request object to use with this endpoint
2174 *
2175 * Check usb_ep_alloc_request() at "usb_gadget.h" for details
2176 */
2177 static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
2178 {
2179 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2180 struct ci13xxx_req *mReq = NULL;
2181
2182 trace("%p, %i", ep, gfp_flags);
2183
2184 if (ep == NULL) {
2185 err("EINVAL");
2186 return NULL;
2187 }
2188
2189 mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
2190 if (mReq != NULL) {
2191 INIT_LIST_HEAD(&mReq->queue);
2192
2193 mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
2194 &mReq->dma);
2195 if (mReq->ptr == NULL) {
2196 kfree(mReq);
2197 mReq = NULL;
2198 }
2199 }
2200
2201 dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
2202
2203 return (mReq == NULL) ? NULL : &mReq->req;
2204 }
2205
2206 /**
2207 * ep_free_request: frees a request object
2208 *
2209 * Check usb_ep_free_request() at "usb_gadget.h" for details
2210 */
2211 static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
2212 {
2213 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2214 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2215 unsigned long flags;
2216
2217 trace("%p, %p", ep, req);
2218
2219 if (ep == NULL || req == NULL) {
2220 err("EINVAL");
2221 return;
2222 } else if (!list_empty(&mReq->queue)) {
2223 err("EBUSY");
2224 return;
2225 }
2226
2227 spin_lock_irqsave(mEp->lock, flags);
2228
2229 if (mReq->ptr)
2230 dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
2231 kfree(mReq);
2232
2233 dbg_event(_usb_addr(mEp), "FREE", 0);
2234
2235 spin_unlock_irqrestore(mEp->lock, flags);
2236 }
2237
2238 /**
2239 * ep_queue: queues (submits) an I/O request to an endpoint
2240 *
2241 * Check usb_ep_queue()* at usb_gadget.h" for details
2242 */
2243 static int ep_queue(struct usb_ep *ep, struct usb_request *req,
2244 gfp_t __maybe_unused gfp_flags)
2245 {
2246 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2247 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2248 int retval = 0;
2249 unsigned long flags;
2250
2251 trace("%p, %p, %X", ep, req, gfp_flags);
2252
2253 if (ep == NULL || req == NULL || mEp->desc == NULL)
2254 return -EINVAL;
2255
2256 spin_lock_irqsave(mEp->lock, flags);
2257
2258 if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
2259 if (req->length)
2260 mEp = (_udc->ep0_dir == RX) ?
2261 &_udc->ep0out : &_udc->ep0in;
2262 if (!list_empty(&mEp->qh.queue)) {
2263 _ep_nuke(mEp);
2264 retval = -EOVERFLOW;
2265 warn("endpoint ctrl %X nuked", _usb_addr(mEp));
2266 }
2267 }
2268
2269 /* first nuke then test link, e.g. previous status has not sent */
2270 if (!list_empty(&mReq->queue)) {
2271 retval = -EBUSY;
2272 err("request already in queue");
2273 goto done;
2274 }
2275
2276 if (req->length > (4 * CI13XXX_PAGE_SIZE)) {
2277 req->length = (4 * CI13XXX_PAGE_SIZE);
2278 retval = -EMSGSIZE;
2279 warn("request length truncated");
2280 }
2281
2282 dbg_queue(_usb_addr(mEp), req, retval);
2283
2284 /* push request */
2285 mReq->req.status = -EINPROGRESS;
2286 mReq->req.actual = 0;
2287
2288 retval = _hardware_enqueue(mEp, mReq);
2289
2290 if (retval == -EALREADY) {
2291 dbg_event(_usb_addr(mEp), "QUEUE", retval);
2292 retval = 0;
2293 }
2294 if (!retval)
2295 list_add_tail(&mReq->queue, &mEp->qh.queue);
2296
2297 done:
2298 spin_unlock_irqrestore(mEp->lock, flags);
2299 return retval;
2300 }
2301
2302 /**
2303 * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
2304 *
2305 * Check usb_ep_dequeue() at "usb_gadget.h" for details
2306 */
2307 static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2308 {
2309 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2310 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2311 unsigned long flags;
2312
2313 trace("%p, %p", ep, req);
2314
2315 if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
2316 mEp->desc == NULL || list_empty(&mReq->queue) ||
2317 list_empty(&mEp->qh.queue))
2318 return -EINVAL;
2319
2320 spin_lock_irqsave(mEp->lock, flags);
2321
2322 dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
2323
2324 hw_ep_flush(mEp->num, mEp->dir);
2325
2326 /* pop request */
2327 list_del_init(&mReq->queue);
2328 if (mReq->map) {
2329 dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
2330 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
2331 mReq->req.dma = 0;
2332 mReq->map = 0;
2333 }
2334 req->status = -ECONNRESET;
2335
2336 if (mReq->req.complete != NULL) {
2337 spin_unlock(mEp->lock);
2338 mReq->req.complete(&mEp->ep, &mReq->req);
2339 spin_lock(mEp->lock);
2340 }
2341
2342 spin_unlock_irqrestore(mEp->lock, flags);
2343 return 0;
2344 }
2345
2346 /**
2347 * ep_set_halt: sets the endpoint halt feature
2348 *
2349 * Check usb_ep_set_halt() at "usb_gadget.h" for details
2350 */
2351 static int ep_set_halt(struct usb_ep *ep, int value)
2352 {
2353 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2354 int direction, retval = 0;
2355 unsigned long flags;
2356
2357 trace("%p, %i", ep, value);
2358
2359 if (ep == NULL || mEp->desc == NULL)
2360 return -EINVAL;
2361
2362 spin_lock_irqsave(mEp->lock, flags);
2363
2364 #ifndef STALL_IN
2365 /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
2366 if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
2367 !list_empty(&mEp->qh.queue)) {
2368 spin_unlock_irqrestore(mEp->lock, flags);
2369 return -EAGAIN;
2370 }
2371 #endif
2372
2373 direction = mEp->dir;
2374 do {
2375 dbg_event(_usb_addr(mEp), "HALT", value);
2376 retval |= hw_ep_set_halt(mEp->num, mEp->dir, value);
2377
2378 if (!value)
2379 mEp->wedge = 0;
2380
2381 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2382 mEp->dir = (mEp->dir == TX) ? RX : TX;
2383
2384 } while (mEp->dir != direction);
2385
2386 spin_unlock_irqrestore(mEp->lock, flags);
2387 return retval;
2388 }
2389
2390 /**
2391 * ep_set_wedge: sets the halt feature and ignores clear requests
2392 *
2393 * Check usb_ep_set_wedge() at "usb_gadget.h" for details
2394 */
2395 static int ep_set_wedge(struct usb_ep *ep)
2396 {
2397 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2398 unsigned long flags;
2399
2400 trace("%p", ep);
2401
2402 if (ep == NULL || mEp->desc == NULL)
2403 return -EINVAL;
2404
2405 spin_lock_irqsave(mEp->lock, flags);
2406
2407 dbg_event(_usb_addr(mEp), "WEDGE", 0);
2408 mEp->wedge = 1;
2409
2410 spin_unlock_irqrestore(mEp->lock, flags);
2411
2412 return usb_ep_set_halt(ep);
2413 }
2414
2415 /**
2416 * ep_fifo_flush: flushes contents of a fifo
2417 *
2418 * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
2419 */
2420 static void ep_fifo_flush(struct usb_ep *ep)
2421 {
2422 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2423 unsigned long flags;
2424
2425 trace("%p", ep);
2426
2427 if (ep == NULL) {
2428 err("%02X: -EINVAL", _usb_addr(mEp));
2429 return;
2430 }
2431
2432 spin_lock_irqsave(mEp->lock, flags);
2433
2434 dbg_event(_usb_addr(mEp), "FFLUSH", 0);
2435 hw_ep_flush(mEp->num, mEp->dir);
2436
2437 spin_unlock_irqrestore(mEp->lock, flags);
2438 }
2439
2440 /**
2441 * Endpoint-specific part of the API to the USB controller hardware
2442 * Check "usb_gadget.h" for details
2443 */
2444 static const struct usb_ep_ops usb_ep_ops = {
2445 .enable = ep_enable,
2446 .disable = ep_disable,
2447 .alloc_request = ep_alloc_request,
2448 .free_request = ep_free_request,
2449 .queue = ep_queue,
2450 .dequeue = ep_dequeue,
2451 .set_halt = ep_set_halt,
2452 .set_wedge = ep_set_wedge,
2453 .fifo_flush = ep_fifo_flush,
2454 };
2455
2456 /******************************************************************************
2457 * GADGET block
2458 *****************************************************************************/
2459 static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
2460 {
2461 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
2462 unsigned long flags;
2463 int gadget_ready = 0;
2464
2465 if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
2466 return -EOPNOTSUPP;
2467
2468 spin_lock_irqsave(udc->lock, flags);
2469 udc->vbus_active = is_active;
2470 if (udc->driver)
2471 gadget_ready = 1;
2472 spin_unlock_irqrestore(udc->lock, flags);
2473
2474 if (gadget_ready) {
2475 if (is_active) {
2476 pm_runtime_get_sync(&_gadget->dev);
2477 hw_device_reset(udc);
2478 hw_device_state(udc->ep0out.qh.dma);
2479 } else {
2480 hw_device_state(0);
2481 if (udc->udc_driver->notify_event)
2482 udc->udc_driver->notify_event(udc,
2483 CI13XXX_CONTROLLER_STOPPED_EVENT);
2484 _gadget_stop_activity(&udc->gadget);
2485 pm_runtime_put_sync(&_gadget->dev);
2486 }
2487 }
2488
2489 return 0;
2490 }
2491
2492 static int ci13xxx_wakeup(struct usb_gadget *_gadget)
2493 {
2494 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
2495 unsigned long flags;
2496 int ret = 0;
2497
2498 trace();
2499
2500 spin_lock_irqsave(udc->lock, flags);
2501 if (!udc->remote_wakeup) {
2502 ret = -EOPNOTSUPP;
2503 dbg_trace("remote wakeup feature is not enabled\n");
2504 goto out;
2505 }
2506 if (!hw_cread(CAP_PORTSC, PORTSC_SUSP)) {
2507 ret = -EINVAL;
2508 dbg_trace("port is not suspended\n");
2509 goto out;
2510 }
2511 hw_cwrite(CAP_PORTSC, PORTSC_FPR, PORTSC_FPR);
2512 out:
2513 spin_unlock_irqrestore(udc->lock, flags);
2514 return ret;
2515 }
2516
2517 static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
2518 {
2519 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
2520
2521 if (udc->transceiver)
2522 return otg_set_power(udc->transceiver, mA);
2523 return -ENOTSUPP;
2524 }
2525
2526 static int ci13xxx_start(struct usb_gadget_driver *driver,
2527 int (*bind)(struct usb_gadget *));
2528 static int ci13xxx_stop(struct usb_gadget_driver *driver);
2529 /**
2530 * Device operations part of the API to the USB controller hardware,
2531 * which don't involve endpoints (or i/o)
2532 * Check "usb_gadget.h" for details
2533 */
2534 static const struct usb_gadget_ops usb_gadget_ops = {
2535 .vbus_session = ci13xxx_vbus_session,
2536 .wakeup = ci13xxx_wakeup,
2537 .vbus_draw = ci13xxx_vbus_draw,
2538 .start = ci13xxx_start,
2539 .stop = ci13xxx_stop,
2540 };
2541
2542 /**
2543 * ci13xxx_start: register a gadget driver
2544 * @driver: the driver being registered
2545 * @bind: the driver's bind callback
2546 *
2547 * Check ci13xxx_start() at <linux/usb/gadget.h> for details.
2548 * Interrupts are enabled here.
2549 */
2550 static int ci13xxx_start(struct usb_gadget_driver *driver,
2551 int (*bind)(struct usb_gadget *))
2552 {
2553 struct ci13xxx *udc = _udc;
2554 unsigned long flags;
2555 int i, j;
2556 int retval = -ENOMEM;
2557
2558 trace("%p", driver);
2559
2560 if (driver == NULL ||
2561 bind == NULL ||
2562 driver->setup == NULL ||
2563 driver->disconnect == NULL ||
2564 driver->suspend == NULL ||
2565 driver->resume == NULL)
2566 return -EINVAL;
2567 else if (udc == NULL)
2568 return -ENODEV;
2569 else if (udc->driver != NULL)
2570 return -EBUSY;
2571
2572 /* alloc resources */
2573 udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
2574 sizeof(struct ci13xxx_qh),
2575 64, CI13XXX_PAGE_SIZE);
2576 if (udc->qh_pool == NULL)
2577 return -ENOMEM;
2578
2579 udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
2580 sizeof(struct ci13xxx_td),
2581 64, CI13XXX_PAGE_SIZE);
2582 if (udc->td_pool == NULL) {
2583 dma_pool_destroy(udc->qh_pool);
2584 udc->qh_pool = NULL;
2585 return -ENOMEM;
2586 }
2587
2588 spin_lock_irqsave(udc->lock, flags);
2589
2590 info("hw_ep_max = %d", hw_ep_max);
2591
2592 udc->gadget.dev.driver = NULL;
2593
2594 retval = 0;
2595 for (i = 0; i < hw_ep_max/2; i++) {
2596 for (j = RX; j <= TX; j++) {
2597 int k = i + j * hw_ep_max/2;
2598 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
2599
2600 scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
2601 (j == TX) ? "in" : "out");
2602
2603 mEp->lock = udc->lock;
2604 mEp->device = &udc->gadget.dev;
2605 mEp->td_pool = udc->td_pool;
2606
2607 mEp->ep.name = mEp->name;
2608 mEp->ep.ops = &usb_ep_ops;
2609 mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
2610
2611 INIT_LIST_HEAD(&mEp->qh.queue);
2612 spin_unlock_irqrestore(udc->lock, flags);
2613 mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
2614 &mEp->qh.dma);
2615 spin_lock_irqsave(udc->lock, flags);
2616 if (mEp->qh.ptr == NULL)
2617 retval = -ENOMEM;
2618 else
2619 memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
2620
2621 /* skip ep0 out and in endpoints */
2622 if (i == 0)
2623 continue;
2624
2625 list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
2626 }
2627 }
2628 if (retval)
2629 goto done;
2630 spin_unlock_irqrestore(udc->lock, flags);
2631 udc->ep0out.ep.desc = &ctrl_endpt_out_desc;
2632 retval = usb_ep_enable(&udc->ep0out.ep);
2633 if (retval)
2634 return retval;
2635
2636 udc->ep0in.ep.desc = &ctrl_endpt_in_desc;
2637 retval = usb_ep_enable(&udc->ep0in.ep);
2638 if (retval)
2639 return retval;
2640 spin_lock_irqsave(udc->lock, flags);
2641
2642 udc->gadget.ep0 = &udc->ep0in.ep;
2643 /* bind gadget */
2644 driver->driver.bus = NULL;
2645 udc->gadget.dev.driver = &driver->driver;
2646
2647 spin_unlock_irqrestore(udc->lock, flags);
2648 retval = bind(&udc->gadget); /* MAY SLEEP */
2649 spin_lock_irqsave(udc->lock, flags);
2650
2651 if (retval) {
2652 udc->gadget.dev.driver = NULL;
2653 goto done;
2654 }
2655
2656 udc->driver = driver;
2657 pm_runtime_get_sync(&udc->gadget.dev);
2658 if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
2659 if (udc->vbus_active) {
2660 if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
2661 hw_device_reset(udc);
2662 } else {
2663 pm_runtime_put_sync(&udc->gadget.dev);
2664 goto done;
2665 }
2666 }
2667
2668 retval = hw_device_state(udc->ep0out.qh.dma);
2669 if (retval)
2670 pm_runtime_put_sync(&udc->gadget.dev);
2671
2672 done:
2673 spin_unlock_irqrestore(udc->lock, flags);
2674 return retval;
2675 }
2676
2677 /**
2678 * ci13xxx_stop: unregister a gadget driver
2679 *
2680 * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
2681 */
2682 static int ci13xxx_stop(struct usb_gadget_driver *driver)
2683 {
2684 struct ci13xxx *udc = _udc;
2685 unsigned long i, flags;
2686
2687 trace("%p", driver);
2688
2689 if (driver == NULL ||
2690 driver->unbind == NULL ||
2691 driver->setup == NULL ||
2692 driver->disconnect == NULL ||
2693 driver->suspend == NULL ||
2694 driver->resume == NULL ||
2695 driver != udc->driver)
2696 return -EINVAL;
2697
2698 spin_lock_irqsave(udc->lock, flags);
2699
2700 if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
2701 udc->vbus_active) {
2702 hw_device_state(0);
2703 if (udc->udc_driver->notify_event)
2704 udc->udc_driver->notify_event(udc,
2705 CI13XXX_CONTROLLER_STOPPED_EVENT);
2706 _gadget_stop_activity(&udc->gadget);
2707 pm_runtime_put(&udc->gadget.dev);
2708 }
2709
2710 /* unbind gadget */
2711 spin_unlock_irqrestore(udc->lock, flags);
2712 driver->unbind(&udc->gadget); /* MAY SLEEP */
2713 spin_lock_irqsave(udc->lock, flags);
2714
2715 udc->gadget.dev.driver = NULL;
2716
2717 /* free resources */
2718 for (i = 0; i < hw_ep_max; i++) {
2719 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
2720
2721 if (!list_empty(&mEp->ep.ep_list))
2722 list_del_init(&mEp->ep.ep_list);
2723
2724 if (mEp->qh.ptr != NULL)
2725 dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
2726 }
2727
2728 udc->gadget.ep0 = NULL;
2729 udc->driver = NULL;
2730
2731 spin_unlock_irqrestore(udc->lock, flags);
2732
2733 if (udc->td_pool != NULL) {
2734 dma_pool_destroy(udc->td_pool);
2735 udc->td_pool = NULL;
2736 }
2737 if (udc->qh_pool != NULL) {
2738 dma_pool_destroy(udc->qh_pool);
2739 udc->qh_pool = NULL;
2740 }
2741
2742 return 0;
2743 }
2744
2745 /******************************************************************************
2746 * BUS block
2747 *****************************************************************************/
2748 /**
2749 * udc_irq: global interrupt handler
2750 *
2751 * This function returns IRQ_HANDLED if the IRQ has been handled
2752 * It locks access to registers
2753 */
2754 static irqreturn_t udc_irq(void)
2755 {
2756 struct ci13xxx *udc = _udc;
2757 irqreturn_t retval;
2758 u32 intr;
2759
2760 trace();
2761
2762 if (udc == NULL) {
2763 err("ENODEV");
2764 return IRQ_HANDLED;
2765 }
2766
2767 spin_lock(udc->lock);
2768
2769 if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
2770 if (hw_cread(CAP_USBMODE, USBMODE_CM) !=
2771 USBMODE_CM_DEVICE) {
2772 spin_unlock(udc->lock);
2773 return IRQ_NONE;
2774 }
2775 }
2776 intr = hw_test_and_clear_intr_active();
2777 if (intr) {
2778 isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
2779 isr_statistics.hndl.idx &= ISR_MASK;
2780 isr_statistics.hndl.cnt++;
2781
2782 /* order defines priority - do NOT change it */
2783 if (USBi_URI & intr) {
2784 isr_statistics.uri++;
2785 isr_reset_handler(udc);
2786 }
2787 if (USBi_PCI & intr) {
2788 isr_statistics.pci++;
2789 udc->gadget.speed = hw_port_is_high_speed() ?
2790 USB_SPEED_HIGH : USB_SPEED_FULL;
2791 if (udc->suspended) {
2792 spin_unlock(udc->lock);
2793 udc->driver->resume(&udc->gadget);
2794 spin_lock(udc->lock);
2795 udc->suspended = 0;
2796 }
2797 }
2798 if (USBi_UEI & intr)
2799 isr_statistics.uei++;
2800 if (USBi_UI & intr) {
2801 isr_statistics.ui++;
2802 isr_tr_complete_handler(udc);
2803 }
2804 if (USBi_SLI & intr) {
2805 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
2806 udc->suspended = 1;
2807 spin_unlock(udc->lock);
2808 udc->driver->suspend(&udc->gadget);
2809 spin_lock(udc->lock);
2810 }
2811 isr_statistics.sli++;
2812 }
2813 retval = IRQ_HANDLED;
2814 } else {
2815 isr_statistics.none++;
2816 retval = IRQ_NONE;
2817 }
2818 spin_unlock(udc->lock);
2819
2820 return retval;
2821 }
2822
2823 /**
2824 * udc_release: driver release function
2825 * @dev: device
2826 *
2827 * Currently does nothing
2828 */
2829 static void udc_release(struct device *dev)
2830 {
2831 trace("%p", dev);
2832
2833 if (dev == NULL)
2834 err("EINVAL");
2835 }
2836
2837 /**
2838 * udc_probe: parent probe must call this to initialize UDC
2839 * @dev: parent device
2840 * @regs: registers base address
2841 * @name: driver name
2842 *
2843 * This function returns an error code
2844 * No interrupts active, the IRQ has not been requested yet
2845 * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
2846 */
2847 static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
2848 void __iomem *regs)
2849 {
2850 struct ci13xxx *udc;
2851 int retval = 0;
2852
2853 trace("%p, %p, %p", dev, regs, name);
2854
2855 if (dev == NULL || regs == NULL || driver == NULL ||
2856 driver->name == NULL)
2857 return -EINVAL;
2858
2859 udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
2860 if (udc == NULL)
2861 return -ENOMEM;
2862
2863 udc->lock = &udc_lock;
2864 udc->regs = regs;
2865 udc->udc_driver = driver;
2866
2867 udc->gadget.ops = &usb_gadget_ops;
2868 udc->gadget.speed = USB_SPEED_UNKNOWN;
2869 udc->gadget.is_dualspeed = 1;
2870 udc->gadget.is_otg = 0;
2871 udc->gadget.name = driver->name;
2872
2873 INIT_LIST_HEAD(&udc->gadget.ep_list);
2874 udc->gadget.ep0 = NULL;
2875
2876 dev_set_name(&udc->gadget.dev, "gadget");
2877 udc->gadget.dev.dma_mask = dev->dma_mask;
2878 udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
2879 udc->gadget.dev.parent = dev;
2880 udc->gadget.dev.release = udc_release;
2881
2882 retval = hw_device_init(regs);
2883 if (retval < 0)
2884 goto free_udc;
2885
2886 udc->transceiver = otg_get_transceiver();
2887
2888 if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
2889 if (udc->transceiver == NULL) {
2890 retval = -ENODEV;
2891 goto free_udc;
2892 }
2893 }
2894
2895 if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
2896 retval = hw_device_reset(udc);
2897 if (retval)
2898 goto put_transceiver;
2899 }
2900
2901 retval = device_register(&udc->gadget.dev);
2902 if (retval) {
2903 put_device(&udc->gadget.dev);
2904 goto put_transceiver;
2905 }
2906
2907 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2908 retval = dbg_create_files(&udc->gadget.dev);
2909 #endif
2910 if (retval)
2911 goto unreg_device;
2912
2913 if (udc->transceiver) {
2914 retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
2915 if (retval)
2916 goto remove_dbg;
2917 }
2918
2919 retval = usb_add_gadget_udc(dev, &udc->gadget);
2920 if (retval)
2921 goto remove_trans;
2922
2923 pm_runtime_no_callbacks(&udc->gadget.dev);
2924 pm_runtime_enable(&udc->gadget.dev);
2925
2926 _udc = udc;
2927 return retval;
2928
2929 remove_trans:
2930 if (udc->transceiver) {
2931 otg_set_peripheral(udc->transceiver, &udc->gadget);
2932 otg_put_transceiver(udc->transceiver);
2933 }
2934
2935 err("error = %i", retval);
2936 remove_dbg:
2937 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2938 dbg_remove_files(&udc->gadget.dev);
2939 #endif
2940 unreg_device:
2941 device_unregister(&udc->gadget.dev);
2942 put_transceiver:
2943 if (udc->transceiver)
2944 otg_put_transceiver(udc->transceiver);
2945 free_udc:
2946 kfree(udc);
2947 _udc = NULL;
2948 return retval;
2949 }
2950
2951 /**
2952 * udc_remove: parent remove must call this to remove UDC
2953 *
2954 * No interrupts active, the IRQ has been released
2955 */
2956 static void udc_remove(void)
2957 {
2958 struct ci13xxx *udc = _udc;
2959
2960 if (udc == NULL) {
2961 err("EINVAL");
2962 return;
2963 }
2964 usb_del_gadget_udc(&udc->gadget);
2965
2966 if (udc->transceiver) {
2967 otg_set_peripheral(udc->transceiver, &udc->gadget);
2968 otg_put_transceiver(udc->transceiver);
2969 }
2970 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2971 dbg_remove_files(&udc->gadget.dev);
2972 #endif
2973 device_unregister(&udc->gadget.dev);
2974
2975 kfree(udc);
2976 _udc = NULL;
2977 }
Linux with added FPC-III support