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usb: gadget: r8a66597-udc: fix cannot connect after rmmod gadget driver
[linux/fpc-iii.git] / drivers / usb / gadget / fusb300_udc.c
blob24a924330c81f0d23bd70e5270c31ca97f0488c3
1 /*
2 * Fusb300 UDC (USB gadget)
3 *
4 * Copyright (C) 2010 Faraday Technology Corp.
5 *
6 * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22 #include <linux/dma-mapping.h>
23 #include <linux/err.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/platform_device.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29
30 #include "fusb300_udc.h"
31
32 MODULE_DESCRIPTION("FUSB300 USB gadget driver");
33 MODULE_LICENSE("GPL");
34 MODULE_AUTHOR("Yuan Hsin Chen <yhchen@faraday-tech.com>");
35 MODULE_ALIAS("platform:fusb300_udc");
36
37 #define DRIVER_VERSION "20 October 2010"
38
39 static const char udc_name[] = "fusb300_udc";
40 static const char * const fusb300_ep_name[] = {
41 "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7", "ep8", "ep9",
42 "ep10", "ep11", "ep12", "ep13", "ep14", "ep15"
43 };
44
45 static void done(struct fusb300_ep *ep, struct fusb300_request *req,
46 int status);
47
48 static void fusb300_enable_bit(struct fusb300 *fusb300, u32 offset,
49 u32 value)
50 {
51 u32 reg = ioread32(fusb300->reg + offset);
52
53 reg |= value;
54 iowrite32(reg, fusb300->reg + offset);
55 }
56
57 static void fusb300_disable_bit(struct fusb300 *fusb300, u32 offset,
58 u32 value)
59 {
60 u32 reg = ioread32(fusb300->reg + offset);
61
62 reg &= ~value;
63 iowrite32(reg, fusb300->reg + offset);
64 }
65
66
67 static void fusb300_ep_setting(struct fusb300_ep *ep,
68 struct fusb300_ep_info info)
69 {
70 ep->epnum = info.epnum;
71 ep->type = info.type;
72 }
73
74 static int fusb300_ep_release(struct fusb300_ep *ep)
75 {
76 if (!ep->epnum)
77 return 0;
78 ep->epnum = 0;
79 ep->stall = 0;
80 ep->wedged = 0;
81 return 0;
82 }
83
84 static void fusb300_set_fifo_entry(struct fusb300 *fusb300,
85 u32 ep)
86 {
87 u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
88
89 val &= ~FUSB300_EPSET1_FIFOENTRY_MSK;
90 val |= FUSB300_EPSET1_FIFOENTRY(FUSB300_FIFO_ENTRY_NUM);
91 iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
92 }
93
94 static void fusb300_set_start_entry(struct fusb300 *fusb300,
95 u8 ep)
96 {
97 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
98 u32 start_entry = fusb300->fifo_entry_num * FUSB300_FIFO_ENTRY_NUM;
99
100 reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ;
101 reg |= FUSB300_EPSET1_START_ENTRY(start_entry);
102 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
103 if (fusb300->fifo_entry_num == FUSB300_MAX_FIFO_ENTRY) {
104 fusb300->fifo_entry_num = 0;
105 fusb300->addrofs = 0;
106 pr_err("fifo entry is over the maximum number!\n");
107 } else
108 fusb300->fifo_entry_num++;
109 }
110
111 /* set fusb300_set_start_entry first before fusb300_set_epaddrofs */
112 static void fusb300_set_epaddrofs(struct fusb300 *fusb300,
113 struct fusb300_ep_info info)
114 {
115 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
116
117 reg &= ~FUSB300_EPSET2_ADDROFS_MSK;
118 reg |= FUSB300_EPSET2_ADDROFS(fusb300->addrofs);
119 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
120 fusb300->addrofs += (info.maxpacket + 7) / 8 * FUSB300_FIFO_ENTRY_NUM;
121 }
122
123 static void ep_fifo_setting(struct fusb300 *fusb300,
124 struct fusb300_ep_info info)
125 {
126 fusb300_set_fifo_entry(fusb300, info.epnum);
127 fusb300_set_start_entry(fusb300, info.epnum);
128 fusb300_set_epaddrofs(fusb300, info);
129 }
130
131 static void fusb300_set_eptype(struct fusb300 *fusb300,
132 struct fusb300_ep_info info)
133 {
134 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
135
136 reg &= ~FUSB300_EPSET1_TYPE_MSK;
137 reg |= FUSB300_EPSET1_TYPE(info.type);
138 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
139 }
140
141 static void fusb300_set_epdir(struct fusb300 *fusb300,
142 struct fusb300_ep_info info)
143 {
144 u32 reg;
145
146 if (!info.dir_in)
147 return;
148 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
149 reg &= ~FUSB300_EPSET1_DIR_MSK;
150 reg |= FUSB300_EPSET1_DIRIN;
151 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
152 }
153
154 static void fusb300_set_ep_active(struct fusb300 *fusb300,
155 u8 ep)
156 {
157 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
158
159 reg |= FUSB300_EPSET1_ACTEN;
160 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
161 }
162
163 static void fusb300_set_epmps(struct fusb300 *fusb300,
164 struct fusb300_ep_info info)
165 {
166 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
167
168 reg &= ~FUSB300_EPSET2_MPS_MSK;
169 reg |= FUSB300_EPSET2_MPS(info.maxpacket);
170 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
171 }
172
173 static void fusb300_set_interval(struct fusb300 *fusb300,
174 struct fusb300_ep_info info)
175 {
176 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
177
178 reg &= ~FUSB300_EPSET1_INTERVAL(0x7);
179 reg |= FUSB300_EPSET1_INTERVAL(info.interval);
180 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
181 }
182
183 static void fusb300_set_bwnum(struct fusb300 *fusb300,
184 struct fusb300_ep_info info)
185 {
186 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
187
188 reg &= ~FUSB300_EPSET1_BWNUM(0x3);
189 reg |= FUSB300_EPSET1_BWNUM(info.bw_num);
190 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
191 }
192
193 static void set_ep_reg(struct fusb300 *fusb300,
194 struct fusb300_ep_info info)
195 {
196 fusb300_set_eptype(fusb300, info);
197 fusb300_set_epdir(fusb300, info);
198 fusb300_set_epmps(fusb300, info);
199
200 if (info.interval)
201 fusb300_set_interval(fusb300, info);
202
203 if (info.bw_num)
204 fusb300_set_bwnum(fusb300, info);
205
206 fusb300_set_ep_active(fusb300, info.epnum);
207 }
208
209 static int config_ep(struct fusb300_ep *ep,
210 const struct usb_endpoint_descriptor *desc)
211 {
212 struct fusb300 *fusb300 = ep->fusb300;
213 struct fusb300_ep_info info;
214
215 ep->desc = desc;
216
217 info.interval = 0;
218 info.addrofs = 0;
219 info.bw_num = 0;
220
221 info.type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
222 info.dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
223 info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
224 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
225
226 if ((info.type == USB_ENDPOINT_XFER_INT) ||
227 (info.type == USB_ENDPOINT_XFER_ISOC)) {
228 info.interval = desc->bInterval;
229 if (info.type == USB_ENDPOINT_XFER_ISOC)
230 info.bw_num = ((desc->wMaxPacketSize & 0x1800) >> 11);
231 }
232
233 ep_fifo_setting(fusb300, info);
234
235 set_ep_reg(fusb300, info);
236
237 fusb300_ep_setting(ep, info);
238
239 fusb300->ep[info.epnum] = ep;
240
241 return 0;
242 }
243
244 static int fusb300_enable(struct usb_ep *_ep,
245 const struct usb_endpoint_descriptor *desc)
246 {
247 struct fusb300_ep *ep;
248
249 ep = container_of(_ep, struct fusb300_ep, ep);
250
251 if (ep->fusb300->reenum) {
252 ep->fusb300->fifo_entry_num = 0;
253 ep->fusb300->addrofs = 0;
254 ep->fusb300->reenum = 0;
255 }
256
257 return config_ep(ep, desc);
258 }
259
260 static int fusb300_disable(struct usb_ep *_ep)
261 {
262 struct fusb300_ep *ep;
263 struct fusb300_request *req;
264 unsigned long flags;
265
266 ep = container_of(_ep, struct fusb300_ep, ep);
267
268 BUG_ON(!ep);
269
270 while (!list_empty(&ep->queue)) {
271 req = list_entry(ep->queue.next, struct fusb300_request, queue);
272 spin_lock_irqsave(&ep->fusb300->lock, flags);
273 done(ep, req, -ECONNRESET);
274 spin_unlock_irqrestore(&ep->fusb300->lock, flags);
275 }
276
277 return fusb300_ep_release(ep);
278 }
279
280 static struct usb_request *fusb300_alloc_request(struct usb_ep *_ep,
281 gfp_t gfp_flags)
282 {
283 struct fusb300_request *req;
284
285 req = kzalloc(sizeof(struct fusb300_request), gfp_flags);
286 if (!req)
287 return NULL;
288 INIT_LIST_HEAD(&req->queue);
289
290 return &req->req;
291 }
292
293 static void fusb300_free_request(struct usb_ep *_ep, struct usb_request *_req)
294 {
295 struct fusb300_request *req;
296
297 req = container_of(_req, struct fusb300_request, req);
298 kfree(req);
299 }
300
301 static int enable_fifo_int(struct fusb300_ep *ep)
302 {
303 struct fusb300 *fusb300 = ep->fusb300;
304
305 if (ep->epnum) {
306 fusb300_enable_bit(fusb300, FUSB300_OFFSET_IGER0,
307 FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
308 } else {
309 pr_err("can't enable_fifo_int ep0\n");
310 return -EINVAL;
311 }
312
313 return 0;
314 }
315
316 static int disable_fifo_int(struct fusb300_ep *ep)
317 {
318 struct fusb300 *fusb300 = ep->fusb300;
319
320 if (ep->epnum) {
321 fusb300_disable_bit(fusb300, FUSB300_OFFSET_IGER0,
322 FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
323 } else {
324 pr_err("can't disable_fifo_int ep0\n");
325 return -EINVAL;
326 }
327
328 return 0;
329 }
330
331 static void fusb300_set_cxlen(struct fusb300 *fusb300, u32 length)
332 {
333 u32 reg;
334
335 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
336 reg &= ~FUSB300_CSR_LEN_MSK;
337 reg |= FUSB300_CSR_LEN(length);
338 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_CSR);
339 }
340
341 /* write data to cx fifo */
342 static void fusb300_wrcxf(struct fusb300_ep *ep,
343 struct fusb300_request *req)
344 {
345 int i = 0;
346 u8 *tmp;
347 u32 data;
348 struct fusb300 *fusb300 = ep->fusb300;
349 u32 length = req->req.length - req->req.actual;
350
351 tmp = req->req.buf + req->req.actual;
352
353 if (length > SS_CTL_MAX_PACKET_SIZE) {
354 fusb300_set_cxlen(fusb300, SS_CTL_MAX_PACKET_SIZE);
355 for (i = (SS_CTL_MAX_PACKET_SIZE >> 2); i > 0; i--) {
356 data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
357 *(tmp + 3) << 24;
358 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
359 tmp += 4;
360 }
361 req->req.actual += SS_CTL_MAX_PACKET_SIZE;
362 } else { /* length is less than max packet size */
363 fusb300_set_cxlen(fusb300, length);
364 for (i = length >> 2; i > 0; i--) {
365 data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
366 *(tmp + 3) << 24;
367 printk(KERN_DEBUG " 0x%x\n", data);
368 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
369 tmp = tmp + 4;
370 }
371 switch (length % 4) {
372 case 1:
373 data = *tmp;
374 printk(KERN_DEBUG " 0x%x\n", data);
375 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
376 break;
377 case 2:
378 data = *tmp | *(tmp + 1) << 8;
379 printk(KERN_DEBUG " 0x%x\n", data);
380 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
381 break;
382 case 3:
383 data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
384 printk(KERN_DEBUG " 0x%x\n", data);
385 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
386 break;
387 default:
388 break;
389 }
390 req->req.actual += length;
391 }
392 }
393
394 static void fusb300_set_epnstall(struct fusb300 *fusb300, u8 ep)
395 {
396 fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
397 FUSB300_EPSET0_STL);
398 }
399
400 static void fusb300_clear_epnstall(struct fusb300 *fusb300, u8 ep)
401 {
402 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
403
404 if (reg & FUSB300_EPSET0_STL) {
405 printk(KERN_DEBUG "EP%d stall... Clear!!\n", ep);
406 reg &= ~FUSB300_EPSET0_STL;
407 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
408 }
409 }
410
411 static void ep0_queue(struct fusb300_ep *ep, struct fusb300_request *req)
412 {
413 if (ep->fusb300->ep0_dir) { /* if IN */
414 if (req->req.length) {
415 fusb300_wrcxf(ep, req);
416 } else
417 printk(KERN_DEBUG "%s : req->req.length = 0x%x\n",
418 __func__, req->req.length);
419 if ((req->req.length == req->req.actual) ||
420 (req->req.actual < ep->ep.maxpacket))
421 done(ep, req, 0);
422 } else { /* OUT */
423 if (!req->req.length)
424 done(ep, req, 0);
425 else
426 fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER1,
427 FUSB300_IGER1_CX_OUT_INT);
428 }
429 }
430
431 static int fusb300_queue(struct usb_ep *_ep, struct usb_request *_req,
432 gfp_t gfp_flags)
433 {
434 struct fusb300_ep *ep;
435 struct fusb300_request *req;
436 unsigned long flags;
437 int request = 0;
438
439 ep = container_of(_ep, struct fusb300_ep, ep);
440 req = container_of(_req, struct fusb300_request, req);
441
442 if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
443 return -ESHUTDOWN;
444
445 spin_lock_irqsave(&ep->fusb300->lock, flags);
446
447 if (list_empty(&ep->queue))
448 request = 1;
449
450 list_add_tail(&req->queue, &ep->queue);
451
452 req->req.actual = 0;
453 req->req.status = -EINPROGRESS;
454
455 if (ep->desc == NULL) /* ep0 */
456 ep0_queue(ep, req);
457 else if (request && !ep->stall)
458 enable_fifo_int(ep);
459
460 spin_unlock_irqrestore(&ep->fusb300->lock, flags);
461
462 return 0;
463 }
464
465 static int fusb300_dequeue(struct usb_ep *_ep, struct usb_request *_req)
466 {
467 struct fusb300_ep *ep;
468 struct fusb300_request *req;
469 unsigned long flags;
470
471 ep = container_of(_ep, struct fusb300_ep, ep);
472 req = container_of(_req, struct fusb300_request, req);
473
474 spin_lock_irqsave(&ep->fusb300->lock, flags);
475 if (!list_empty(&ep->queue))
476 done(ep, req, -ECONNRESET);
477 spin_unlock_irqrestore(&ep->fusb300->lock, flags);
478
479 return 0;
480 }
481
482 static int fusb300_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
483 {
484 struct fusb300_ep *ep;
485 struct fusb300 *fusb300;
486 unsigned long flags;
487 int ret = 0;
488
489 ep = container_of(_ep, struct fusb300_ep, ep);
490
491 fusb300 = ep->fusb300;
492
493 spin_lock_irqsave(&ep->fusb300->lock, flags);
494
495 if (!list_empty(&ep->queue)) {
496 ret = -EAGAIN;
497 goto out;
498 }
499
500 if (value) {
501 fusb300_set_epnstall(fusb300, ep->epnum);
502 ep->stall = 1;
503 if (wedge)
504 ep->wedged = 1;
505 } else {
506 fusb300_clear_epnstall(fusb300, ep->epnum);
507 ep->stall = 0;
508 ep->wedged = 0;
509 }
510
511 out:
512 spin_unlock_irqrestore(&ep->fusb300->lock, flags);
513 return ret;
514 }
515
516 static int fusb300_set_halt(struct usb_ep *_ep, int value)
517 {
518 return fusb300_set_halt_and_wedge(_ep, value, 0);
519 }
520
521 static int fusb300_set_wedge(struct usb_ep *_ep)
522 {
523 return fusb300_set_halt_and_wedge(_ep, 1, 1);
524 }
525
526 static void fusb300_fifo_flush(struct usb_ep *_ep)
527 {
528 }
529
530 static struct usb_ep_ops fusb300_ep_ops = {
531 .enable = fusb300_enable,
532 .disable = fusb300_disable,
533
534 .alloc_request = fusb300_alloc_request,
535 .free_request = fusb300_free_request,
536
537 .queue = fusb300_queue,
538 .dequeue = fusb300_dequeue,
539
540 .set_halt = fusb300_set_halt,
541 .fifo_flush = fusb300_fifo_flush,
542 .set_wedge = fusb300_set_wedge,
543 };
544
545 /*****************************************************************************/
546 static void fusb300_clear_int(struct fusb300 *fusb300, u32 offset,
547 u32 value)
548 {
549 iowrite32(value, fusb300->reg + offset);
550 }
551
552 static void fusb300_reset(void)
553 {
554 }
555
556 static void fusb300_set_cxstall(struct fusb300 *fusb300)
557 {
558 fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
559 FUSB300_CSR_STL);
560 }
561
562 static void fusb300_set_cxdone(struct fusb300 *fusb300)
563 {
564 fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
565 FUSB300_CSR_DONE);
566 }
567
568 /* read data from cx fifo */
569 void fusb300_rdcxf(struct fusb300 *fusb300,
570 u8 *buffer, u32 length)
571 {
572 int i = 0;
573 u8 *tmp;
574 u32 data;
575
576 tmp = buffer;
577
578 for (i = (length >> 2); i > 0; i--) {
579 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
580 printk(KERN_DEBUG " 0x%x\n", data);
581 *tmp = data & 0xFF;
582 *(tmp + 1) = (data >> 8) & 0xFF;
583 *(tmp + 2) = (data >> 16) & 0xFF;
584 *(tmp + 3) = (data >> 24) & 0xFF;
585 tmp = tmp + 4;
586 }
587
588 switch (length % 4) {
589 case 1:
590 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
591 printk(KERN_DEBUG " 0x%x\n", data);
592 *tmp = data & 0xFF;
593 break;
594 case 2:
595 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
596 printk(KERN_DEBUG " 0x%x\n", data);
597 *tmp = data & 0xFF;
598 *(tmp + 1) = (data >> 8) & 0xFF;
599 break;
600 case 3:
601 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
602 printk(KERN_DEBUG " 0x%x\n", data);
603 *tmp = data & 0xFF;
604 *(tmp + 1) = (data >> 8) & 0xFF;
605 *(tmp + 2) = (data >> 16) & 0xFF;
606 break;
607 default:
608 break;
609 }
610 }
611
612 #if 0
613 static void fusb300_dbg_fifo(struct fusb300_ep *ep,
614 u8 entry, u16 length)
615 {
616 u32 reg;
617 u32 i = 0;
618 u32 j = 0;
619
620 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_GTM);
621 reg &= ~(FUSB300_GTM_TST_EP_ENTRY(0xF) |
622 FUSB300_GTM_TST_EP_NUM(0xF) | FUSB300_GTM_TST_FIFO_DEG);
623 reg |= (FUSB300_GTM_TST_EP_ENTRY(entry) |
624 FUSB300_GTM_TST_EP_NUM(ep->epnum) | FUSB300_GTM_TST_FIFO_DEG);
625 iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_GTM);
626
627 for (i = 0; i < (length >> 2); i++) {
628 if (i * 4 == 1024)
629 break;
630 reg = ioread32(ep->fusb300->reg +
631 FUSB300_OFFSET_BUFDBG_START + i * 4);
632 printk(KERN_DEBUG" 0x%-8x", reg);
633 j++;
634 if ((j % 4) == 0)
635 printk(KERN_DEBUG "\n");
636 }
637
638 if (length % 4) {
639 reg = ioread32(ep->fusb300->reg +
640 FUSB300_OFFSET_BUFDBG_START + i * 4);
641 printk(KERN_DEBUG " 0x%x\n", reg);
642 }
643
644 if ((j % 4) != 0)
645 printk(KERN_DEBUG "\n");
646
647 fusb300_disable_bit(ep->fusb300, FUSB300_OFFSET_GTM,
648 FUSB300_GTM_TST_FIFO_DEG);
649 }
650
651 static void fusb300_cmp_dbg_fifo(struct fusb300_ep *ep,
652 u8 entry, u16 length, u8 *golden)
653 {
654 u32 reg;
655 u32 i = 0;
656 u32 golden_value;
657 u8 *tmp;
658
659 tmp = golden;
660
661 printk(KERN_DEBUG "fusb300_cmp_dbg_fifo (entry %d) : start\n", entry);
662
663 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_GTM);
664 reg &= ~(FUSB300_GTM_TST_EP_ENTRY(0xF) |
665 FUSB300_GTM_TST_EP_NUM(0xF) | FUSB300_GTM_TST_FIFO_DEG);
666 reg |= (FUSB300_GTM_TST_EP_ENTRY(entry) |
667 FUSB300_GTM_TST_EP_NUM(ep->epnum) | FUSB300_GTM_TST_FIFO_DEG);
668 iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_GTM);
669
670 for (i = 0; i < (length >> 2); i++) {
671 if (i * 4 == 1024)
672 break;
673 golden_value = *tmp | *(tmp + 1) << 8 |
674 *(tmp + 2) << 16 | *(tmp + 3) << 24;
675
676 reg = ioread32(ep->fusb300->reg +
677 FUSB300_OFFSET_BUFDBG_START + i*4);
678
679 if (reg != golden_value) {
680 printk(KERN_DEBUG "0x%x : ", (u32)(ep->fusb300->reg +
681 FUSB300_OFFSET_BUFDBG_START + i*4));
682 printk(KERN_DEBUG " golden = 0x%x, reg = 0x%x\n",
683 golden_value, reg);
684 }
685 tmp += 4;
686 }
687
688 switch (length % 4) {
689 case 1:
690 golden_value = *tmp;
691 case 2:
692 golden_value = *tmp | *(tmp + 1) << 8;
693 case 3:
694 golden_value = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
695 default:
696 break;
697
698 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_BUFDBG_START + i*4);
699 if (reg != golden_value) {
700 printk(KERN_DEBUG "0x%x:", (u32)(ep->fusb300->reg +
701 FUSB300_OFFSET_BUFDBG_START + i*4));
702 printk(KERN_DEBUG " golden = 0x%x, reg = 0x%x\n",
703 golden_value, reg);
704 }
705 }
706
707 printk(KERN_DEBUG "fusb300_cmp_dbg_fifo : end\n");
708 fusb300_disable_bit(ep->fusb300, FUSB300_OFFSET_GTM,
709 FUSB300_GTM_TST_FIFO_DEG);
710 }
711 #endif
712
713 static void fusb300_rdfifo(struct fusb300_ep *ep,
714 struct fusb300_request *req,
715 u32 length)
716 {
717 int i = 0;
718 u8 *tmp;
719 u32 data, reg;
720 struct fusb300 *fusb300 = ep->fusb300;
721
722 tmp = req->req.buf + req->req.actual;
723 req->req.actual += length;
724
725 if (req->req.actual > req->req.length)
726 printk(KERN_DEBUG "req->req.actual > req->req.length\n");
727
728 for (i = (length >> 2); i > 0; i--) {
729 data = ioread32(fusb300->reg +
730 FUSB300_OFFSET_EPPORT(ep->epnum));
731 *tmp = data & 0xFF;
732 *(tmp + 1) = (data >> 8) & 0xFF;
733 *(tmp + 2) = (data >> 16) & 0xFF;
734 *(tmp + 3) = (data >> 24) & 0xFF;
735 tmp = tmp + 4;
736 }
737
738 switch (length % 4) {
739 case 1:
740 data = ioread32(fusb300->reg +
741 FUSB300_OFFSET_EPPORT(ep->epnum));
742 *tmp = data & 0xFF;
743 break;
744 case 2:
745 data = ioread32(fusb300->reg +
746 FUSB300_OFFSET_EPPORT(ep->epnum));
747 *tmp = data & 0xFF;
748 *(tmp + 1) = (data >> 8) & 0xFF;
749 break;
750 case 3:
751 data = ioread32(fusb300->reg +
752 FUSB300_OFFSET_EPPORT(ep->epnum));
753 *tmp = data & 0xFF;
754 *(tmp + 1) = (data >> 8) & 0xFF;
755 *(tmp + 2) = (data >> 16) & 0xFF;
756 break;
757 default:
758 break;
759 }
760
761 do {
762 reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
763 reg &= FUSB300_IGR1_SYNF0_EMPTY_INT;
764 if (i)
765 printk(KERN_INFO "sync fifo is not empty!\n");
766 i++;
767 } while (!reg);
768 }
769
770 static u8 fusb300_get_epnstall(struct fusb300 *fusb300, u8 ep)
771 {
772 u8 value;
773 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
774
775 value = reg & FUSB300_EPSET0_STL;
776
777 return value;
778 }
779
780 static u8 fusb300_get_cxstall(struct fusb300 *fusb300)
781 {
782 u8 value;
783 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
784
785 value = (reg & FUSB300_CSR_STL) >> 1;
786
787 return value;
788 }
789
790 static void request_error(struct fusb300 *fusb300)
791 {
792 fusb300_set_cxstall(fusb300);
793 printk(KERN_DEBUG "request error!!\n");
794 }
795
796 static void get_status(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
797 __releases(fusb300->lock)
798 __acquires(fusb300->lock)
799 {
800 u8 ep;
801 u16 status = 0;
802 u16 w_index = ctrl->wIndex;
803
804 switch (ctrl->bRequestType & USB_RECIP_MASK) {
805 case USB_RECIP_DEVICE:
806 status = 1 << USB_DEVICE_SELF_POWERED;
807 break;
808 case USB_RECIP_INTERFACE:
809 status = 0;
810 break;
811 case USB_RECIP_ENDPOINT:
812 ep = w_index & USB_ENDPOINT_NUMBER_MASK;
813 if (ep) {
814 if (fusb300_get_epnstall(fusb300, ep))
815 status = 1 << USB_ENDPOINT_HALT;
816 } else {
817 if (fusb300_get_cxstall(fusb300))
818 status = 0;
819 }
820 break;
821
822 default:
823 request_error(fusb300);
824 return; /* exit */
825 }
826
827 fusb300->ep0_data = cpu_to_le16(status);
828 fusb300->ep0_req->buf = &fusb300->ep0_data;
829 fusb300->ep0_req->length = 2;
830
831 spin_unlock(&fusb300->lock);
832 fusb300_queue(fusb300->gadget.ep0, fusb300->ep0_req, GFP_KERNEL);
833 spin_lock(&fusb300->lock);
834 }
835
836 static void set_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
837 {
838 u8 ep;
839
840 switch (ctrl->bRequestType & USB_RECIP_MASK) {
841 case USB_RECIP_DEVICE:
842 fusb300_set_cxdone(fusb300);
843 break;
844 case USB_RECIP_INTERFACE:
845 fusb300_set_cxdone(fusb300);
846 break;
847 case USB_RECIP_ENDPOINT: {
848 u16 w_index = le16_to_cpu(ctrl->wIndex);
849
850 ep = w_index & USB_ENDPOINT_NUMBER_MASK;
851 if (ep)
852 fusb300_set_epnstall(fusb300, ep);
853 else
854 fusb300_set_cxstall(fusb300);
855 fusb300_set_cxdone(fusb300);
856 }
857 break;
858 default:
859 request_error(fusb300);
860 break;
861 }
862 }
863
864 static void fusb300_clear_seqnum(struct fusb300 *fusb300, u8 ep)
865 {
866 fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
867 FUSB300_EPSET0_CLRSEQNUM);
868 }
869
870 static void clear_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
871 {
872 struct fusb300_ep *ep =
873 fusb300->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
874
875 switch (ctrl->bRequestType & USB_RECIP_MASK) {
876 case USB_RECIP_DEVICE:
877 fusb300_set_cxdone(fusb300);
878 break;
879 case USB_RECIP_INTERFACE:
880 fusb300_set_cxdone(fusb300);
881 break;
882 case USB_RECIP_ENDPOINT:
883 if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
884 if (ep->wedged) {
885 fusb300_set_cxdone(fusb300);
886 break;
887 }
888 if (ep->stall) {
889 ep->stall = 0;
890 fusb300_clear_seqnum(fusb300, ep->epnum);
891 fusb300_clear_epnstall(fusb300, ep->epnum);
892 if (!list_empty(&ep->queue))
893 enable_fifo_int(ep);
894 }
895 }
896 fusb300_set_cxdone(fusb300);
897 break;
898 default:
899 request_error(fusb300);
900 break;
901 }
902 }
903
904 static void fusb300_set_dev_addr(struct fusb300 *fusb300, u16 addr)
905 {
906 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_DAR);
907
908 reg &= ~FUSB300_DAR_DRVADDR_MSK;
909 reg |= FUSB300_DAR_DRVADDR(addr);
910
911 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_DAR);
912 }
913
914 static void set_address(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
915 {
916 if (ctrl->wValue >= 0x0100)
917 request_error(fusb300);
918 else {
919 fusb300_set_dev_addr(fusb300, ctrl->wValue);
920 fusb300_set_cxdone(fusb300);
921 }
922 }
923
924 #define UVC_COPY_DESCRIPTORS(mem, src) \
925 do { \
926 const struct usb_descriptor_header * const *__src; \
927 for (__src = src; *__src; ++__src) { \
928 memcpy(mem, *__src, (*__src)->bLength); \
929 mem += (*__src)->bLength; \
930 } \
931 } while (0)
932
933 static int setup_packet(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
934 {
935 u8 *p = (u8 *)ctrl;
936 u8 ret = 0;
937 u8 i = 0;
938
939 fusb300_rdcxf(fusb300, p, 8);
940 fusb300->ep0_dir = ctrl->bRequestType & USB_DIR_IN;
941 fusb300->ep0_length = ctrl->wLength;
942
943 /* check request */
944 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
945 switch (ctrl->bRequest) {
946 case USB_REQ_GET_STATUS:
947 get_status(fusb300, ctrl);
948 break;
949 case USB_REQ_CLEAR_FEATURE:
950 clear_feature(fusb300, ctrl);
951 break;
952 case USB_REQ_SET_FEATURE:
953 set_feature(fusb300, ctrl);
954 break;
955 case USB_REQ_SET_ADDRESS:
956 set_address(fusb300, ctrl);
957 break;
958 case USB_REQ_SET_CONFIGURATION:
959 fusb300_enable_bit(fusb300, FUSB300_OFFSET_DAR,
960 FUSB300_DAR_SETCONFG);
961 /* clear sequence number */
962 for (i = 1; i <= FUSB300_MAX_NUM_EP; i++)
963 fusb300_clear_seqnum(fusb300, i);
964 fusb300->reenum = 1;
965 ret = 1;
966 break;
967 default:
968 ret = 1;
969 break;
970 }
971 } else
972 ret = 1;
973
974 return ret;
975 }
976
977 static void done(struct fusb300_ep *ep, struct fusb300_request *req,
978 int status)
979 {
980 list_del_init(&req->queue);
981
982 /* don't modify queue heads during completion callback */
983 if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
984 req->req.status = -ESHUTDOWN;
985 else
986 req->req.status = status;
987
988 spin_unlock(&ep->fusb300->lock);
989 req->req.complete(&ep->ep, &req->req);
990 spin_lock(&ep->fusb300->lock);
991
992 if (ep->epnum) {
993 disable_fifo_int(ep);
994 if (!list_empty(&ep->queue))
995 enable_fifo_int(ep);
996 } else
997 fusb300_set_cxdone(ep->fusb300);
998 }
999
1000 static void fusb300_fill_idma_prdtbl(struct fusb300_ep *ep, dma_addr_t d,
1001 u32 len)
1002 {
1003 u32 value;
1004 u32 reg;
1005
1006 /* wait SW owner */
1007 do {
1008 reg = ioread32(ep->fusb300->reg +
1009 FUSB300_OFFSET_EPPRD_W0(ep->epnum));
1010 reg &= FUSB300_EPPRD0_H;
1011 } while (reg);
1012
1013 iowrite32(d, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W1(ep->epnum));
1014
1015 value = FUSB300_EPPRD0_BTC(len) | FUSB300_EPPRD0_H |
1016 FUSB300_EPPRD0_F | FUSB300_EPPRD0_L | FUSB300_EPPRD0_I;
1017 iowrite32(value, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W0(ep->epnum));
1018
1019 iowrite32(0x0, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W2(ep->epnum));
1020
1021 fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_EPPRDRDY,
1022 FUSB300_EPPRDR_EP_PRD_RDY(ep->epnum));
1023 }
1024
1025 static void fusb300_wait_idma_finished(struct fusb300_ep *ep)
1026 {
1027 u32 reg;
1028
1029 do {
1030 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR1);
1031 if ((reg & FUSB300_IGR1_VBUS_CHG_INT) ||
1032 (reg & FUSB300_IGR1_WARM_RST_INT) ||
1033 (reg & FUSB300_IGR1_HOT_RST_INT) ||
1034 (reg & FUSB300_IGR1_USBRST_INT)
1035 )
1036 goto IDMA_RESET;
1037 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR0);
1038 reg &= FUSB300_IGR0_EPn_PRD_INT(ep->epnum);
1039 } while (!reg);
1040
1041 fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGR0,
1042 FUSB300_IGR0_EPn_PRD_INT(ep->epnum));
1043 IDMA_RESET:
1044 fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGER0,
1045 FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
1046 }
1047
1048 static void fusb300_set_idma(struct fusb300_ep *ep,
1049 struct fusb300_request *req)
1050 {
1051 dma_addr_t d;
1052
1053 d = dma_map_single(NULL, req->req.buf, req->req.length, DMA_TO_DEVICE);
1054
1055 if (dma_mapping_error(NULL, d)) {
1056 printk(KERN_DEBUG "dma_mapping_error\n");
1057 return;
1058 }
1059
1060 dma_sync_single_for_device(NULL, d, req->req.length, DMA_TO_DEVICE);
1061
1062 fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER0,
1063 FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
1064
1065 fusb300_fill_idma_prdtbl(ep, d, req->req.length);
1066 /* check idma is done */
1067 fusb300_wait_idma_finished(ep);
1068
1069 dma_unmap_single(NULL, d, req->req.length, DMA_TO_DEVICE);
1070 }
1071
1072 static void in_ep_fifo_handler(struct fusb300_ep *ep)
1073 {
1074 struct fusb300_request *req = list_entry(ep->queue.next,
1075 struct fusb300_request, queue);
1076
1077 if (req->req.length)
1078 fusb300_set_idma(ep, req);
1079 done(ep, req, 0);
1080 }
1081
1082 static void out_ep_fifo_handler(struct fusb300_ep *ep)
1083 {
1084 struct fusb300 *fusb300 = ep->fusb300;
1085 struct fusb300_request *req = list_entry(ep->queue.next,
1086 struct fusb300_request, queue);
1087 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum));
1088 u32 length = reg & FUSB300_FFR_BYCNT;
1089
1090 fusb300_rdfifo(ep, req, length);
1091
1092 /* finish out transfer */
1093 if ((req->req.length == req->req.actual) || (length < ep->ep.maxpacket))
1094 done(ep, req, 0);
1095 }
1096
1097 static void check_device_mode(struct fusb300 *fusb300)
1098 {
1099 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_GCR);
1100
1101 switch (reg & FUSB300_GCR_DEVEN_MSK) {
1102 case FUSB300_GCR_DEVEN_SS:
1103 fusb300->gadget.speed = USB_SPEED_SUPER;
1104 break;
1105 case FUSB300_GCR_DEVEN_HS:
1106 fusb300->gadget.speed = USB_SPEED_HIGH;
1107 break;
1108 case FUSB300_GCR_DEVEN_FS:
1109 fusb300->gadget.speed = USB_SPEED_FULL;
1110 break;
1111 default:
1112 fusb300->gadget.speed = USB_SPEED_UNKNOWN;
1113 break;
1114 }
1115 printk(KERN_INFO "dev_mode = %d\n", (reg & FUSB300_GCR_DEVEN_MSK));
1116 }
1117
1118
1119 static void fusb300_ep0out(struct fusb300 *fusb300)
1120 {
1121 struct fusb300_ep *ep = fusb300->ep[0];
1122 u32 reg;
1123
1124 if (!list_empty(&ep->queue)) {
1125 struct fusb300_request *req;
1126
1127 req = list_first_entry(&ep->queue,
1128 struct fusb300_request, queue);
1129 if (req->req.length)
1130 fusb300_rdcxf(ep->fusb300, req->req.buf,
1131 req->req.length);
1132 done(ep, req, 0);
1133 reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
1134 reg &= ~FUSB300_IGER1_CX_OUT_INT;
1135 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_IGER1);
1136 } else
1137 pr_err("%s : empty queue\n", __func__);
1138 }
1139
1140 static void fusb300_ep0in(struct fusb300 *fusb300)
1141 {
1142 struct fusb300_request *req;
1143 struct fusb300_ep *ep = fusb300->ep[0];
1144
1145 if ((!list_empty(&ep->queue)) && (fusb300->ep0_dir)) {
1146 req = list_entry(ep->queue.next,
1147 struct fusb300_request, queue);
1148 if (req->req.length)
1149 fusb300_wrcxf(ep, req);
1150 if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
1151 done(ep, req, 0);
1152 } else
1153 fusb300_set_cxdone(fusb300);
1154 }
1155
1156 static void fusb300_grp2_handler(void)
1157 {
1158 }
1159
1160 static void fusb300_grp3_handler(void)
1161 {
1162 }
1163
1164 static void fusb300_grp4_handler(void)
1165 {
1166 }
1167
1168 static void fusb300_grp5_handler(void)
1169 {
1170 }
1171
1172 static irqreturn_t fusb300_irq(int irq, void *_fusb300)
1173 {
1174 struct fusb300 *fusb300 = _fusb300;
1175 u32 int_grp1 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
1176 u32 int_grp1_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
1177 u32 int_grp0 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR0);
1178 u32 int_grp0_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER0);
1179 struct usb_ctrlrequest ctrl;
1180 u8 in;
1181 u32 reg;
1182 int i;
1183
1184 spin_lock(&fusb300->lock);
1185
1186 int_grp1 &= int_grp1_en;
1187 int_grp0 &= int_grp0_en;
1188
1189 if (int_grp1 & FUSB300_IGR1_WARM_RST_INT) {
1190 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1191 FUSB300_IGR1_WARM_RST_INT);
1192 printk(KERN_INFO"fusb300_warmreset\n");
1193 fusb300_reset();
1194 }
1195
1196 if (int_grp1 & FUSB300_IGR1_HOT_RST_INT) {
1197 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1198 FUSB300_IGR1_HOT_RST_INT);
1199 printk(KERN_INFO"fusb300_hotreset\n");
1200 fusb300_reset();
1201 }
1202
1203 if (int_grp1 & FUSB300_IGR1_USBRST_INT) {
1204 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1205 FUSB300_IGR1_USBRST_INT);
1206 fusb300_reset();
1207 }
1208 /* COMABT_INT has a highest priority */
1209
1210 if (int_grp1 & FUSB300_IGR1_CX_COMABT_INT) {
1211 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1212 FUSB300_IGR1_CX_COMABT_INT);
1213 printk(KERN_INFO"fusb300_ep0abt\n");
1214 }
1215
1216 if (int_grp1 & FUSB300_IGR1_VBUS_CHG_INT) {
1217 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1218 FUSB300_IGR1_VBUS_CHG_INT);
1219 printk(KERN_INFO"fusb300_vbus_change\n");
1220 }
1221
1222 if (int_grp1 & FUSB300_IGR1_U3_EXIT_FAIL_INT) {
1223 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1224 FUSB300_IGR1_U3_EXIT_FAIL_INT);
1225 }
1226
1227 if (int_grp1 & FUSB300_IGR1_U2_EXIT_FAIL_INT) {
1228 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1229 FUSB300_IGR1_U2_EXIT_FAIL_INT);
1230 }
1231
1232 if (int_grp1 & FUSB300_IGR1_U1_EXIT_FAIL_INT) {
1233 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1234 FUSB300_IGR1_U1_EXIT_FAIL_INT);
1235 }
1236
1237 if (int_grp1 & FUSB300_IGR1_U2_ENTRY_FAIL_INT) {
1238 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1239 FUSB300_IGR1_U2_ENTRY_FAIL_INT);
1240 }
1241
1242 if (int_grp1 & FUSB300_IGR1_U1_ENTRY_FAIL_INT) {
1243 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1244 FUSB300_IGR1_U1_ENTRY_FAIL_INT);
1245 }
1246
1247 if (int_grp1 & FUSB300_IGR1_U3_EXIT_INT) {
1248 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1249 FUSB300_IGR1_U3_EXIT_INT);
1250 printk(KERN_INFO "FUSB300_IGR1_U3_EXIT_INT\n");
1251 }
1252
1253 if (int_grp1 & FUSB300_IGR1_U2_EXIT_INT) {
1254 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1255 FUSB300_IGR1_U2_EXIT_INT);
1256 printk(KERN_INFO "FUSB300_IGR1_U2_EXIT_INT\n");
1257 }
1258
1259 if (int_grp1 & FUSB300_IGR1_U1_EXIT_INT) {
1260 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1261 FUSB300_IGR1_U1_EXIT_INT);
1262 printk(KERN_INFO "FUSB300_IGR1_U1_EXIT_INT\n");
1263 }
1264
1265 if (int_grp1 & FUSB300_IGR1_U3_ENTRY_INT) {
1266 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1267 FUSB300_IGR1_U3_ENTRY_INT);
1268 printk(KERN_INFO "FUSB300_IGR1_U3_ENTRY_INT\n");
1269 fusb300_enable_bit(fusb300, FUSB300_OFFSET_SSCR1,
1270 FUSB300_SSCR1_GO_U3_DONE);
1271 }
1272
1273 if (int_grp1 & FUSB300_IGR1_U2_ENTRY_INT) {
1274 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1275 FUSB300_IGR1_U2_ENTRY_INT);
1276 printk(KERN_INFO "FUSB300_IGR1_U2_ENTRY_INT\n");
1277 }
1278
1279 if (int_grp1 & FUSB300_IGR1_U1_ENTRY_INT) {
1280 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1281 FUSB300_IGR1_U1_ENTRY_INT);
1282 printk(KERN_INFO "FUSB300_IGR1_U1_ENTRY_INT\n");
1283 }
1284
1285 if (int_grp1 & FUSB300_IGR1_RESM_INT) {
1286 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1287 FUSB300_IGR1_RESM_INT);
1288 printk(KERN_INFO "fusb300_resume\n");
1289 }
1290
1291 if (int_grp1 & FUSB300_IGR1_SUSP_INT) {
1292 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1293 FUSB300_IGR1_SUSP_INT);
1294 printk(KERN_INFO "fusb300_suspend\n");
1295 }
1296
1297 if (int_grp1 & FUSB300_IGR1_HS_LPM_INT) {
1298 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1299 FUSB300_IGR1_HS_LPM_INT);
1300 printk(KERN_INFO "fusb300_HS_LPM_INT\n");
1301 }
1302
1303 if (int_grp1 & FUSB300_IGR1_DEV_MODE_CHG_INT) {
1304 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1305 FUSB300_IGR1_DEV_MODE_CHG_INT);
1306 check_device_mode(fusb300);
1307 }
1308
1309 if (int_grp1 & FUSB300_IGR1_CX_COMFAIL_INT) {
1310 fusb300_set_cxstall(fusb300);
1311 printk(KERN_INFO "fusb300_ep0fail\n");
1312 }
1313
1314 if (int_grp1 & FUSB300_IGR1_CX_SETUP_INT) {
1315 printk(KERN_INFO "fusb300_ep0setup\n");
1316 if (setup_packet(fusb300, &ctrl)) {
1317 spin_unlock(&fusb300->lock);
1318 if (fusb300->driver->setup(&fusb300->gadget, &ctrl) < 0)
1319 fusb300_set_cxstall(fusb300);
1320 spin_lock(&fusb300->lock);
1321 }
1322 }
1323
1324 if (int_grp1 & FUSB300_IGR1_CX_CMDEND_INT)
1325 printk(KERN_INFO "fusb300_cmdend\n");
1326
1327
1328 if (int_grp1 & FUSB300_IGR1_CX_OUT_INT) {
1329 printk(KERN_INFO "fusb300_cxout\n");
1330 fusb300_ep0out(fusb300);
1331 }
1332
1333 if (int_grp1 & FUSB300_IGR1_CX_IN_INT) {
1334 printk(KERN_INFO "fusb300_cxin\n");
1335 fusb300_ep0in(fusb300);
1336 }
1337
1338 if (int_grp1 & FUSB300_IGR1_INTGRP5)
1339 fusb300_grp5_handler();
1340
1341 if (int_grp1 & FUSB300_IGR1_INTGRP4)
1342 fusb300_grp4_handler();
1343
1344 if (int_grp1 & FUSB300_IGR1_INTGRP3)
1345 fusb300_grp3_handler();
1346
1347 if (int_grp1 & FUSB300_IGR1_INTGRP2)
1348 fusb300_grp2_handler();
1349
1350 if (int_grp0) {
1351 for (i = 1; i < FUSB300_MAX_NUM_EP; i++) {
1352 if (int_grp0 & FUSB300_IGR0_EPn_FIFO_INT(i)) {
1353 reg = ioread32(fusb300->reg +
1354 FUSB300_OFFSET_EPSET1(i));
1355 in = (reg & FUSB300_EPSET1_DIRIN) ? 1 : 0;
1356 if (in)
1357 in_ep_fifo_handler(fusb300->ep[i]);
1358 else
1359 out_ep_fifo_handler(fusb300->ep[i]);
1360 }
1361 }
1362 }
1363
1364 spin_unlock(&fusb300->lock);
1365
1366 return IRQ_HANDLED;
1367 }
1368
1369 static void fusb300_set_u2_timeout(struct fusb300 *fusb300,
1370 u32 time)
1371 {
1372 u32 reg;
1373
1374 reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
1375 reg &= ~0xff;
1376 reg |= FUSB300_SSCR2_U2TIMEOUT(time);
1377
1378 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
1379 }
1380
1381 static void fusb300_set_u1_timeout(struct fusb300 *fusb300,
1382 u32 time)
1383 {
1384 u32 reg;
1385
1386 reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
1387 reg &= ~(0xff << 8);
1388 reg |= FUSB300_SSCR2_U1TIMEOUT(time);
1389
1390 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
1391 }
1392
1393 static void init_controller(struct fusb300 *fusb300)
1394 {
1395 u32 reg;
1396 u32 mask = 0;
1397 u32 val = 0;
1398
1399 /* split on */
1400 mask = val = FUSB300_AHBBCR_S0_SPLIT_ON | FUSB300_AHBBCR_S1_SPLIT_ON;
1401 reg = ioread32(fusb300->reg + FUSB300_OFFSET_AHBCR);
1402 reg &= ~mask;
1403 reg |= val;
1404 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_AHBCR);
1405
1406 /* enable high-speed LPM */
1407 mask = val = FUSB300_HSCR_HS_LPM_PERMIT;
1408 reg = ioread32(fusb300->reg + FUSB300_OFFSET_HSCR);
1409 reg &= ~mask;
1410 reg |= val;
1411 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_HSCR);
1412
1413 /*set u1 u2 timmer*/
1414 fusb300_set_u2_timeout(fusb300, 0xff);
1415 fusb300_set_u1_timeout(fusb300, 0xff);
1416
1417 /* enable all grp1 interrupt */
1418 iowrite32(0xcfffff9f, fusb300->reg + FUSB300_OFFSET_IGER1);
1419 }
1420 /*------------------------------------------------------------------------*/
1421 static struct fusb300 *the_controller;
1422
1423 static int fusb300_udc_start(struct usb_gadget_driver *driver,
1424 int (*bind)(struct usb_gadget *))
1425 {
1426 struct fusb300 *fusb300 = the_controller;
1427 int retval;
1428
1429 if (!driver
1430 || driver->speed < USB_SPEED_FULL
1431 || !bind
1432 || !driver->setup)
1433 return -EINVAL;
1434
1435 if (!fusb300)
1436 return -ENODEV;
1437
1438 if (fusb300->driver)
1439 return -EBUSY;
1440
1441 /* hook up the driver */
1442 driver->driver.bus = NULL;
1443 fusb300->driver = driver;
1444 fusb300->gadget.dev.driver = &driver->driver;
1445
1446 retval = device_add(&fusb300->gadget.dev);
1447 if (retval) {
1448 pr_err("device_add error (%d)\n", retval);
1449 goto error;
1450 }
1451
1452 retval = bind(&fusb300->gadget);
1453 if (retval) {
1454 pr_err("bind to driver error (%d)\n", retval);
1455 device_del(&fusb300->gadget.dev);
1456 goto error;
1457 }
1458
1459 return 0;
1460
1461 error:
1462 fusb300->driver = NULL;
1463 fusb300->gadget.dev.driver = NULL;
1464
1465 return retval;
1466 }
1467
1468 static int fusb300_udc_stop(struct usb_gadget_driver *driver)
1469 {
1470 struct fusb300 *fusb300 = the_controller;
1471
1472 if (driver != fusb300->driver || !driver->unbind)
1473 return -EINVAL;
1474
1475 driver->unbind(&fusb300->gadget);
1476 fusb300->gadget.dev.driver = NULL;
1477
1478 init_controller(fusb300);
1479 device_del(&fusb300->gadget.dev);
1480 fusb300->driver = NULL;
1481
1482 return 0;
1483 }
1484 /*--------------------------------------------------------------------------*/
1485
1486 static int fusb300_udc_pullup(struct usb_gadget *_gadget, int is_active)
1487 {
1488 return 0;
1489 }
1490
1491 static struct usb_gadget_ops fusb300_gadget_ops = {
1492 .pullup = fusb300_udc_pullup,
1493 .start = fusb300_udc_start,
1494 .stop = fusb300_udc_stop,
1495 };
1496
1497 static int __exit fusb300_remove(struct platform_device *pdev)
1498 {
1499 struct fusb300 *fusb300 = dev_get_drvdata(&pdev->dev);
1500
1501 usb_del_gadget_udc(&fusb300->gadget);
1502 iounmap(fusb300->reg);
1503 free_irq(platform_get_irq(pdev, 0), fusb300);
1504
1505 fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
1506 kfree(fusb300);
1507
1508 return 0;
1509 }
1510
1511 static int __init fusb300_probe(struct platform_device *pdev)
1512 {
1513 struct resource *res, *ires, *ires1;
1514 void __iomem *reg = NULL;
1515 struct fusb300 *fusb300 = NULL;
1516 struct fusb300_ep *_ep[FUSB300_MAX_NUM_EP];
1517 int ret = 0;
1518 int i;
1519
1520 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1521 if (!res) {
1522 ret = -ENODEV;
1523 pr_err("platform_get_resource error.\n");
1524 goto clean_up;
1525 }
1526
1527 ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1528 if (!ires) {
1529 ret = -ENODEV;
1530 dev_err(&pdev->dev,
1531 "platform_get_resource IORESOURCE_IRQ error.\n");
1532 goto clean_up;
1533 }
1534
1535 ires1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1536 if (!ires1) {
1537 ret = -ENODEV;
1538 dev_err(&pdev->dev,
1539 "platform_get_resource IORESOURCE_IRQ 1 error.\n");
1540 goto clean_up;
1541 }
1542
1543 reg = ioremap(res->start, resource_size(res));
1544 if (reg == NULL) {
1545 ret = -ENOMEM;
1546 pr_err("ioremap error.\n");
1547 goto clean_up;
1548 }
1549
1550 /* initialize udc */
1551 fusb300 = kzalloc(sizeof(struct fusb300), GFP_KERNEL);
1552 if (fusb300 == NULL) {
1553 pr_err("kzalloc error\n");
1554 goto clean_up;
1555 }
1556
1557 for (i = 0; i < FUSB300_MAX_NUM_EP; i++) {
1558 _ep[i] = kzalloc(sizeof(struct fusb300_ep), GFP_KERNEL);
1559 if (_ep[i] == NULL) {
1560 pr_err("_ep kzalloc error\n");
1561 goto clean_up;
1562 }
1563 fusb300->ep[i] = _ep[i];
1564 }
1565
1566 spin_lock_init(&fusb300->lock);
1567
1568 dev_set_drvdata(&pdev->dev, fusb300);
1569
1570 fusb300->gadget.ops = &fusb300_gadget_ops;
1571
1572 device_initialize(&fusb300->gadget.dev);
1573
1574 dev_set_name(&fusb300->gadget.dev, "gadget");
1575
1576 fusb300->gadget.is_dualspeed = 1;
1577 fusb300->gadget.dev.parent = &pdev->dev;
1578 fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask;
1579 fusb300->gadget.dev.release = pdev->dev.release;
1580 fusb300->gadget.name = udc_name;
1581 fusb300->reg = reg;
1582
1583 ret = request_irq(ires->start, fusb300_irq, IRQF_DISABLED | IRQF_SHARED,
1584 udc_name, fusb300);
1585 if (ret < 0) {
1586 pr_err("request_irq error (%d)\n", ret);
1587 goto clean_up;
1588 }
1589
1590 ret = request_irq(ires1->start, fusb300_irq,
1591 IRQF_DISABLED | IRQF_SHARED, udc_name, fusb300);
1592 if (ret < 0) {
1593 pr_err("request_irq1 error (%d)\n", ret);
1594 goto clean_up;
1595 }
1596
1597 INIT_LIST_HEAD(&fusb300->gadget.ep_list);
1598
1599 for (i = 0; i < FUSB300_MAX_NUM_EP ; i++) {
1600 struct fusb300_ep *ep = fusb300->ep[i];
1601
1602 if (i != 0) {
1603 INIT_LIST_HEAD(&fusb300->ep[i]->ep.ep_list);
1604 list_add_tail(&fusb300->ep[i]->ep.ep_list,
1605 &fusb300->gadget.ep_list);
1606 }
1607 ep->fusb300 = fusb300;
1608 INIT_LIST_HEAD(&ep->queue);
1609 ep->ep.name = fusb300_ep_name[i];
1610 ep->ep.ops = &fusb300_ep_ops;
1611 ep->ep.maxpacket = HS_BULK_MAX_PACKET_SIZE;
1612 }
1613 fusb300->ep[0]->ep.maxpacket = HS_CTL_MAX_PACKET_SIZE;
1614 fusb300->ep[0]->epnum = 0;
1615 fusb300->gadget.ep0 = &fusb300->ep[0]->ep;
1616 INIT_LIST_HEAD(&fusb300->gadget.ep0->ep_list);
1617
1618 the_controller = fusb300;
1619
1620 fusb300->ep0_req = fusb300_alloc_request(&fusb300->ep[0]->ep,
1621 GFP_KERNEL);
1622 if (fusb300->ep0_req == NULL)
1623 goto clean_up3;
1624
1625 init_controller(fusb300);
1626 ret = usb_add_gadget_udc(&pdev->dev, &fusb300->gadget);
1627 if (ret)
1628 goto err_add_udc;
1629
1630 dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
1631
1632 return 0;
1633 err_add_udc:
1634 fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
1635
1636 clean_up3:
1637 free_irq(ires->start, fusb300);
1638
1639 clean_up:
1640 if (fusb300) {
1641 if (fusb300->ep0_req)
1642 fusb300_free_request(&fusb300->ep[0]->ep,
1643 fusb300->ep0_req);
1644 kfree(fusb300);
1645 }
1646 if (reg)
1647 iounmap(reg);
1648
1649 return ret;
1650 }
1651
1652 static struct platform_driver fusb300_driver = {
1653 .remove = __exit_p(fusb300_remove),
1654 .driver = {
1655 .name = (char *) udc_name,
1656 .owner = THIS_MODULE,
1657 },
1658 };
1659
1660 static int __init fusb300_udc_init(void)
1661 {
1662 return platform_driver_probe(&fusb300_driver, fusb300_probe);
1663 }
1664
1665 module_init(fusb300_udc_init);
1666
1667 static void __exit fusb300_udc_cleanup(void)
1668 {
1669 platform_driver_unregister(&fusb300_driver);
1670 }
1671 module_exit(fusb300_udc_cleanup);
Linux with added FPC-III support