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Linux 2.6.20.9
[linux/fpc-iii.git] / arch / x86_64 / kernel / mpparse.c
blob08072568847d997ce0cc50d05ff3831ef33a07d9
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/bootmem.h>
20 #include <linux/smp_lock.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/acpi.h>
24 #include <linux/module.h>
25
26 #include <asm/smp.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/pgalloc.h>
30 #include <asm/io_apic.h>
31 #include <asm/proto.h>
32 #include <asm/acpi.h>
33
34 /* Have we found an MP table */
35 int smp_found_config;
36 unsigned int __initdata maxcpus = NR_CPUS;
37
38 /*
39 * Various Linux-internal data structures created from the
40 * MP-table.
41 */
42 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
43 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
44
45 static int mp_current_pci_id = 0;
46 /* I/O APIC entries */
47 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
48
49 /* # of MP IRQ source entries */
50 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
51
52 /* MP IRQ source entries */
53 int mp_irq_entries;
54
55 int nr_ioapics;
56 unsigned long mp_lapic_addr = 0;
57
58
59
60 /* Processor that is doing the boot up */
61 unsigned int boot_cpu_id = -1U;
62 /* Internal processor count */
63 unsigned int num_processors __initdata = 0;
64
65 unsigned disabled_cpus __initdata;
66
67 /* Bitmask of physically existing CPUs */
68 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
69
70 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
71
72
73 /*
74 * Intel MP BIOS table parsing routines:
75 */
76
77 /*
78 * Checksum an MP configuration block.
79 */
80
81 static int __init mpf_checksum(unsigned char *mp, int len)
82 {
83 int sum = 0;
84
85 while (len--)
86 sum += *mp++;
87
88 return sum & 0xFF;
89 }
90
91 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
92 {
93 int cpu;
94 cpumask_t tmp_map;
95 char *bootup_cpu = "";
96
97 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
98 disabled_cpus++;
99 return;
100 }
101 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
102 bootup_cpu = " (Bootup-CPU)";
103 boot_cpu_id = m->mpc_apicid;
104 }
105
106 printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);
107
108 if (num_processors >= NR_CPUS) {
109 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
110 " Processor ignored.\n", NR_CPUS);
111 return;
112 }
113
114 num_processors++;
115 cpus_complement(tmp_map, cpu_present_map);
116 cpu = first_cpu(tmp_map);
117
118 physid_set(m->mpc_apicid, phys_cpu_present_map);
119 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
120 /*
121 * bios_cpu_apicid is required to have processors listed
122 * in same order as logical cpu numbers. Hence the first
123 * entry is BSP, and so on.
124 */
125 cpu = 0;
126 }
127 bios_cpu_apicid[cpu] = m->mpc_apicid;
128 x86_cpu_to_apicid[cpu] = m->mpc_apicid;
129
130 cpu_set(cpu, cpu_possible_map);
131 cpu_set(cpu, cpu_present_map);
132 }
133
134 static void __init MP_bus_info (struct mpc_config_bus *m)
135 {
136 char str[7];
137
138 memcpy(str, m->mpc_bustype, 6);
139 str[6] = 0;
140 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
141
142 if (strncmp(str, "ISA", 3) == 0) {
143 set_bit(m->mpc_busid, mp_bus_not_pci);
144 } else if (strncmp(str, "PCI", 3) == 0) {
145 clear_bit(m->mpc_busid, mp_bus_not_pci);
146 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
147 mp_current_pci_id++;
148 } else {
149 printk(KERN_ERR "Unknown bustype %s\n", str);
150 }
151 }
152
153 static int bad_ioapic(unsigned long address)
154 {
155 if (nr_ioapics >= MAX_IO_APICS) {
156 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
157 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
158 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
159 }
160 if (!address) {
161 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
162 " found in table, skipping!\n");
163 return 1;
164 }
165 return 0;
166 }
167
168 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
169 {
170 if (!(m->mpc_flags & MPC_APIC_USABLE))
171 return;
172
173 printk("I/O APIC #%d at 0x%X.\n",
174 m->mpc_apicid, m->mpc_apicaddr);
175
176 if (bad_ioapic(m->mpc_apicaddr))
177 return;
178
179 mp_ioapics[nr_ioapics] = *m;
180 nr_ioapics++;
181 }
182
183 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
184 {
185 mp_irqs [mp_irq_entries] = *m;
186 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
187 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
188 m->mpc_irqtype, m->mpc_irqflag & 3,
189 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
190 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
191 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
192 panic("Max # of irq sources exceeded!!\n");
193 }
194
195 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
196 {
197 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
198 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
199 m->mpc_irqtype, m->mpc_irqflag & 3,
200 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
201 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
202 }
203
204 /*
205 * Read/parse the MPC
206 */
207
208 static int __init smp_read_mpc(struct mp_config_table *mpc)
209 {
210 char str[16];
211 int count=sizeof(*mpc);
212 unsigned char *mpt=((unsigned char *)mpc)+count;
213
214 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
215 printk("MPTABLE: bad signature [%c%c%c%c]!\n",
216 mpc->mpc_signature[0],
217 mpc->mpc_signature[1],
218 mpc->mpc_signature[2],
219 mpc->mpc_signature[3]);
220 return 0;
221 }
222 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
223 printk("MPTABLE: checksum error!\n");
224 return 0;
225 }
226 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
227 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
228 mpc->mpc_spec);
229 return 0;
230 }
231 if (!mpc->mpc_lapic) {
232 printk(KERN_ERR "MPTABLE: null local APIC address!\n");
233 return 0;
234 }
235 memcpy(str,mpc->mpc_oem,8);
236 str[8] = 0;
237 printk(KERN_INFO "MPTABLE: OEM ID: %s ",str);
238
239 memcpy(str,mpc->mpc_productid,12);
240 str[12] = 0;
241 printk("MPTABLE: Product ID: %s ",str);
242
243 printk("MPTABLE: APIC at: 0x%X\n",mpc->mpc_lapic);
244
245 /* save the local APIC address, it might be non-default */
246 if (!acpi_lapic)
247 mp_lapic_addr = mpc->mpc_lapic;
248
249 /*
250 * Now process the configuration blocks.
251 */
252 while (count < mpc->mpc_length) {
253 switch(*mpt) {
254 case MP_PROCESSOR:
255 {
256 struct mpc_config_processor *m=
257 (struct mpc_config_processor *)mpt;
258 if (!acpi_lapic)
259 MP_processor_info(m);
260 mpt += sizeof(*m);
261 count += sizeof(*m);
262 break;
263 }
264 case MP_BUS:
265 {
266 struct mpc_config_bus *m=
267 (struct mpc_config_bus *)mpt;
268 MP_bus_info(m);
269 mpt += sizeof(*m);
270 count += sizeof(*m);
271 break;
272 }
273 case MP_IOAPIC:
274 {
275 struct mpc_config_ioapic *m=
276 (struct mpc_config_ioapic *)mpt;
277 MP_ioapic_info(m);
278 mpt += sizeof(*m);
279 count += sizeof(*m);
280 break;
281 }
282 case MP_INTSRC:
283 {
284 struct mpc_config_intsrc *m=
285 (struct mpc_config_intsrc *)mpt;
286
287 MP_intsrc_info(m);
288 mpt += sizeof(*m);
289 count += sizeof(*m);
290 break;
291 }
292 case MP_LINTSRC:
293 {
294 struct mpc_config_lintsrc *m=
295 (struct mpc_config_lintsrc *)mpt;
296 MP_lintsrc_info(m);
297 mpt += sizeof(*m);
298 count += sizeof(*m);
299 break;
300 }
301 }
302 }
303 clustered_apic_check();
304 if (!num_processors)
305 printk(KERN_ERR "MPTABLE: no processors registered!\n");
306 return num_processors;
307 }
308
309 static int __init ELCR_trigger(unsigned int irq)
310 {
311 unsigned int port;
312
313 port = 0x4d0 + (irq >> 3);
314 return (inb(port) >> (irq & 7)) & 1;
315 }
316
317 static void __init construct_default_ioirq_mptable(int mpc_default_type)
318 {
319 struct mpc_config_intsrc intsrc;
320 int i;
321 int ELCR_fallback = 0;
322
323 intsrc.mpc_type = MP_INTSRC;
324 intsrc.mpc_irqflag = 0; /* conforming */
325 intsrc.mpc_srcbus = 0;
326 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
327
328 intsrc.mpc_irqtype = mp_INT;
329
330 /*
331 * If true, we have an ISA/PCI system with no IRQ entries
332 * in the MP table. To prevent the PCI interrupts from being set up
333 * incorrectly, we try to use the ELCR. The sanity check to see if
334 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
335 * never be level sensitive, so we simply see if the ELCR agrees.
336 * If it does, we assume it's valid.
337 */
338 if (mpc_default_type == 5) {
339 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
340
341 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
342 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
343 else {
344 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
345 ELCR_fallback = 1;
346 }
347 }
348
349 for (i = 0; i < 16; i++) {
350 switch (mpc_default_type) {
351 case 2:
352 if (i == 0 || i == 13)
353 continue; /* IRQ0 & IRQ13 not connected */
354 /* fall through */
355 default:
356 if (i == 2)
357 continue; /* IRQ2 is never connected */
358 }
359
360 if (ELCR_fallback) {
361 /*
362 * If the ELCR indicates a level-sensitive interrupt, we
363 * copy that information over to the MP table in the
364 * irqflag field (level sensitive, active high polarity).
365 */
366 if (ELCR_trigger(i))
367 intsrc.mpc_irqflag = 13;
368 else
369 intsrc.mpc_irqflag = 0;
370 }
371
372 intsrc.mpc_srcbusirq = i;
373 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
374 MP_intsrc_info(&intsrc);
375 }
376
377 intsrc.mpc_irqtype = mp_ExtINT;
378 intsrc.mpc_srcbusirq = 0;
379 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
380 MP_intsrc_info(&intsrc);
381 }
382
383 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
384 {
385 struct mpc_config_processor processor;
386 struct mpc_config_bus bus;
387 struct mpc_config_ioapic ioapic;
388 struct mpc_config_lintsrc lintsrc;
389 int linttypes[2] = { mp_ExtINT, mp_NMI };
390 int i;
391
392 /*
393 * local APIC has default address
394 */
395 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
396
397 /*
398 * 2 CPUs, numbered 0 & 1.
399 */
400 processor.mpc_type = MP_PROCESSOR;
401 processor.mpc_apicver = 0;
402 processor.mpc_cpuflag = CPU_ENABLED;
403 processor.mpc_cpufeature = 0;
404 processor.mpc_featureflag = 0;
405 processor.mpc_reserved[0] = 0;
406 processor.mpc_reserved[1] = 0;
407 for (i = 0; i < 2; i++) {
408 processor.mpc_apicid = i;
409 MP_processor_info(&processor);
410 }
411
412 bus.mpc_type = MP_BUS;
413 bus.mpc_busid = 0;
414 switch (mpc_default_type) {
415 default:
416 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
417 mpc_default_type);
418 /* fall through */
419 case 1:
420 case 5:
421 memcpy(bus.mpc_bustype, "ISA ", 6);
422 break;
423 }
424 MP_bus_info(&bus);
425 if (mpc_default_type > 4) {
426 bus.mpc_busid = 1;
427 memcpy(bus.mpc_bustype, "PCI ", 6);
428 MP_bus_info(&bus);
429 }
430
431 ioapic.mpc_type = MP_IOAPIC;
432 ioapic.mpc_apicid = 2;
433 ioapic.mpc_apicver = 0;
434 ioapic.mpc_flags = MPC_APIC_USABLE;
435 ioapic.mpc_apicaddr = 0xFEC00000;
436 MP_ioapic_info(&ioapic);
437
438 /*
439 * We set up most of the low 16 IO-APIC pins according to MPS rules.
440 */
441 construct_default_ioirq_mptable(mpc_default_type);
442
443 lintsrc.mpc_type = MP_LINTSRC;
444 lintsrc.mpc_irqflag = 0; /* conforming */
445 lintsrc.mpc_srcbusid = 0;
446 lintsrc.mpc_srcbusirq = 0;
447 lintsrc.mpc_destapic = MP_APIC_ALL;
448 for (i = 0; i < 2; i++) {
449 lintsrc.mpc_irqtype = linttypes[i];
450 lintsrc.mpc_destapiclint = i;
451 MP_lintsrc_info(&lintsrc);
452 }
453 }
454
455 static struct intel_mp_floating *mpf_found;
456
457 /*
458 * Scan the memory blocks for an SMP configuration block.
459 */
460 void __init get_smp_config (void)
461 {
462 struct intel_mp_floating *mpf = mpf_found;
463
464 /*
465 * ACPI supports both logical (e.g. Hyper-Threading) and physical
466 * processors, where MPS only supports physical.
467 */
468 if (acpi_lapic && acpi_ioapic) {
469 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
470 return;
471 }
472 else if (acpi_lapic)
473 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
474
475 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
476
477 /*
478 * Now see if we need to read further.
479 */
480 if (mpf->mpf_feature1 != 0) {
481
482 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
483 construct_default_ISA_mptable(mpf->mpf_feature1);
484
485 } else if (mpf->mpf_physptr) {
486
487 /*
488 * Read the physical hardware table. Anything here will
489 * override the defaults.
490 */
491 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
492 smp_found_config = 0;
493 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
494 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
495 return;
496 }
497 /*
498 * If there are no explicit MP IRQ entries, then we are
499 * broken. We set up most of the low 16 IO-APIC pins to
500 * ISA defaults and hope it will work.
501 */
502 if (!mp_irq_entries) {
503 struct mpc_config_bus bus;
504
505 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
506
507 bus.mpc_type = MP_BUS;
508 bus.mpc_busid = 0;
509 memcpy(bus.mpc_bustype, "ISA ", 6);
510 MP_bus_info(&bus);
511
512 construct_default_ioirq_mptable(0);
513 }
514
515 } else
516 BUG();
517
518 printk(KERN_INFO "Processors: %d\n", num_processors);
519 /*
520 * Only use the first configuration found.
521 */
522 }
523
524 static int __init smp_scan_config (unsigned long base, unsigned long length)
525 {
526 extern void __bad_mpf_size(void);
527 unsigned int *bp = phys_to_virt(base);
528 struct intel_mp_floating *mpf;
529
530 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
531 if (sizeof(*mpf) != 16)
532 __bad_mpf_size();
533
534 while (length > 0) {
535 mpf = (struct intel_mp_floating *)bp;
536 if ((*bp == SMP_MAGIC_IDENT) &&
537 (mpf->mpf_length == 1) &&
538 !mpf_checksum((unsigned char *)bp, 16) &&
539 ((mpf->mpf_specification == 1)
540 || (mpf->mpf_specification == 4)) ) {
541
542 smp_found_config = 1;
543 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
544 if (mpf->mpf_physptr)
545 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
546 mpf_found = mpf;
547 return 1;
548 }
549 bp += 4;
550 length -= 16;
551 }
552 return 0;
553 }
554
555 void __init find_smp_config(void)
556 {
557 unsigned int address;
558
559 /*
560 * FIXME: Linux assumes you have 640K of base ram..
561 * this continues the error...
562 *
563 * 1) Scan the bottom 1K for a signature
564 * 2) Scan the top 1K of base RAM
565 * 3) Scan the 64K of bios
566 */
567 if (smp_scan_config(0x0,0x400) ||
568 smp_scan_config(639*0x400,0x400) ||
569 smp_scan_config(0xF0000,0x10000))
570 return;
571 /*
572 * If it is an SMP machine we should know now.
573 *
574 * there is a real-mode segmented pointer pointing to the
575 * 4K EBDA area at 0x40E, calculate and scan it here.
576 *
577 * NOTE! There are Linux loaders that will corrupt the EBDA
578 * area, and as such this kind of SMP config may be less
579 * trustworthy, simply because the SMP table may have been
580 * stomped on during early boot. These loaders are buggy and
581 * should be fixed.
582 */
583
584 address = *(unsigned short *)phys_to_virt(0x40E);
585 address <<= 4;
586 if (smp_scan_config(address, 0x1000))
587 return;
588
589 /* If we have come this far, we did not find an MP table */
590 printk(KERN_INFO "No mptable found.\n");
591 }
592
593 /* --------------------------------------------------------------------------
594 ACPI-based MP Configuration
595 -------------------------------------------------------------------------- */
596
597 #ifdef CONFIG_ACPI
598
599 void __init mp_register_lapic_address(u64 address)
600 {
601 mp_lapic_addr = (unsigned long) address;
602 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
603 if (boot_cpu_id == -1U)
604 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
605 }
606
607 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
608 {
609 struct mpc_config_processor processor;
610 int boot_cpu = 0;
611
612 if (id == boot_cpu_id)
613 boot_cpu = 1;
614
615 processor.mpc_type = MP_PROCESSOR;
616 processor.mpc_apicid = id;
617 processor.mpc_apicver = 0;
618 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
619 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
620 processor.mpc_cpufeature = 0;
621 processor.mpc_featureflag = 0;
622 processor.mpc_reserved[0] = 0;
623 processor.mpc_reserved[1] = 0;
624
625 MP_processor_info(&processor);
626 }
627
628 #define MP_ISA_BUS 0
629 #define MP_MAX_IOAPIC_PIN 127
630
631 static struct mp_ioapic_routing {
632 int apic_id;
633 int gsi_start;
634 int gsi_end;
635 u32 pin_programmed[4];
636 } mp_ioapic_routing[MAX_IO_APICS];
637
638 static int mp_find_ioapic(int gsi)
639 {
640 int i = 0;
641
642 /* Find the IOAPIC that manages this GSI. */
643 for (i = 0; i < nr_ioapics; i++) {
644 if ((gsi >= mp_ioapic_routing[i].gsi_start)
645 && (gsi <= mp_ioapic_routing[i].gsi_end))
646 return i;
647 }
648
649 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
650 return -1;
651 }
652
653 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
654 {
655 int idx = 0;
656
657 if (bad_ioapic(address))
658 return;
659
660 idx = nr_ioapics++;
661
662 mp_ioapics[idx].mpc_type = MP_IOAPIC;
663 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
664 mp_ioapics[idx].mpc_apicaddr = address;
665
666 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
667 mp_ioapics[idx].mpc_apicid = id;
668 mp_ioapics[idx].mpc_apicver = 0;
669
670 /*
671 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
672 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
673 */
674 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
675 mp_ioapic_routing[idx].gsi_start = gsi_base;
676 mp_ioapic_routing[idx].gsi_end = gsi_base +
677 io_apic_get_redir_entries(idx);
678
679 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, "
680 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
681 mp_ioapics[idx].mpc_apicaddr,
682 mp_ioapic_routing[idx].gsi_start,
683 mp_ioapic_routing[idx].gsi_end);
684 }
685
686 void __init
687 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
688 {
689 struct mpc_config_intsrc intsrc;
690 int ioapic = -1;
691 int pin = -1;
692
693 /*
694 * Convert 'gsi' to 'ioapic.pin'.
695 */
696 ioapic = mp_find_ioapic(gsi);
697 if (ioapic < 0)
698 return;
699 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
700
701 /*
702 * TBD: This check is for faulty timer entries, where the override
703 * erroneously sets the trigger to level, resulting in a HUGE
704 * increase of timer interrupts!
705 */
706 if ((bus_irq == 0) && (trigger == 3))
707 trigger = 1;
708
709 intsrc.mpc_type = MP_INTSRC;
710 intsrc.mpc_irqtype = mp_INT;
711 intsrc.mpc_irqflag = (trigger << 2) | polarity;
712 intsrc.mpc_srcbus = MP_ISA_BUS;
713 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
714 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
715 intsrc.mpc_dstirq = pin; /* INTIN# */
716
717 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
718 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
719 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
720 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
721
722 mp_irqs[mp_irq_entries] = intsrc;
723 if (++mp_irq_entries == MAX_IRQ_SOURCES)
724 panic("Max # of irq sources exceeded!\n");
725 }
726
727 void __init mp_config_acpi_legacy_irqs(void)
728 {
729 struct mpc_config_intsrc intsrc;
730 int i = 0;
731 int ioapic = -1;
732
733 /*
734 * Fabricate the legacy ISA bus (bus #31).
735 */
736 set_bit(MP_ISA_BUS, mp_bus_not_pci);
737
738 /*
739 * Locate the IOAPIC that manages the ISA IRQs (0-15).
740 */
741 ioapic = mp_find_ioapic(0);
742 if (ioapic < 0)
743 return;
744
745 intsrc.mpc_type = MP_INTSRC;
746 intsrc.mpc_irqflag = 0; /* Conforming */
747 intsrc.mpc_srcbus = MP_ISA_BUS;
748 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
749
750 /*
751 * Use the default configuration for the IRQs 0-15. Unless
752 * overridden by (MADT) interrupt source override entries.
753 */
754 for (i = 0; i < 16; i++) {
755 int idx;
756
757 for (idx = 0; idx < mp_irq_entries; idx++) {
758 struct mpc_config_intsrc *irq = mp_irqs + idx;
759
760 /* Do we already have a mapping for this ISA IRQ? */
761 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
762 break;
763
764 /* Do we already have a mapping for this IOAPIC pin */
765 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
766 (irq->mpc_dstirq == i))
767 break;
768 }
769
770 if (idx != mp_irq_entries) {
771 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
772 continue; /* IRQ already used */
773 }
774
775 intsrc.mpc_irqtype = mp_INT;
776 intsrc.mpc_srcbusirq = i; /* Identity mapped */
777 intsrc.mpc_dstirq = i;
778
779 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
780 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
781 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
782 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
783 intsrc.mpc_dstirq);
784
785 mp_irqs[mp_irq_entries] = intsrc;
786 if (++mp_irq_entries == MAX_IRQ_SOURCES)
787 panic("Max # of irq sources exceeded!\n");
788 }
789 }
790
791 int mp_register_gsi(u32 gsi, int triggering, int polarity)
792 {
793 int ioapic = -1;
794 int ioapic_pin = 0;
795 int idx, bit = 0;
796
797 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
798 return gsi;
799
800 /* Don't set up the ACPI SCI because it's already set up */
801 if (acpi_fadt.sci_int == gsi)
802 return gsi;
803
804 ioapic = mp_find_ioapic(gsi);
805 if (ioapic < 0) {
806 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
807 return gsi;
808 }
809
810 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
811
812 /*
813 * Avoid pin reprogramming. PRTs typically include entries
814 * with redundant pin->gsi mappings (but unique PCI devices);
815 * we only program the IOAPIC on the first.
816 */
817 bit = ioapic_pin % 32;
818 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
819 if (idx > 3) {
820 printk(KERN_ERR "Invalid reference to IOAPIC pin "
821 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
822 ioapic_pin);
823 return gsi;
824 }
825 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
826 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
827 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
828 return gsi;
829 }
830
831 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
832
833 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
834 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
835 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
836 return gsi;
837 }
838 #endif /*CONFIG_ACPI*/
Linux with added FPC-III support