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Linux 2.6.20.9
[linux/fpc-iii.git] / drivers / ata / ahci.c
blob21fb66fee4949195ebc9fccad2b2d2e8d0f53d0c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "2.0"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_PORTS = 32,
57 AHCI_MAX_SG = 168, /* hardware max is 64K */
58 AHCI_DMA_BOUNDARY = 0xffffffff,
59 AHCI_USE_CLUSTERING = 0,
60 AHCI_MAX_CMDS = 32,
61 AHCI_CMD_SZ = 32,
62 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
63 AHCI_RX_FIS_SZ = 256,
64 AHCI_CMD_TBL_CDB = 0x40,
65 AHCI_CMD_TBL_HDR_SZ = 0x80,
66 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
67 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
68 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
69 AHCI_RX_FIS_SZ,
70 AHCI_IRQ_ON_SG = (1 << 31),
71 AHCI_CMD_ATAPI = (1 << 5),
72 AHCI_CMD_WRITE = (1 << 6),
73 AHCI_CMD_PREFETCH = (1 << 7),
74 AHCI_CMD_RESET = (1 << 8),
75 AHCI_CMD_CLR_BUSY = (1 << 10),
76
77 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
78 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
79 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
80
81 board_ahci = 0,
82 board_ahci_pi = 1,
83 board_ahci_vt8251 = 2,
84 board_ahci_ign_iferr = 3,
85 board_ahci_sb600 = 4,
86
87 /* global controller registers */
88 HOST_CAP = 0x00, /* host capabilities */
89 HOST_CTL = 0x04, /* global host control */
90 HOST_IRQ_STAT = 0x08, /* interrupt status */
91 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
92 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
93
94 /* HOST_CTL bits */
95 HOST_RESET = (1 << 0), /* reset controller; self-clear */
96 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
97 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
98
99 /* HOST_CAP bits */
100 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
101 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
102 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
103 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
104 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
105
106 /* registers for each SATA port */
107 PORT_LST_ADDR = 0x00, /* command list DMA addr */
108 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
109 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
110 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
111 PORT_IRQ_STAT = 0x10, /* interrupt status */
112 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
113 PORT_CMD = 0x18, /* port command */
114 PORT_TFDATA = 0x20, /* taskfile data */
115 PORT_SIG = 0x24, /* device TF signature */
116 PORT_CMD_ISSUE = 0x38, /* command issue */
117 PORT_SCR = 0x28, /* SATA phy register block */
118 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
119 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
120 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
121 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
122
123 /* PORT_IRQ_{STAT,MASK} bits */
124 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
125 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
126 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
127 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
128 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
129 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
130 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
131 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
132
133 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
134 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
135 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
136 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
137 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
138 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
139 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
140 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
141 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
142
143 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
144 PORT_IRQ_IF_ERR |
145 PORT_IRQ_CONNECT |
146 PORT_IRQ_PHYRDY |
147 PORT_IRQ_UNK_FIS,
148 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
149 PORT_IRQ_TF_ERR |
150 PORT_IRQ_HBUS_DATA_ERR,
151 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
152 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
153 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
154
155 /* PORT_CMD bits */
156 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
157 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
158 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
159 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
160 PORT_CMD_CLO = (1 << 3), /* Command list override */
161 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
162 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
163 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
164
165 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
166 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
167 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
168 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
169
170 /* hpriv->flags bits */
171 AHCI_FLAG_MSI = (1 << 0),
172
173 /* ap->flags bits */
174 AHCI_FLAG_NO_NCQ = (1 << 24),
175 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
176 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
177 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
178 };
179
180 struct ahci_cmd_hdr {
181 u32 opts;
182 u32 status;
183 u32 tbl_addr;
184 u32 tbl_addr_hi;
185 u32 reserved[4];
186 };
187
188 struct ahci_sg {
189 u32 addr;
190 u32 addr_hi;
191 u32 reserved;
192 u32 flags_size;
193 };
194
195 struct ahci_host_priv {
196 unsigned long flags;
197 u32 cap; /* cache of HOST_CAP register */
198 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
199 };
200
201 struct ahci_port_priv {
202 struct ahci_cmd_hdr *cmd_slot;
203 dma_addr_t cmd_slot_dma;
204 void *cmd_tbl;
205 dma_addr_t cmd_tbl_dma;
206 void *rx_fis;
207 dma_addr_t rx_fis_dma;
208 /* for NCQ spurious interrupt analysis */
209 int ncq_saw_spurious_sdb_cnt;
210 unsigned int ncq_saw_d2h:1;
211 unsigned int ncq_saw_dmas:1;
212 };
213
214 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
215 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
216 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
217 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
218 static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
219 static void ahci_irq_clear(struct ata_port *ap);
220 static int ahci_port_start(struct ata_port *ap);
221 static void ahci_port_stop(struct ata_port *ap);
222 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
223 static void ahci_qc_prep(struct ata_queued_cmd *qc);
224 static u8 ahci_check_status(struct ata_port *ap);
225 static void ahci_freeze(struct ata_port *ap);
226 static void ahci_thaw(struct ata_port *ap);
227 static void ahci_error_handler(struct ata_port *ap);
228 static void ahci_vt8251_error_handler(struct ata_port *ap);
229 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
230 #ifdef CONFIG_PM
231 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
232 static int ahci_port_resume(struct ata_port *ap);
233 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
234 static int ahci_pci_device_resume(struct pci_dev *pdev);
235 #endif
236 static void ahci_remove_one (struct pci_dev *pdev);
237
238 static struct scsi_host_template ahci_sht = {
239 .module = THIS_MODULE,
240 .name = DRV_NAME,
241 .ioctl = ata_scsi_ioctl,
242 .queuecommand = ata_scsi_queuecmd,
243 .change_queue_depth = ata_scsi_change_queue_depth,
244 .can_queue = AHCI_MAX_CMDS - 1,
245 .this_id = ATA_SHT_THIS_ID,
246 .sg_tablesize = AHCI_MAX_SG,
247 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
248 .emulated = ATA_SHT_EMULATED,
249 .use_clustering = AHCI_USE_CLUSTERING,
250 .proc_name = DRV_NAME,
251 .dma_boundary = AHCI_DMA_BOUNDARY,
252 .slave_configure = ata_scsi_slave_config,
253 .slave_destroy = ata_scsi_slave_destroy,
254 .bios_param = ata_std_bios_param,
255 #ifdef CONFIG_PM
256 .suspend = ata_scsi_device_suspend,
257 .resume = ata_scsi_device_resume,
258 #endif
259 };
260
261 static const struct ata_port_operations ahci_ops = {
262 .port_disable = ata_port_disable,
263
264 .check_status = ahci_check_status,
265 .check_altstatus = ahci_check_status,
266 .dev_select = ata_noop_dev_select,
267
268 .tf_read = ahci_tf_read,
269
270 .qc_prep = ahci_qc_prep,
271 .qc_issue = ahci_qc_issue,
272
273 .irq_handler = ahci_interrupt,
274 .irq_clear = ahci_irq_clear,
275
276 .scr_read = ahci_scr_read,
277 .scr_write = ahci_scr_write,
278
279 .freeze = ahci_freeze,
280 .thaw = ahci_thaw,
281
282 .error_handler = ahci_error_handler,
283 .post_internal_cmd = ahci_post_internal_cmd,
284
285 #ifdef CONFIG_PM
286 .port_suspend = ahci_port_suspend,
287 .port_resume = ahci_port_resume,
288 #endif
289
290 .port_start = ahci_port_start,
291 .port_stop = ahci_port_stop,
292 };
293
294 static const struct ata_port_operations ahci_vt8251_ops = {
295 .port_disable = ata_port_disable,
296
297 .check_status = ahci_check_status,
298 .check_altstatus = ahci_check_status,
299 .dev_select = ata_noop_dev_select,
300
301 .tf_read = ahci_tf_read,
302
303 .qc_prep = ahci_qc_prep,
304 .qc_issue = ahci_qc_issue,
305
306 .irq_handler = ahci_interrupt,
307 .irq_clear = ahci_irq_clear,
308
309 .scr_read = ahci_scr_read,
310 .scr_write = ahci_scr_write,
311
312 .freeze = ahci_freeze,
313 .thaw = ahci_thaw,
314
315 .error_handler = ahci_vt8251_error_handler,
316 .post_internal_cmd = ahci_post_internal_cmd,
317
318 #ifdef CONFIG_PM
319 .port_suspend = ahci_port_suspend,
320 .port_resume = ahci_port_resume,
321 #endif
322
323 .port_start = ahci_port_start,
324 .port_stop = ahci_port_stop,
325 };
326
327 static const struct ata_port_info ahci_port_info[] = {
328 /* board_ahci */
329 {
330 .sht = &ahci_sht,
331 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
332 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
333 ATA_FLAG_SKIP_D2H_BSY,
334 .pio_mask = 0x1f, /* pio0-4 */
335 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
336 .port_ops = &ahci_ops,
337 },
338 /* board_ahci_pi */
339 {
340 .sht = &ahci_sht,
341 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
342 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
343 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
344 .pio_mask = 0x1f, /* pio0-4 */
345 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
346 .port_ops = &ahci_ops,
347 },
348 /* board_ahci_vt8251 */
349 {
350 .sht = &ahci_sht,
351 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
352 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
353 ATA_FLAG_SKIP_D2H_BSY |
354 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
355 .pio_mask = 0x1f, /* pio0-4 */
356 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
357 .port_ops = &ahci_vt8251_ops,
358 },
359 /* board_ahci_ign_iferr */
360 {
361 .sht = &ahci_sht,
362 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
363 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
364 ATA_FLAG_SKIP_D2H_BSY |
365 AHCI_FLAG_IGN_IRQ_IF_ERR,
366 .pio_mask = 0x1f, /* pio0-4 */
367 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
368 .port_ops = &ahci_ops,
369 },
370 /* board_ahci_sb600 */
371 {
372 .sht = &ahci_sht,
373 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
374 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
375 ATA_FLAG_SKIP_D2H_BSY |
376 AHCI_FLAG_IGN_SERR_INTERNAL,
377 .pio_mask = 0x1f, /* pio0-4 */
378 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
379 .port_ops = &ahci_ops,
380 },
381
382 };
383
384 static const struct pci_device_id ahci_pci_tbl[] = {
385 /* Intel */
386 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
387 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
388 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
389 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
390 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
391 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
392 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
393 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
394 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
395 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
396 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
397 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
398 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
399 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
400 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
401 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
402 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
403 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
404 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
405 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
406 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
407 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
408 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
409 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
410 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
411 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
412
413 /* JMicron */
414 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */
415 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */
416 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */
417 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */
418 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */
419
420 /* ATI */
421 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 non-raid */
422 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
423
424 /* VIA */
425 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
426
427 /* NVIDIA */
428 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
431 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
432 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
433 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
434 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
435 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
436 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
445 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
446 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
447 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
448
449 /* SiS */
450 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
451 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
452 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
453
454 /* Generic, PCI class code for AHCI */
455 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
456 0x010601, 0xffffff, board_ahci },
457
458 { } /* terminate list */
459 };
460
461
462 static struct pci_driver ahci_pci_driver = {
463 .name = DRV_NAME,
464 .id_table = ahci_pci_tbl,
465 .probe = ahci_init_one,
466 #ifdef CONFIG_PM
467 .suspend = ahci_pci_device_suspend,
468 .resume = ahci_pci_device_resume,
469 #endif
470 .remove = ahci_remove_one,
471 };
472
473
474 static inline int ahci_nr_ports(u32 cap)
475 {
476 return (cap & 0x1f) + 1;
477 }
478
479 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
480 {
481 return base + 0x100 + (port * 0x80);
482 }
483
484 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
485 {
486 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
487 }
488
489 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
490 {
491 unsigned int sc_reg;
492
493 switch (sc_reg_in) {
494 case SCR_STATUS: sc_reg = 0; break;
495 case SCR_CONTROL: sc_reg = 1; break;
496 case SCR_ERROR: sc_reg = 2; break;
497 case SCR_ACTIVE: sc_reg = 3; break;
498 default:
499 return 0xffffffffU;
500 }
501
502 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
503 }
504
505
506 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
507 u32 val)
508 {
509 unsigned int sc_reg;
510
511 switch (sc_reg_in) {
512 case SCR_STATUS: sc_reg = 0; break;
513 case SCR_CONTROL: sc_reg = 1; break;
514 case SCR_ERROR: sc_reg = 2; break;
515 case SCR_ACTIVE: sc_reg = 3; break;
516 default:
517 return;
518 }
519
520 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
521 }
522
523 static void ahci_start_engine(void __iomem *port_mmio)
524 {
525 u32 tmp;
526
527 /* start DMA */
528 tmp = readl(port_mmio + PORT_CMD);
529 tmp |= PORT_CMD_START;
530 writel(tmp, port_mmio + PORT_CMD);
531 readl(port_mmio + PORT_CMD); /* flush */
532 }
533
534 static int ahci_stop_engine(void __iomem *port_mmio)
535 {
536 u32 tmp;
537
538 tmp = readl(port_mmio + PORT_CMD);
539
540 /* check if the HBA is idle */
541 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
542 return 0;
543
544 /* setting HBA to idle */
545 tmp &= ~PORT_CMD_START;
546 writel(tmp, port_mmio + PORT_CMD);
547
548 /* wait for engine to stop. This could be as long as 500 msec */
549 tmp = ata_wait_register(port_mmio + PORT_CMD,
550 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
551 if (tmp & PORT_CMD_LIST_ON)
552 return -EIO;
553
554 return 0;
555 }
556
557 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
558 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
559 {
560 u32 tmp;
561
562 /* set FIS registers */
563 if (cap & HOST_CAP_64)
564 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
565 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
566
567 if (cap & HOST_CAP_64)
568 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
569 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
570
571 /* enable FIS reception */
572 tmp = readl(port_mmio + PORT_CMD);
573 tmp |= PORT_CMD_FIS_RX;
574 writel(tmp, port_mmio + PORT_CMD);
575
576 /* flush */
577 readl(port_mmio + PORT_CMD);
578 }
579
580 static int ahci_stop_fis_rx(void __iomem *port_mmio)
581 {
582 u32 tmp;
583
584 /* disable FIS reception */
585 tmp = readl(port_mmio + PORT_CMD);
586 tmp &= ~PORT_CMD_FIS_RX;
587 writel(tmp, port_mmio + PORT_CMD);
588
589 /* wait for completion, spec says 500ms, give it 1000 */
590 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
591 PORT_CMD_FIS_ON, 10, 1000);
592 if (tmp & PORT_CMD_FIS_ON)
593 return -EBUSY;
594
595 return 0;
596 }
597
598 static void ahci_power_up(void __iomem *port_mmio, u32 cap)
599 {
600 u32 cmd;
601
602 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
603
604 /* spin up device */
605 if (cap & HOST_CAP_SSS) {
606 cmd |= PORT_CMD_SPIN_UP;
607 writel(cmd, port_mmio + PORT_CMD);
608 }
609
610 /* wake up link */
611 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
612 }
613
614 #ifdef CONFIG_PM
615 static void ahci_power_down(void __iomem *port_mmio, u32 cap)
616 {
617 u32 cmd, scontrol;
618
619 if (!(cap & HOST_CAP_SSS))
620 return;
621
622 /* put device into listen mode, first set PxSCTL.DET to 0 */
623 scontrol = readl(port_mmio + PORT_SCR_CTL);
624 scontrol &= ~0xf;
625 writel(scontrol, port_mmio + PORT_SCR_CTL);
626
627 /* then set PxCMD.SUD to 0 */
628 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
629 cmd &= ~PORT_CMD_SPIN_UP;
630 writel(cmd, port_mmio + PORT_CMD);
631 }
632 #endif
633
634 static void ahci_init_port(void __iomem *port_mmio, u32 cap,
635 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
636 {
637 /* enable FIS reception */
638 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
639
640 /* enable DMA */
641 ahci_start_engine(port_mmio);
642 }
643
644 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
645 {
646 int rc;
647
648 /* disable DMA */
649 rc = ahci_stop_engine(port_mmio);
650 if (rc) {
651 *emsg = "failed to stop engine";
652 return rc;
653 }
654
655 /* disable FIS reception */
656 rc = ahci_stop_fis_rx(port_mmio);
657 if (rc) {
658 *emsg = "failed stop FIS RX";
659 return rc;
660 }
661
662 return 0;
663 }
664
665 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
666 {
667 u32 cap_save, impl_save, tmp;
668
669 cap_save = readl(mmio + HOST_CAP);
670 impl_save = readl(mmio + HOST_PORTS_IMPL);
671
672 /* global controller reset */
673 tmp = readl(mmio + HOST_CTL);
674 if ((tmp & HOST_RESET) == 0) {
675 writel(tmp | HOST_RESET, mmio + HOST_CTL);
676 readl(mmio + HOST_CTL); /* flush */
677 }
678
679 /* reset must complete within 1 second, or
680 * the hardware should be considered fried.
681 */
682 ssleep(1);
683
684 tmp = readl(mmio + HOST_CTL);
685 if (tmp & HOST_RESET) {
686 dev_printk(KERN_ERR, &pdev->dev,
687 "controller reset failed (0x%x)\n", tmp);
688 return -EIO;
689 }
690
691 /* turn on AHCI mode */
692 writel(HOST_AHCI_EN, mmio + HOST_CTL);
693 (void) readl(mmio + HOST_CTL); /* flush */
694
695 /* These write-once registers are normally cleared on reset.
696 * Restore BIOS values... which we HOPE were present before
697 * reset.
698 */
699 if (!impl_save) {
700 impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
701 dev_printk(KERN_WARNING, &pdev->dev,
702 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
703 }
704 writel(cap_save, mmio + HOST_CAP);
705 writel(impl_save, mmio + HOST_PORTS_IMPL);
706 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
707
708 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
709 u16 tmp16;
710
711 /* configure PCS */
712 pci_read_config_word(pdev, 0x92, &tmp16);
713 tmp16 |= 0xf;
714 pci_write_config_word(pdev, 0x92, tmp16);
715 }
716
717 return 0;
718 }
719
720 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
721 int n_ports, unsigned int port_flags,
722 struct ahci_host_priv *hpriv)
723 {
724 int i, rc;
725 u32 tmp;
726
727 for (i = 0; i < n_ports; i++) {
728 void __iomem *port_mmio = ahci_port_base(mmio, i);
729 const char *emsg = NULL;
730
731 if ((port_flags & AHCI_FLAG_HONOR_PI) &&
732 !(hpriv->port_map & (1 << i)))
733 continue;
734
735 /* make sure port is not active */
736 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
737 if (rc)
738 dev_printk(KERN_WARNING, &pdev->dev,
739 "%s (%d)\n", emsg, rc);
740
741 /* clear SError */
742 tmp = readl(port_mmio + PORT_SCR_ERR);
743 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
744 writel(tmp, port_mmio + PORT_SCR_ERR);
745
746 /* clear port IRQ */
747 tmp = readl(port_mmio + PORT_IRQ_STAT);
748 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
749 if (tmp)
750 writel(tmp, port_mmio + PORT_IRQ_STAT);
751
752 writel(1 << i, mmio + HOST_IRQ_STAT);
753 }
754
755 tmp = readl(mmio + HOST_CTL);
756 VPRINTK("HOST_CTL 0x%x\n", tmp);
757 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
758 tmp = readl(mmio + HOST_CTL);
759 VPRINTK("HOST_CTL 0x%x\n", tmp);
760 }
761
762 static unsigned int ahci_dev_classify(struct ata_port *ap)
763 {
764 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
765 struct ata_taskfile tf;
766 u32 tmp;
767
768 tmp = readl(port_mmio + PORT_SIG);
769 tf.lbah = (tmp >> 24) & 0xff;
770 tf.lbam = (tmp >> 16) & 0xff;
771 tf.lbal = (tmp >> 8) & 0xff;
772 tf.nsect = (tmp) & 0xff;
773
774 return ata_dev_classify(&tf);
775 }
776
777 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
778 u32 opts)
779 {
780 dma_addr_t cmd_tbl_dma;
781
782 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
783
784 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
785 pp->cmd_slot[tag].status = 0;
786 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
787 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
788 }
789
790 static int ahci_clo(struct ata_port *ap)
791 {
792 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
793 struct ahci_host_priv *hpriv = ap->host->private_data;
794 u32 tmp;
795
796 if (!(hpriv->cap & HOST_CAP_CLO))
797 return -EOPNOTSUPP;
798
799 tmp = readl(port_mmio + PORT_CMD);
800 tmp |= PORT_CMD_CLO;
801 writel(tmp, port_mmio + PORT_CMD);
802
803 tmp = ata_wait_register(port_mmio + PORT_CMD,
804 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
805 if (tmp & PORT_CMD_CLO)
806 return -EIO;
807
808 return 0;
809 }
810
811 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
812 {
813 struct ahci_port_priv *pp = ap->private_data;
814 void __iomem *mmio = ap->host->mmio_base;
815 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
816 const u32 cmd_fis_len = 5; /* five dwords */
817 const char *reason = NULL;
818 struct ata_taskfile tf;
819 u32 tmp;
820 u8 *fis;
821 int rc;
822
823 DPRINTK("ENTER\n");
824
825 if (ata_port_offline(ap)) {
826 DPRINTK("PHY reports no device\n");
827 *class = ATA_DEV_NONE;
828 return 0;
829 }
830
831 /* prepare for SRST (AHCI-1.1 10.4.1) */
832 rc = ahci_stop_engine(port_mmio);
833 if (rc) {
834 reason = "failed to stop engine";
835 goto fail_restart;
836 }
837
838 /* check BUSY/DRQ, perform Command List Override if necessary */
839 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
840 rc = ahci_clo(ap);
841
842 if (rc == -EOPNOTSUPP) {
843 reason = "port busy but CLO unavailable";
844 goto fail_restart;
845 } else if (rc) {
846 reason = "port busy but CLO failed";
847 goto fail_restart;
848 }
849 }
850
851 /* restart engine */
852 ahci_start_engine(port_mmio);
853
854 ata_tf_init(ap->device, &tf);
855 fis = pp->cmd_tbl;
856
857 /* issue the first D2H Register FIS */
858 ahci_fill_cmd_slot(pp, 0,
859 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
860
861 tf.ctl |= ATA_SRST;
862 ata_tf_to_fis(&tf, fis, 0);
863 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
864
865 writel(1, port_mmio + PORT_CMD_ISSUE);
866
867 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
868 if (tmp & 0x1) {
869 rc = -EIO;
870 reason = "1st FIS failed";
871 goto fail;
872 }
873
874 /* spec says at least 5us, but be generous and sleep for 1ms */
875 msleep(1);
876
877 /* issue the second D2H Register FIS */
878 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
879
880 tf.ctl &= ~ATA_SRST;
881 ata_tf_to_fis(&tf, fis, 0);
882 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
883
884 writel(1, port_mmio + PORT_CMD_ISSUE);
885 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
886
887 /* spec mandates ">= 2ms" before checking status.
888 * We wait 150ms, because that was the magic delay used for
889 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
890 * between when the ATA command register is written, and then
891 * status is checked. Because waiting for "a while" before
892 * checking status is fine, post SRST, we perform this magic
893 * delay here as well.
894 */
895 msleep(150);
896
897 *class = ATA_DEV_NONE;
898 if (ata_port_online(ap)) {
899 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
900 rc = -EIO;
901 reason = "device not ready";
902 goto fail;
903 }
904 *class = ahci_dev_classify(ap);
905 }
906
907 DPRINTK("EXIT, class=%u\n", *class);
908 return 0;
909
910 fail_restart:
911 ahci_start_engine(port_mmio);
912 fail:
913 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
914 return rc;
915 }
916
917 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
918 {
919 struct ahci_port_priv *pp = ap->private_data;
920 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
921 struct ata_taskfile tf;
922 void __iomem *mmio = ap->host->mmio_base;
923 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
924 int rc;
925
926 DPRINTK("ENTER\n");
927
928 ahci_stop_engine(port_mmio);
929
930 /* clear D2H reception area to properly wait for D2H FIS */
931 ata_tf_init(ap->device, &tf);
932 tf.command = 0x80;
933 ata_tf_to_fis(&tf, d2h_fis, 0);
934
935 rc = sata_std_hardreset(ap, class);
936
937 ahci_start_engine(port_mmio);
938
939 if (rc == 0 && ata_port_online(ap))
940 *class = ahci_dev_classify(ap);
941 if (*class == ATA_DEV_UNKNOWN)
942 *class = ATA_DEV_NONE;
943
944 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
945 return rc;
946 }
947
948 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
949 {
950 void __iomem *mmio = ap->host->mmio_base;
951 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
952 int rc;
953
954 DPRINTK("ENTER\n");
955
956 ahci_stop_engine(port_mmio);
957
958 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
959
960 /* vt8251 needs SError cleared for the port to operate */
961 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
962
963 ahci_start_engine(port_mmio);
964
965 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
966
967 /* vt8251 doesn't clear BSY on signature FIS reception,
968 * request follow-up softreset.
969 */
970 return rc ?: -EAGAIN;
971 }
972
973 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
974 {
975 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
976 u32 new_tmp, tmp;
977
978 ata_std_postreset(ap, class);
979
980 /* Make sure port's ATAPI bit is set appropriately */
981 new_tmp = tmp = readl(port_mmio + PORT_CMD);
982 if (*class == ATA_DEV_ATAPI)
983 new_tmp |= PORT_CMD_ATAPI;
984 else
985 new_tmp &= ~PORT_CMD_ATAPI;
986 if (new_tmp != tmp) {
987 writel(new_tmp, port_mmio + PORT_CMD);
988 readl(port_mmio + PORT_CMD); /* flush */
989 }
990 }
991
992 static u8 ahci_check_status(struct ata_port *ap)
993 {
994 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
995
996 return readl(mmio + PORT_TFDATA) & 0xFF;
997 }
998
999 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1000 {
1001 struct ahci_port_priv *pp = ap->private_data;
1002 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1003
1004 ata_tf_from_fis(d2h_fis, tf);
1005 }
1006
1007 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1008 {
1009 struct scatterlist *sg;
1010 struct ahci_sg *ahci_sg;
1011 unsigned int n_sg = 0;
1012
1013 VPRINTK("ENTER\n");
1014
1015 /*
1016 * Next, the S/G list.
1017 */
1018 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1019 ata_for_each_sg(sg, qc) {
1020 dma_addr_t addr = sg_dma_address(sg);
1021 u32 sg_len = sg_dma_len(sg);
1022
1023 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1024 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1025 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1026
1027 ahci_sg++;
1028 n_sg++;
1029 }
1030
1031 return n_sg;
1032 }
1033
1034 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1035 {
1036 struct ata_port *ap = qc->ap;
1037 struct ahci_port_priv *pp = ap->private_data;
1038 int is_atapi = is_atapi_taskfile(&qc->tf);
1039 void *cmd_tbl;
1040 u32 opts;
1041 const u32 cmd_fis_len = 5; /* five dwords */
1042 unsigned int n_elem;
1043
1044 /*
1045 * Fill in command table information. First, the header,
1046 * a SATA Register - Host to Device command FIS.
1047 */
1048 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1049
1050 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
1051 if (is_atapi) {
1052 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1053 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1054 }
1055
1056 n_elem = 0;
1057 if (qc->flags & ATA_QCFLAG_DMAMAP)
1058 n_elem = ahci_fill_sg(qc, cmd_tbl);
1059
1060 /*
1061 * Fill in command slot information.
1062 */
1063 opts = cmd_fis_len | n_elem << 16;
1064 if (qc->tf.flags & ATA_TFLAG_WRITE)
1065 opts |= AHCI_CMD_WRITE;
1066 if (is_atapi)
1067 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1068
1069 ahci_fill_cmd_slot(pp, qc->tag, opts);
1070 }
1071
1072 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1073 {
1074 struct ahci_port_priv *pp = ap->private_data;
1075 struct ata_eh_info *ehi = &ap->eh_info;
1076 unsigned int err_mask = 0, action = 0;
1077 struct ata_queued_cmd *qc;
1078 u32 serror;
1079
1080 ata_ehi_clear_desc(ehi);
1081
1082 /* AHCI needs SError cleared; otherwise, it might lock up */
1083 serror = ahci_scr_read(ap, SCR_ERROR);
1084 ahci_scr_write(ap, SCR_ERROR, serror);
1085
1086 /* analyze @irq_stat */
1087 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1088
1089 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1090 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1091 irq_stat &= ~PORT_IRQ_IF_ERR;
1092
1093 if (irq_stat & PORT_IRQ_TF_ERR) {
1094 err_mask |= AC_ERR_DEV;
1095 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1096 serror &= ~SERR_INTERNAL;
1097 }
1098
1099 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1100 err_mask |= AC_ERR_HOST_BUS;
1101 action |= ATA_EH_SOFTRESET;
1102 }
1103
1104 if (irq_stat & PORT_IRQ_IF_ERR) {
1105 err_mask |= AC_ERR_ATA_BUS;
1106 action |= ATA_EH_SOFTRESET;
1107 ata_ehi_push_desc(ehi, ", interface fatal error");
1108 }
1109
1110 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1111 ata_ehi_hotplugged(ehi);
1112 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1113 "connection status changed" : "PHY RDY changed");
1114 }
1115
1116 if (irq_stat & PORT_IRQ_UNK_FIS) {
1117 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1118
1119 err_mask |= AC_ERR_HSM;
1120 action |= ATA_EH_SOFTRESET;
1121 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1122 unk[0], unk[1], unk[2], unk[3]);
1123 }
1124
1125 /* okay, let's hand over to EH */
1126 ehi->serror |= serror;
1127 ehi->action |= action;
1128
1129 qc = ata_qc_from_tag(ap, ap->active_tag);
1130 if (qc)
1131 qc->err_mask |= err_mask;
1132 else
1133 ehi->err_mask |= err_mask;
1134
1135 if (irq_stat & PORT_IRQ_FREEZE)
1136 ata_port_freeze(ap);
1137 else
1138 ata_port_abort(ap);
1139 }
1140
1141 static void ahci_host_intr(struct ata_port *ap)
1142 {
1143 void __iomem *mmio = ap->host->mmio_base;
1144 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1145 struct ata_eh_info *ehi = &ap->eh_info;
1146 struct ahci_port_priv *pp = ap->private_data;
1147 u32 status, qc_active;
1148 int rc, known_irq = 0;
1149
1150 status = readl(port_mmio + PORT_IRQ_STAT);
1151 writel(status, port_mmio + PORT_IRQ_STAT);
1152
1153 if (unlikely(status & PORT_IRQ_ERROR)) {
1154 ahci_error_intr(ap, status);
1155 return;
1156 }
1157
1158 if (ap->sactive)
1159 qc_active = readl(port_mmio + PORT_SCR_ACT);
1160 else
1161 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1162
1163 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1164 if (rc > 0)
1165 return;
1166 if (rc < 0) {
1167 ehi->err_mask |= AC_ERR_HSM;
1168 ehi->action |= ATA_EH_SOFTRESET;
1169 ata_port_freeze(ap);
1170 return;
1171 }
1172
1173 /* hmmm... a spurious interupt */
1174
1175 /* if !NCQ, ignore. No modern ATA device has broken HSM
1176 * implementation for non-NCQ commands.
1177 */
1178 if (!ap->sactive)
1179 return;
1180
1181 if (status & PORT_IRQ_D2H_REG_FIS) {
1182 if (!pp->ncq_saw_d2h)
1183 ata_port_printk(ap, KERN_INFO,
1184 "D2H reg with I during NCQ, "
1185 "this message won't be printed again\n");
1186 pp->ncq_saw_d2h = 1;
1187 known_irq = 1;
1188 }
1189
1190 if (status & PORT_IRQ_DMAS_FIS) {
1191 if (!pp->ncq_saw_dmas)
1192 ata_port_printk(ap, KERN_INFO,
1193 "DMAS FIS during NCQ, "
1194 "this message won't be printed again\n");
1195 pp->ncq_saw_dmas = 1;
1196 known_irq = 1;
1197 }
1198
1199 if (status & PORT_IRQ_SDB_FIS &&
1200 pp->ncq_saw_spurious_sdb_cnt < 10) {
1201 /* SDB FIS containing spurious completions might be
1202 * dangerous, we need to know more about them. Print
1203 * more of it.
1204 */
1205 const u32 *f = pp->rx_fis + RX_FIS_SDB;
1206
1207 ata_port_printk(ap, KERN_INFO, "Spurious SDB FIS during NCQ "
1208 "issue=0x%x SAct=0x%x FIS=%08x:%08x%s\n",
1209 readl(port_mmio + PORT_CMD_ISSUE),
1210 readl(port_mmio + PORT_SCR_ACT),
1211 le32_to_cpu(f[0]), le32_to_cpu(f[1]),
1212 pp->ncq_saw_spurious_sdb_cnt < 10 ?
1213 "" : ", shutting up");
1214
1215 pp->ncq_saw_spurious_sdb_cnt++;
1216 known_irq = 1;
1217 }
1218
1219 if (!known_irq)
1220 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1221 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1222 status, ap->active_tag, ap->sactive);
1223 }
1224
1225 static void ahci_irq_clear(struct ata_port *ap)
1226 {
1227 /* TODO */
1228 }
1229
1230 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1231 {
1232 struct ata_host *host = dev_instance;
1233 struct ahci_host_priv *hpriv;
1234 unsigned int i, handled = 0;
1235 void __iomem *mmio;
1236 u32 irq_stat, irq_ack = 0;
1237
1238 VPRINTK("ENTER\n");
1239
1240 hpriv = host->private_data;
1241 mmio = host->mmio_base;
1242
1243 /* sigh. 0xffffffff is a valid return from h/w */
1244 irq_stat = readl(mmio + HOST_IRQ_STAT);
1245 irq_stat &= hpriv->port_map;
1246 if (!irq_stat)
1247 return IRQ_NONE;
1248
1249 spin_lock(&host->lock);
1250
1251 for (i = 0; i < host->n_ports; i++) {
1252 struct ata_port *ap;
1253
1254 if (!(irq_stat & (1 << i)))
1255 continue;
1256
1257 ap = host->ports[i];
1258 if (ap) {
1259 ahci_host_intr(ap);
1260 VPRINTK("port %u\n", i);
1261 } else {
1262 VPRINTK("port %u (no irq)\n", i);
1263 if (ata_ratelimit())
1264 dev_printk(KERN_WARNING, host->dev,
1265 "interrupt on disabled port %u\n", i);
1266 }
1267
1268 irq_ack |= (1 << i);
1269 }
1270
1271 if (irq_ack) {
1272 writel(irq_ack, mmio + HOST_IRQ_STAT);
1273 handled = 1;
1274 }
1275
1276 spin_unlock(&host->lock);
1277
1278 VPRINTK("EXIT\n");
1279
1280 return IRQ_RETVAL(handled);
1281 }
1282
1283 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1284 {
1285 struct ata_port *ap = qc->ap;
1286 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1287
1288 if (qc->tf.protocol == ATA_PROT_NCQ)
1289 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1290 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1291 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1292
1293 return 0;
1294 }
1295
1296 static void ahci_freeze(struct ata_port *ap)
1297 {
1298 void __iomem *mmio = ap->host->mmio_base;
1299 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1300
1301 /* turn IRQ off */
1302 writel(0, port_mmio + PORT_IRQ_MASK);
1303 }
1304
1305 static void ahci_thaw(struct ata_port *ap)
1306 {
1307 void __iomem *mmio = ap->host->mmio_base;
1308 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1309 u32 tmp;
1310
1311 /* clear IRQ */
1312 tmp = readl(port_mmio + PORT_IRQ_STAT);
1313 writel(tmp, port_mmio + PORT_IRQ_STAT);
1314 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1315
1316 /* turn IRQ back on */
1317 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1318 }
1319
1320 static void ahci_error_handler(struct ata_port *ap)
1321 {
1322 void __iomem *mmio = ap->host->mmio_base;
1323 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1324
1325 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1326 /* restart engine */
1327 ahci_stop_engine(port_mmio);
1328 ahci_start_engine(port_mmio);
1329 }
1330
1331 /* perform recovery */
1332 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1333 ahci_postreset);
1334 }
1335
1336 static void ahci_vt8251_error_handler(struct ata_port *ap)
1337 {
1338 void __iomem *mmio = ap->host->mmio_base;
1339 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1340
1341 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1342 /* restart engine */
1343 ahci_stop_engine(port_mmio);
1344 ahci_start_engine(port_mmio);
1345 }
1346
1347 /* perform recovery */
1348 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1349 ahci_postreset);
1350 }
1351
1352 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1353 {
1354 struct ata_port *ap = qc->ap;
1355 void __iomem *mmio = ap->host->mmio_base;
1356 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1357
1358 if (qc->flags & ATA_QCFLAG_FAILED)
1359 qc->err_mask |= AC_ERR_OTHER;
1360
1361 if (qc->err_mask) {
1362 /* make DMA engine forget about the failed command */
1363 ahci_stop_engine(port_mmio);
1364 ahci_start_engine(port_mmio);
1365 }
1366 }
1367
1368 #ifdef CONFIG_PM
1369 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1370 {
1371 struct ahci_host_priv *hpriv = ap->host->private_data;
1372 struct ahci_port_priv *pp = ap->private_data;
1373 void __iomem *mmio = ap->host->mmio_base;
1374 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1375 const char *emsg = NULL;
1376 int rc;
1377
1378 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1379 if (rc == 0)
1380 ahci_power_down(port_mmio, hpriv->cap);
1381 else {
1382 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1383 ahci_init_port(port_mmio, hpriv->cap,
1384 pp->cmd_slot_dma, pp->rx_fis_dma);
1385 }
1386
1387 return rc;
1388 }
1389
1390 static int ahci_port_resume(struct ata_port *ap)
1391 {
1392 struct ahci_port_priv *pp = ap->private_data;
1393 struct ahci_host_priv *hpriv = ap->host->private_data;
1394 void __iomem *mmio = ap->host->mmio_base;
1395 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1396
1397 ahci_power_up(port_mmio, hpriv->cap);
1398 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1399
1400 return 0;
1401 }
1402
1403 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1404 {
1405 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1406 void __iomem *mmio = host->mmio_base;
1407 u32 ctl;
1408
1409 if (mesg.event == PM_EVENT_SUSPEND) {
1410 /* AHCI spec rev1.1 section 8.3.3:
1411 * Software must disable interrupts prior to requesting a
1412 * transition of the HBA to D3 state.
1413 */
1414 ctl = readl(mmio + HOST_CTL);
1415 ctl &= ~HOST_IRQ_EN;
1416 writel(ctl, mmio + HOST_CTL);
1417 readl(mmio + HOST_CTL); /* flush */
1418 }
1419
1420 return ata_pci_device_suspend(pdev, mesg);
1421 }
1422
1423 static int ahci_pci_device_resume(struct pci_dev *pdev)
1424 {
1425 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1426 struct ahci_host_priv *hpriv = host->private_data;
1427 void __iomem *mmio = host->mmio_base;
1428 int rc;
1429
1430 ata_pci_device_do_resume(pdev);
1431
1432 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1433 rc = ahci_reset_controller(mmio, pdev);
1434 if (rc)
1435 return rc;
1436
1437 ahci_init_controller(mmio, pdev, host->n_ports,
1438 host->ports[0]->flags, hpriv);
1439 }
1440
1441 ata_host_resume(host);
1442
1443 return 0;
1444 }
1445 #endif
1446
1447 static int ahci_port_start(struct ata_port *ap)
1448 {
1449 struct device *dev = ap->host->dev;
1450 struct ahci_host_priv *hpriv = ap->host->private_data;
1451 struct ahci_port_priv *pp;
1452 void __iomem *mmio = ap->host->mmio_base;
1453 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1454 void *mem;
1455 dma_addr_t mem_dma;
1456 int rc;
1457
1458 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1459 if (!pp)
1460 return -ENOMEM;
1461 memset(pp, 0, sizeof(*pp));
1462
1463 rc = ata_pad_alloc(ap, dev);
1464 if (rc) {
1465 kfree(pp);
1466 return rc;
1467 }
1468
1469 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1470 if (!mem) {
1471 ata_pad_free(ap, dev);
1472 kfree(pp);
1473 return -ENOMEM;
1474 }
1475 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1476
1477 /*
1478 * First item in chunk of DMA memory: 32-slot command table,
1479 * 32 bytes each in size
1480 */
1481 pp->cmd_slot = mem;
1482 pp->cmd_slot_dma = mem_dma;
1483
1484 mem += AHCI_CMD_SLOT_SZ;
1485 mem_dma += AHCI_CMD_SLOT_SZ;
1486
1487 /*
1488 * Second item: Received-FIS area
1489 */
1490 pp->rx_fis = mem;
1491 pp->rx_fis_dma = mem_dma;
1492
1493 mem += AHCI_RX_FIS_SZ;
1494 mem_dma += AHCI_RX_FIS_SZ;
1495
1496 /*
1497 * Third item: data area for storing a single command
1498 * and its scatter-gather table
1499 */
1500 pp->cmd_tbl = mem;
1501 pp->cmd_tbl_dma = mem_dma;
1502
1503 ap->private_data = pp;
1504
1505 /* power up port */
1506 ahci_power_up(port_mmio, hpriv->cap);
1507
1508 /* initialize port */
1509 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1510
1511 return 0;
1512 }
1513
1514 static void ahci_port_stop(struct ata_port *ap)
1515 {
1516 struct device *dev = ap->host->dev;
1517 struct ahci_host_priv *hpriv = ap->host->private_data;
1518 struct ahci_port_priv *pp = ap->private_data;
1519 void __iomem *mmio = ap->host->mmio_base;
1520 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1521 const char *emsg = NULL;
1522 int rc;
1523
1524 /* de-initialize port */
1525 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1526 if (rc)
1527 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1528
1529 ap->private_data = NULL;
1530 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1531 pp->cmd_slot, pp->cmd_slot_dma);
1532 ata_pad_free(ap, dev);
1533 kfree(pp);
1534 }
1535
1536 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1537 unsigned int port_idx)
1538 {
1539 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1540 base = ahci_port_base_ul(base, port_idx);
1541 VPRINTK("base now==0x%lx\n", base);
1542
1543 port->cmd_addr = base;
1544 port->scr_addr = base + PORT_SCR;
1545
1546 VPRINTK("EXIT\n");
1547 }
1548
1549 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1550 {
1551 struct ahci_host_priv *hpriv = probe_ent->private_data;
1552 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1553 void __iomem *mmio = probe_ent->mmio_base;
1554 unsigned int i, cap_n_ports, using_dac;
1555 int rc;
1556
1557 rc = ahci_reset_controller(mmio, pdev);
1558 if (rc)
1559 return rc;
1560
1561 hpriv->cap = readl(mmio + HOST_CAP);
1562 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1563 cap_n_ports = ahci_nr_ports(hpriv->cap);
1564
1565 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1566 hpriv->cap, hpriv->port_map, cap_n_ports);
1567
1568 if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) {
1569 unsigned int n_ports = cap_n_ports;
1570 u32 port_map = hpriv->port_map;
1571 int max_port = 0;
1572
1573 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
1574 if (port_map & (1 << i)) {
1575 n_ports--;
1576 port_map &= ~(1 << i);
1577 max_port = i;
1578 } else
1579 probe_ent->dummy_port_mask |= 1 << i;
1580 }
1581
1582 if (n_ports || port_map)
1583 dev_printk(KERN_WARNING, &pdev->dev,
1584 "nr_ports (%u) and implemented port map "
1585 "(0x%x) don't match\n",
1586 cap_n_ports, hpriv->port_map);
1587
1588 probe_ent->n_ports = max_port + 1;
1589 } else
1590 probe_ent->n_ports = cap_n_ports;
1591
1592 using_dac = hpriv->cap & HOST_CAP_64;
1593 if (using_dac &&
1594 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1595 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1596 if (rc) {
1597 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1598 if (rc) {
1599 dev_printk(KERN_ERR, &pdev->dev,
1600 "64-bit DMA enable failed\n");
1601 return rc;
1602 }
1603 }
1604 } else {
1605 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1606 if (rc) {
1607 dev_printk(KERN_ERR, &pdev->dev,
1608 "32-bit DMA enable failed\n");
1609 return rc;
1610 }
1611 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1612 if (rc) {
1613 dev_printk(KERN_ERR, &pdev->dev,
1614 "32-bit consistent DMA enable failed\n");
1615 return rc;
1616 }
1617 }
1618
1619 for (i = 0; i < probe_ent->n_ports; i++)
1620 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1621
1622 ahci_init_controller(mmio, pdev, probe_ent->n_ports,
1623 probe_ent->port_flags, hpriv);
1624
1625 pci_set_master(pdev);
1626
1627 return 0;
1628 }
1629
1630 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1631 {
1632 struct ahci_host_priv *hpriv = probe_ent->private_data;
1633 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1634 void __iomem *mmio = probe_ent->mmio_base;
1635 u32 vers, cap, impl, speed;
1636 const char *speed_s;
1637 u16 cc;
1638 const char *scc_s;
1639
1640 vers = readl(mmio + HOST_VERSION);
1641 cap = hpriv->cap;
1642 impl = hpriv->port_map;
1643
1644 speed = (cap >> 20) & 0xf;
1645 if (speed == 1)
1646 speed_s = "1.5";
1647 else if (speed == 2)
1648 speed_s = "3";
1649 else
1650 speed_s = "?";
1651
1652 pci_read_config_word(pdev, 0x0a, &cc);
1653 if (cc == 0x0101)
1654 scc_s = "IDE";
1655 else if (cc == 0x0106)
1656 scc_s = "SATA";
1657 else if (cc == 0x0104)
1658 scc_s = "RAID";
1659 else
1660 scc_s = "unknown";
1661
1662 dev_printk(KERN_INFO, &pdev->dev,
1663 "AHCI %02x%02x.%02x%02x "
1664 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1665 ,
1666
1667 (vers >> 24) & 0xff,
1668 (vers >> 16) & 0xff,
1669 (vers >> 8) & 0xff,
1670 vers & 0xff,
1671
1672 ((cap >> 8) & 0x1f) + 1,
1673 (cap & 0x1f) + 1,
1674 speed_s,
1675 impl,
1676 scc_s);
1677
1678 dev_printk(KERN_INFO, &pdev->dev,
1679 "flags: "
1680 "%s%s%s%s%s%s"
1681 "%s%s%s%s%s%s%s\n"
1682 ,
1683
1684 cap & (1 << 31) ? "64bit " : "",
1685 cap & (1 << 30) ? "ncq " : "",
1686 cap & (1 << 28) ? "ilck " : "",
1687 cap & (1 << 27) ? "stag " : "",
1688 cap & (1 << 26) ? "pm " : "",
1689 cap & (1 << 25) ? "led " : "",
1690
1691 cap & (1 << 24) ? "clo " : "",
1692 cap & (1 << 19) ? "nz " : "",
1693 cap & (1 << 18) ? "only " : "",
1694 cap & (1 << 17) ? "pmp " : "",
1695 cap & (1 << 15) ? "pio " : "",
1696 cap & (1 << 14) ? "slum " : "",
1697 cap & (1 << 13) ? "part " : ""
1698 );
1699 }
1700
1701 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1702 {
1703 static int printed_version;
1704 struct ata_probe_ent *probe_ent = NULL;
1705 struct ahci_host_priv *hpriv;
1706 unsigned long base;
1707 void __iomem *mmio_base;
1708 unsigned int board_idx = (unsigned int) ent->driver_data;
1709 int have_msi, pci_dev_busy = 0;
1710 int rc;
1711
1712 VPRINTK("ENTER\n");
1713
1714 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1715
1716 if (!printed_version++)
1717 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1718
1719 /* JMicron-specific fixup: make sure we're in AHCI mode */
1720 /* This is protected from races with ata_jmicron by the pci probe
1721 locking */
1722 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1723 /* AHCI enable, AHCI on function 0 */
1724 pci_write_config_byte(pdev, 0x41, 0xa1);
1725 /* Function 1 is the PATA controller */
1726 if (PCI_FUNC(pdev->devfn))
1727 return -ENODEV;
1728 }
1729
1730 rc = pci_enable_device(pdev);
1731 if (rc)
1732 return rc;
1733
1734 rc = pci_request_regions(pdev, DRV_NAME);
1735 if (rc) {
1736 pci_dev_busy = 1;
1737 goto err_out;
1738 }
1739
1740 if (pci_enable_msi(pdev) == 0)
1741 have_msi = 1;
1742 else {
1743 pci_intx(pdev, 1);
1744 have_msi = 0;
1745 }
1746
1747 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1748 if (probe_ent == NULL) {
1749 rc = -ENOMEM;
1750 goto err_out_msi;
1751 }
1752
1753 memset(probe_ent, 0, sizeof(*probe_ent));
1754 probe_ent->dev = pci_dev_to_dev(pdev);
1755 INIT_LIST_HEAD(&probe_ent->node);
1756
1757 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1758 if (mmio_base == NULL) {
1759 rc = -ENOMEM;
1760 goto err_out_free_ent;
1761 }
1762 base = (unsigned long) mmio_base;
1763
1764 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1765 if (!hpriv) {
1766 rc = -ENOMEM;
1767 goto err_out_iounmap;
1768 }
1769 memset(hpriv, 0, sizeof(*hpriv));
1770
1771 probe_ent->sht = ahci_port_info[board_idx].sht;
1772 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1773 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1774 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1775 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1776
1777 probe_ent->irq = pdev->irq;
1778 probe_ent->irq_flags = IRQF_SHARED;
1779 probe_ent->mmio_base = mmio_base;
1780 probe_ent->private_data = hpriv;
1781
1782 if (have_msi)
1783 hpriv->flags |= AHCI_FLAG_MSI;
1784
1785 /* initialize adapter */
1786 rc = ahci_host_init(probe_ent);
1787 if (rc)
1788 goto err_out_hpriv;
1789
1790 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
1791 (hpriv->cap & HOST_CAP_NCQ))
1792 probe_ent->port_flags |= ATA_FLAG_NCQ;
1793
1794 ahci_print_info(probe_ent);
1795
1796 /* FIXME: check ata_device_add return value */
1797 ata_device_add(probe_ent);
1798 kfree(probe_ent);
1799
1800 return 0;
1801
1802 err_out_hpriv:
1803 kfree(hpriv);
1804 err_out_iounmap:
1805 pci_iounmap(pdev, mmio_base);
1806 err_out_free_ent:
1807 kfree(probe_ent);
1808 err_out_msi:
1809 if (have_msi)
1810 pci_disable_msi(pdev);
1811 else
1812 pci_intx(pdev, 0);
1813 pci_release_regions(pdev);
1814 err_out:
1815 if (!pci_dev_busy)
1816 pci_disable_device(pdev);
1817 return rc;
1818 }
1819
1820 static void ahci_remove_one (struct pci_dev *pdev)
1821 {
1822 struct device *dev = pci_dev_to_dev(pdev);
1823 struct ata_host *host = dev_get_drvdata(dev);
1824 struct ahci_host_priv *hpriv = host->private_data;
1825 unsigned int i;
1826 int have_msi;
1827
1828 for (i = 0; i < host->n_ports; i++)
1829 ata_port_detach(host->ports[i]);
1830
1831 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1832 free_irq(host->irq, host);
1833
1834 for (i = 0; i < host->n_ports; i++) {
1835 struct ata_port *ap = host->ports[i];
1836
1837 ata_scsi_release(ap->scsi_host);
1838 scsi_host_put(ap->scsi_host);
1839 }
1840
1841 kfree(hpriv);
1842 pci_iounmap(pdev, host->mmio_base);
1843 kfree(host);
1844
1845 if (have_msi)
1846 pci_disable_msi(pdev);
1847 else
1848 pci_intx(pdev, 0);
1849 pci_release_regions(pdev);
1850 pci_disable_device(pdev);
1851 dev_set_drvdata(dev, NULL);
1852 }
1853
1854 static int __init ahci_init(void)
1855 {
1856 return pci_register_driver(&ahci_pci_driver);
1857 }
1858
1859 static void __exit ahci_exit(void)
1860 {
1861 pci_unregister_driver(&ahci_pci_driver);
1862 }
1863
1864
1865 MODULE_AUTHOR("Jeff Garzik");
1866 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1867 MODULE_LICENSE("GPL");
1868 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1869 MODULE_VERSION(DRV_VERSION);
1870
1871 module_init(ahci_init);
1872 module_exit(ahci_exit);
Linux with added FPC-III support