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Linux 2.6.20.9
[linux/fpc-iii.git] / drivers / ata / sata_sil.c
bloba12d6384ec90d63907ef3deac6eea2416b28022e
1 /*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2005 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "sata_sil"
49 #define DRV_VERSION "2.0"
50
51 enum {
52 /*
53 * host flags
54 */
55 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
56 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
57 SIL_FLAG_MOD15WRITE = (1 << 30),
58
59 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
60 ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME,
61
62 /*
63 * Controller IDs
64 */
65 sil_3112 = 0,
66 sil_3112_no_sata_irq = 1,
67 sil_3512 = 2,
68 sil_3114 = 3,
69
70 /*
71 * Register offsets
72 */
73 SIL_SYSCFG = 0x48,
74
75 /*
76 * Register bits
77 */
78 /* SYSCFG */
79 SIL_MASK_IDE0_INT = (1 << 22),
80 SIL_MASK_IDE1_INT = (1 << 23),
81 SIL_MASK_IDE2_INT = (1 << 24),
82 SIL_MASK_IDE3_INT = (1 << 25),
83 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
84 SIL_MASK_4PORT = SIL_MASK_2PORT |
85 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
86
87 /* BMDMA/BMDMA2 */
88 SIL_INTR_STEERING = (1 << 1),
89
90 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
91 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
92 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
93 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
94 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
95 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
96 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
97 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
98 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
99 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
100
101 /* SIEN */
102 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
103
104 /*
105 * Others
106 */
107 SIL_QUIRK_MOD15WRITE = (1 << 0),
108 SIL_QUIRK_UDMA5MAX = (1 << 1),
109 };
110
111 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
112 #ifdef CONFIG_PM
113 static int sil_pci_device_resume(struct pci_dev *pdev);
114 #endif
115 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
116 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
117 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
118 static void sil_post_set_mode (struct ata_port *ap);
119 static irqreturn_t sil_interrupt(int irq, void *dev_instance);
120 static void sil_freeze(struct ata_port *ap);
121 static void sil_thaw(struct ata_port *ap);
122
123
124 static const struct pci_device_id sil_pci_tbl[] = {
125 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
126 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
127 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
128 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
129 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
130 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
131 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
132
133 { } /* terminate list */
134 };
135
136
137 /* TODO firmware versions should be added - eric */
138 static const struct sil_drivelist {
139 const char * product;
140 unsigned int quirk;
141 } sil_blacklist [] = {
142 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
143 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
144 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
145 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
146 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
147 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
148 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
149 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
150 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
152 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
153 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
154 { }
155 };
156
157 static struct pci_driver sil_pci_driver = {
158 .name = DRV_NAME,
159 .id_table = sil_pci_tbl,
160 .probe = sil_init_one,
161 .remove = ata_pci_remove_one,
162 #ifdef CONFIG_PM
163 .suspend = ata_pci_device_suspend,
164 .resume = sil_pci_device_resume,
165 #endif
166 };
167
168 static struct scsi_host_template sil_sht = {
169 .module = THIS_MODULE,
170 .name = DRV_NAME,
171 .ioctl = ata_scsi_ioctl,
172 .queuecommand = ata_scsi_queuecmd,
173 .can_queue = ATA_DEF_QUEUE,
174 .this_id = ATA_SHT_THIS_ID,
175 .sg_tablesize = LIBATA_MAX_PRD,
176 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
177 .emulated = ATA_SHT_EMULATED,
178 .use_clustering = ATA_SHT_USE_CLUSTERING,
179 .proc_name = DRV_NAME,
180 .dma_boundary = ATA_DMA_BOUNDARY,
181 .slave_configure = ata_scsi_slave_config,
182 .slave_destroy = ata_scsi_slave_destroy,
183 .bios_param = ata_std_bios_param,
184 #ifdef CONFIG_PM
185 .suspend = ata_scsi_device_suspend,
186 .resume = ata_scsi_device_resume,
187 #endif
188 };
189
190 static const struct ata_port_operations sil_ops = {
191 .port_disable = ata_port_disable,
192 .dev_config = sil_dev_config,
193 .tf_load = ata_tf_load,
194 .tf_read = ata_tf_read,
195 .check_status = ata_check_status,
196 .exec_command = ata_exec_command,
197 .dev_select = ata_std_dev_select,
198 .post_set_mode = sil_post_set_mode,
199 .bmdma_setup = ata_bmdma_setup,
200 .bmdma_start = ata_bmdma_start,
201 .bmdma_stop = ata_bmdma_stop,
202 .bmdma_status = ata_bmdma_status,
203 .qc_prep = ata_qc_prep,
204 .qc_issue = ata_qc_issue_prot,
205 .data_xfer = ata_mmio_data_xfer,
206 .freeze = sil_freeze,
207 .thaw = sil_thaw,
208 .error_handler = ata_bmdma_error_handler,
209 .post_internal_cmd = ata_bmdma_post_internal_cmd,
210 .irq_handler = sil_interrupt,
211 .irq_clear = ata_bmdma_irq_clear,
212 .scr_read = sil_scr_read,
213 .scr_write = sil_scr_write,
214 .port_start = ata_port_start,
215 .port_stop = ata_port_stop,
216 .host_stop = ata_pci_host_stop,
217 };
218
219 static const struct ata_port_info sil_port_info[] = {
220 /* sil_3112 */
221 {
222 .sht = &sil_sht,
223 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
224 .pio_mask = 0x1f, /* pio0-4 */
225 .mwdma_mask = 0x07, /* mwdma0-2 */
226 .udma_mask = 0x3f, /* udma0-5 */
227 .port_ops = &sil_ops,
228 },
229 /* sil_3112_no_sata_irq */
230 {
231 .sht = &sil_sht,
232 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
233 SIL_FLAG_NO_SATA_IRQ,
234 .pio_mask = 0x1f, /* pio0-4 */
235 .mwdma_mask = 0x07, /* mwdma0-2 */
236 .udma_mask = 0x3f, /* udma0-5 */
237 .port_ops = &sil_ops,
238 },
239 /* sil_3512 */
240 {
241 .sht = &sil_sht,
242 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
243 .pio_mask = 0x1f, /* pio0-4 */
244 .mwdma_mask = 0x07, /* mwdma0-2 */
245 .udma_mask = 0x3f, /* udma0-5 */
246 .port_ops = &sil_ops,
247 },
248 /* sil_3114 */
249 {
250 .sht = &sil_sht,
251 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
252 .pio_mask = 0x1f, /* pio0-4 */
253 .mwdma_mask = 0x07, /* mwdma0-2 */
254 .udma_mask = 0x3f, /* udma0-5 */
255 .port_ops = &sil_ops,
256 },
257 };
258
259 /* per-port register offsets */
260 /* TODO: we can probably calculate rather than use a table */
261 static const struct {
262 unsigned long tf; /* ATA taskfile register block */
263 unsigned long ctl; /* ATA control/altstatus register block */
264 unsigned long bmdma; /* DMA register block */
265 unsigned long bmdma2; /* DMA register block #2 */
266 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
267 unsigned long scr; /* SATA control register block */
268 unsigned long sien; /* SATA Interrupt Enable register */
269 unsigned long xfer_mode;/* data transfer mode register */
270 unsigned long sfis_cfg; /* SATA FIS reception config register */
271 } sil_port[] = {
272 /* port 0 ... */
273 { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
274 { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
275 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
276 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
277 /* ... port 3 */
278 };
279
280 MODULE_AUTHOR("Jeff Garzik");
281 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
282 MODULE_LICENSE("GPL");
283 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
284 MODULE_VERSION(DRV_VERSION);
285
286 static int slow_down = 0;
287 module_param(slow_down, int, 0444);
288 MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
289
290
291 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
292 {
293 u8 cache_line = 0;
294 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
295 return cache_line;
296 }
297
298 static void sil_post_set_mode (struct ata_port *ap)
299 {
300 struct ata_host *host = ap->host;
301 struct ata_device *dev;
302 void __iomem *addr = host->mmio_base + sil_port[ap->port_no].xfer_mode;
303 u32 tmp, dev_mode[2];
304 unsigned int i;
305
306 for (i = 0; i < 2; i++) {
307 dev = &ap->device[i];
308 if (!ata_dev_enabled(dev))
309 dev_mode[i] = 0; /* PIO0/1/2 */
310 else if (dev->flags & ATA_DFLAG_PIO)
311 dev_mode[i] = 1; /* PIO3/4 */
312 else
313 dev_mode[i] = 3; /* UDMA */
314 /* value 2 indicates MDMA */
315 }
316
317 tmp = readl(addr);
318 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
319 tmp |= dev_mode[0];
320 tmp |= (dev_mode[1] << 4);
321 writel(tmp, addr);
322 readl(addr); /* flush */
323 }
324
325 static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
326 {
327 unsigned long offset = ap->ioaddr.scr_addr;
328
329 switch (sc_reg) {
330 case SCR_STATUS:
331 return offset + 4;
332 case SCR_ERROR:
333 return offset + 8;
334 case SCR_CONTROL:
335 return offset;
336 default:
337 /* do nothing */
338 break;
339 }
340
341 return 0;
342 }
343
344 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
345 {
346 void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
347 if (mmio)
348 return readl(mmio);
349 return 0xffffffffU;
350 }
351
352 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
353 {
354 void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
355 if (mmio)
356 writel(val, mmio);
357 }
358
359 static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
360 {
361 struct ata_eh_info *ehi = &ap->eh_info;
362 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
363 u8 status;
364
365 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
366 u32 serror;
367
368 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
369 * controllers continue to assert IRQ as long as
370 * SError bits are pending. Clear SError immediately.
371 */
372 serror = sil_scr_read(ap, SCR_ERROR);
373 sil_scr_write(ap, SCR_ERROR, serror);
374
375 /* Trigger hotplug and accumulate SError only if the
376 * port isn't already frozen. Otherwise, PHY events
377 * during hardreset makes controllers with broken SIEN
378 * repeat probing needlessly.
379 */
380 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
381 ata_ehi_hotplugged(&ap->eh_info);
382 ap->eh_info.serror |= serror;
383 }
384
385 goto freeze;
386 }
387
388 if (unlikely(!qc))
389 goto freeze;
390
391 if (unlikely(qc->tf.flags & ATA_TFLAG_POLLING)) {
392 /* this sometimes happens, just clear IRQ */
393 ata_chk_status(ap);
394 return;
395 }
396
397 /* Check whether we are expecting interrupt in this state */
398 switch (ap->hsm_task_state) {
399 case HSM_ST_FIRST:
400 /* Some pre-ATAPI-4 devices assert INTRQ
401 * at this state when ready to receive CDB.
402 */
403
404 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
405 * The flag was turned on only for atapi devices.
406 * No need to check is_atapi_taskfile(&qc->tf) again.
407 */
408 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
409 goto err_hsm;
410 break;
411 case HSM_ST_LAST:
412 if (qc->tf.protocol == ATA_PROT_DMA ||
413 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
414 /* clear DMA-Start bit */
415 ap->ops->bmdma_stop(qc);
416
417 if (bmdma2 & SIL_DMA_ERROR) {
418 qc->err_mask |= AC_ERR_HOST_BUS;
419 ap->hsm_task_state = HSM_ST_ERR;
420 }
421 }
422 break;
423 case HSM_ST:
424 break;
425 default:
426 goto err_hsm;
427 }
428
429 /* check main status, clearing INTRQ */
430 status = ata_chk_status(ap);
431 if (unlikely(status & ATA_BUSY))
432 goto err_hsm;
433
434 /* ack bmdma irq events */
435 ata_bmdma_irq_clear(ap);
436
437 /* kick HSM in the ass */
438 ata_hsm_move(ap, qc, status, 0);
439
440 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
441 qc->tf.protocol == ATA_PROT_ATAPI_DMA))
442 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
443
444 return;
445
446 err_hsm:
447 qc->err_mask |= AC_ERR_HSM;
448 freeze:
449 ata_port_freeze(ap);
450 }
451
452 static irqreturn_t sil_interrupt(int irq, void *dev_instance)
453 {
454 struct ata_host *host = dev_instance;
455 void __iomem *mmio_base = host->mmio_base;
456 int handled = 0;
457 int i;
458
459 spin_lock(&host->lock);
460
461 for (i = 0; i < host->n_ports; i++) {
462 struct ata_port *ap = host->ports[i];
463 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
464
465 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
466 continue;
467
468 /* turn off SATA_IRQ if not supported */
469 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
470 bmdma2 &= ~SIL_DMA_SATA_IRQ;
471
472 if (bmdma2 == 0xffffffff ||
473 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
474 continue;
475
476 sil_host_intr(ap, bmdma2);
477 handled = 1;
478 }
479
480 spin_unlock(&host->lock);
481
482 return IRQ_RETVAL(handled);
483 }
484
485 static void sil_freeze(struct ata_port *ap)
486 {
487 void __iomem *mmio_base = ap->host->mmio_base;
488 u32 tmp;
489
490 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
491 writel(0, mmio_base + sil_port[ap->port_no].sien);
492
493 /* plug IRQ */
494 tmp = readl(mmio_base + SIL_SYSCFG);
495 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
496 writel(tmp, mmio_base + SIL_SYSCFG);
497 readl(mmio_base + SIL_SYSCFG); /* flush */
498 }
499
500 static void sil_thaw(struct ata_port *ap)
501 {
502 void __iomem *mmio_base = ap->host->mmio_base;
503 u32 tmp;
504
505 /* clear IRQ */
506 ata_chk_status(ap);
507 ata_bmdma_irq_clear(ap);
508
509 /* turn on SATA IRQ if supported */
510 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
511 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
512
513 /* turn on IRQ */
514 tmp = readl(mmio_base + SIL_SYSCFG);
515 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
516 writel(tmp, mmio_base + SIL_SYSCFG);
517 }
518
519 /**
520 * sil_dev_config - Apply device/host-specific errata fixups
521 * @ap: Port containing device to be examined
522 * @dev: Device to be examined
523 *
524 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
525 * device is known to be present, this function is called.
526 * We apply two errata fixups which are specific to Silicon Image,
527 * a Seagate and a Maxtor fixup.
528 *
529 * For certain Seagate devices, we must limit the maximum sectors
530 * to under 8K.
531 *
532 * For certain Maxtor devices, we must not program the drive
533 * beyond udma5.
534 *
535 * Both fixups are unfairly pessimistic. As soon as I get more
536 * information on these errata, I will create a more exhaustive
537 * list, and apply the fixups to only the specific
538 * devices/hosts/firmwares that need it.
539 *
540 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
541 * The Maxtor quirk is in the blacklist, but I'm keeping the original
542 * pessimistic fix for the following reasons...
543 * - There seems to be less info on it, only one device gleaned off the
544 * Windows driver, maybe only one is affected. More info would be greatly
545 * appreciated.
546 * - But then again UDMA5 is hardly anything to complain about
547 */
548 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
549 {
550 int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO;
551 unsigned int n, quirks = 0;
552 unsigned char model_num[41];
553
554 ata_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
555
556 for (n = 0; sil_blacklist[n].product; n++)
557 if (!strcmp(sil_blacklist[n].product, model_num)) {
558 quirks = sil_blacklist[n].quirk;
559 break;
560 }
561
562 /* limit requests to 15 sectors */
563 if (slow_down ||
564 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
565 (quirks & SIL_QUIRK_MOD15WRITE))) {
566 if (print_info)
567 ata_dev_printk(dev, KERN_INFO, "applying Seagate "
568 "errata fix (mod15write workaround)\n");
569 dev->max_sectors = 15;
570 return;
571 }
572
573 /* limit to udma5 */
574 if (quirks & SIL_QUIRK_UDMA5MAX) {
575 if (print_info)
576 ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
577 "errata fix %s\n", model_num);
578 dev->udma_mask &= ATA_UDMA5;
579 return;
580 }
581 }
582
583 static void sil_init_controller(struct pci_dev *pdev,
584 int n_ports, unsigned long port_flags,
585 void __iomem *mmio_base)
586 {
587 u8 cls;
588 u32 tmp;
589 int i;
590
591 /* Initialize FIFO PCI bus arbitration */
592 cls = sil_get_device_cache_line(pdev);
593 if (cls) {
594 cls >>= 3;
595 cls++; /* cls = (line_size/8)+1 */
596 for (i = 0; i < n_ports; i++)
597 writew(cls << 8 | cls,
598 mmio_base + sil_port[i].fifo_cfg);
599 } else
600 dev_printk(KERN_WARNING, &pdev->dev,
601 "cache line size not set. Driver may not function\n");
602
603 /* Apply R_ERR on DMA activate FIS errata workaround */
604 if (port_flags & SIL_FLAG_RERR_ON_DMA_ACT) {
605 int cnt;
606
607 for (i = 0, cnt = 0; i < n_ports; i++) {
608 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
609 if ((tmp & 0x3) != 0x01)
610 continue;
611 if (!cnt)
612 dev_printk(KERN_INFO, &pdev->dev,
613 "Applying R_ERR on DMA activate "
614 "FIS errata fix\n");
615 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
616 cnt++;
617 }
618 }
619
620 if (n_ports == 4) {
621 /* flip the magic "make 4 ports work" bit */
622 tmp = readl(mmio_base + sil_port[2].bmdma);
623 if ((tmp & SIL_INTR_STEERING) == 0)
624 writel(tmp | SIL_INTR_STEERING,
625 mmio_base + sil_port[2].bmdma);
626 }
627 }
628
629 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
630 {
631 static int printed_version;
632 struct ata_probe_ent *probe_ent = NULL;
633 unsigned long base;
634 void __iomem *mmio_base;
635 int rc;
636 unsigned int i;
637 int pci_dev_busy = 0;
638
639 if (!printed_version++)
640 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
641
642 rc = pci_enable_device(pdev);
643 if (rc)
644 return rc;
645
646 rc = pci_request_regions(pdev, DRV_NAME);
647 if (rc) {
648 pci_dev_busy = 1;
649 goto err_out;
650 }
651
652 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
653 if (rc)
654 goto err_out_regions;
655 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
656 if (rc)
657 goto err_out_regions;
658
659 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
660 if (probe_ent == NULL) {
661 rc = -ENOMEM;
662 goto err_out_regions;
663 }
664
665 INIT_LIST_HEAD(&probe_ent->node);
666 probe_ent->dev = pci_dev_to_dev(pdev);
667 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
668 probe_ent->sht = sil_port_info[ent->driver_data].sht;
669 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
670 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
671 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
672 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
673 probe_ent->irq = pdev->irq;
674 probe_ent->irq_flags = IRQF_SHARED;
675 probe_ent->port_flags = sil_port_info[ent->driver_data].flags;
676
677 mmio_base = pci_iomap(pdev, 5, 0);
678 if (mmio_base == NULL) {
679 rc = -ENOMEM;
680 goto err_out_free_ent;
681 }
682
683 probe_ent->mmio_base = mmio_base;
684
685 base = (unsigned long) mmio_base;
686
687 for (i = 0; i < probe_ent->n_ports; i++) {
688 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
689 probe_ent->port[i].altstatus_addr =
690 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
691 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
692 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
693 ata_std_ports(&probe_ent->port[i]);
694 }
695
696 sil_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags,
697 mmio_base);
698
699 pci_set_master(pdev);
700
701 /* FIXME: check ata_device_add return value */
702 ata_device_add(probe_ent);
703 kfree(probe_ent);
704
705 return 0;
706
707 err_out_free_ent:
708 kfree(probe_ent);
709 err_out_regions:
710 pci_release_regions(pdev);
711 err_out:
712 if (!pci_dev_busy)
713 pci_disable_device(pdev);
714 return rc;
715 }
716
717 #ifdef CONFIG_PM
718 static int sil_pci_device_resume(struct pci_dev *pdev)
719 {
720 struct ata_host *host = dev_get_drvdata(&pdev->dev);
721
722 ata_pci_device_do_resume(pdev);
723 sil_init_controller(pdev, host->n_ports, host->ports[0]->flags,
724 host->mmio_base);
725 ata_host_resume(host);
726
727 return 0;
728 }
729 #endif
730
731 static int __init sil_init(void)
732 {
733 return pci_register_driver(&sil_pci_driver);
734 }
735
736 static void __exit sil_exit(void)
737 {
738 pci_unregister_driver(&sil_pci_driver);
739 }
740
741
742 module_init(sil_init);
743 module_exit(sil_exit);
Linux with added FPC-III support