arch/arm/mach-imx/mach-imx6q.c

   1 /*
   2  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/cpu.h>
  16 #include <linux/delay.h>
  17 #include <linux/export.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqchip.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/pm_opp.h>
  27 #include <linux/pci.h>
  28 #include <linux/phy.h>
  29 #include <linux/reboot.h>
  30 #include <linux/regmap.h>
  31 #include <linux/micrel_phy.h>
  32 #include <linux/mfd/syscon.h>
  33 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  34 #include <asm/mach/arch.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/system_misc.h>
  37
  38 #include "common.h"
  39 #include "cpuidle.h"
  40 #include "hardware.h"
  41
  42 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
  43 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
  44 {
  45         if (IS_BUILTIN(CONFIG_PHYLIB)) {
  46                 /* min rx data delay */
  47                 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
  48                         0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
  49                 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
  50
  51                 /* max rx/tx clock delay, min rx/tx control delay */
  52                 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
  53                         0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
  54                 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
  55                 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
  56                         MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
  57         }
  58
  59         return 0;
  60 }
  61
  62 static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
  63 {
  64         phy_write(dev, 0x0d, device);
  65         phy_write(dev, 0x0e, reg);
  66         phy_write(dev, 0x0d, (1 << 14) | device);
  67         phy_write(dev, 0x0e, val);
  68 }
  69
  70 static int ksz9031rn_phy_fixup(struct phy_device *dev)
  71 {
  72         /*
  73          * min rx data delay, max rx/tx clock delay,
  74          * min rx/tx control delay
  75          */
  76         mmd_write_reg(dev, 2, 4, 0);
  77         mmd_write_reg(dev, 2, 5, 0);
  78         mmd_write_reg(dev, 2, 8, 0x003ff);
  79
  80         return 0;
  81 }
  82
  83 /*
  84  * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
  85  * as they are used for slots1-7 PERST#
  86  */
  87 static void ventana_pciesw_early_fixup(struct pci_dev *dev)
  88 {
  89         u32 dw;
  90
  91         if (!of_machine_is_compatible("gw,ventana"))
  92                 return;
  93
  94         if (dev->devfn != 0)
  95                 return;
  96
  97         pci_read_config_dword(dev, 0x62c, &dw);
  98         dw |= 0xaaa8; // GPIO1-7 outputs
  99         pci_write_config_dword(dev, 0x62c, dw);
 100
 101         pci_read_config_dword(dev, 0x644, &dw);
 102         dw |= 0xfe;   // GPIO1-7 output high
 103         pci_write_config_dword(dev, 0x644, dw);
 104
 105         msleep(100);
 106 }
 107 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
 108 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
 109 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
 110
 111 static int ar8031_phy_fixup(struct phy_device *dev)
 112 {
 113         u16 val;
 114
 115         /* To enable AR8031 output a 125MHz clk from CLK_25M */
 116         phy_write(dev, 0xd, 0x7);
 117         phy_write(dev, 0xe, 0x8016);
 118         phy_write(dev, 0xd, 0x4007);
 119
 120         val = phy_read(dev, 0xe);
 121         val &= 0xffe3;
 122         val |= 0x18;
 123         phy_write(dev, 0xe, val);
 124
 125         /* introduce tx clock delay */
 126         phy_write(dev, 0x1d, 0x5);
 127         val = phy_read(dev, 0x1e);
 128         val |= 0x0100;
 129         phy_write(dev, 0x1e, val);
 130
 131         return 0;
 132 }
 133
 134 #define PHY_ID_AR8031   0x004dd074
 135
 136 static int ar8035_phy_fixup(struct phy_device *dev)
 137 {
 138         u16 val;
 139
 140         /* Ar803x phy SmartEEE feature cause link status generates glitch,
 141          * which cause ethernet link down/up issue, so disable SmartEEE
 142          */
 143         phy_write(dev, 0xd, 0x3);
 144         phy_write(dev, 0xe, 0x805d);
 145         phy_write(dev, 0xd, 0x4003);
 146
 147         val = phy_read(dev, 0xe);
 148         phy_write(dev, 0xe, val & ~(1 << 8));
 149
 150         /*
 151          * Enable 125MHz clock from CLK_25M on the AR8031.  This
 152          * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
 153          * Also, introduce a tx clock delay.
 154          *
 155          * This is the same as is the AR8031 fixup.
 156          */
 157         ar8031_phy_fixup(dev);
 158
 159         /*check phy power*/
 160         val = phy_read(dev, 0x0);
 161         if (val & BMCR_PDOWN)
 162                 phy_write(dev, 0x0, val & ~BMCR_PDOWN);
 163
 164         return 0;
 165 }
 166
 167 #define PHY_ID_AR8035 0x004dd072
 168
 169 static void __init imx6q_enet_phy_init(void)
 170 {
 171         if (IS_BUILTIN(CONFIG_PHYLIB)) {
 172                 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
 173                                 ksz9021rn_phy_fixup);
 174                 phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
 175                                 ksz9031rn_phy_fixup);
 176                 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
 177                                 ar8031_phy_fixup);
 178                 phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
 179                                 ar8035_phy_fixup);
 180         }
 181 }
 182
 183 static void __init imx6q_1588_init(void)
 184 {
 185         struct regmap *gpr;
 186
 187         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 188         if (!IS_ERR(gpr))
 189                 regmap_update_bits(gpr, IOMUXC_GPR1,
 190                                 IMX6Q_GPR1_ENET_CLK_SEL_MASK,
 191                                 IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
 192         else
 193                 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
 194
 195 }
 196
 197 static void __init imx6q_init_machine(void)
 198 {
 199         struct device *parent;
 200
 201         imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
 202                               imx_get_soc_revision());
 203
 204         mxc_arch_reset_init_dt();
 205
 206         parent = imx_soc_device_init();
 207         if (parent == NULL)
 208                 pr_warn("failed to initialize soc device\n");
 209
 210         imx6q_enet_phy_init();
 211
 212         of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
 213
 214         imx_anatop_init();
 215         cpu_is_imx6q() ?  imx6q_pm_init() : imx6dl_pm_init();
 216         imx6q_1588_init();
 217 }
 218
 219 #define OCOTP_CFG3                      0x440
 220 #define OCOTP_CFG3_SPEED_SHIFT          16
 221 #define OCOTP_CFG3_SPEED_1P2GHZ         0x3
 222
 223 static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
 224 {
 225         struct device_node *np;
 226         void __iomem *base;
 227         u32 val;
 228
 229         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
 230         if (!np) {
 231                 pr_warn("failed to find ocotp node\n");
 232                 return;
 233         }
 234
 235         base = of_iomap(np, 0);
 236         if (!base) {
 237                 pr_warn("failed to map ocotp\n");
 238                 goto put_node;
 239         }
 240
 241         val = readl_relaxed(base + OCOTP_CFG3);
 242         val >>= OCOTP_CFG3_SPEED_SHIFT;
 243         if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
 244                 if (dev_pm_opp_disable(cpu_dev, 1200000000))
 245                         pr_warn("failed to disable 1.2 GHz OPP\n");
 246
 247 put_node:
 248         of_node_put(np);
 249 }
 250
 251 static void __init imx6q_opp_init(void)
 252 {
 253         struct device_node *np;
 254         struct device *cpu_dev = get_cpu_device(0);
 255
 256         if (!cpu_dev) {
 257                 pr_warn("failed to get cpu0 device\n");
 258                 return;
 259         }
 260         np = of_node_get(cpu_dev->of_node);
 261         if (!np) {
 262                 pr_warn("failed to find cpu0 node\n");
 263                 return;
 264         }
 265
 266         if (of_init_opp_table(cpu_dev)) {
 267                 pr_warn("failed to init OPP table\n");
 268                 goto put_node;
 269         }
 270
 271         imx6q_opp_check_1p2ghz(cpu_dev);
 272
 273 put_node:
 274         of_node_put(np);
 275 }
 276
 277 static struct platform_device imx6q_cpufreq_pdev = {
 278         .name = "imx6q-cpufreq",
 279 };
 280
 281 static void __init imx6q_init_late(void)
 282 {
 283         /*
 284          * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
 285          * to run cpuidle on them.
 286          */
 287         if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
 288                 imx6q_cpuidle_init();
 289
 290         if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
 291                 imx6q_opp_init();
 292                 platform_device_register(&imx6q_cpufreq_pdev);
 293         }
 294 }
 295
 296 static void __init imx6q_map_io(void)
 297 {
 298         debug_ll_io_init();
 299         imx_scu_map_io();
 300 }
 301
 302 static void __init imx6q_init_irq(void)
 303 {
 304         imx_init_revision_from_anatop();
 305         imx_init_l2cache();
 306         imx_src_init();
 307         imx_gpc_init();
 308         irqchip_init();
 309 }
 310
 311 static const char *imx6q_dt_compat[] __initconst = {
 312         "fsl,imx6dl",
 313         "fsl,imx6q",
 314         NULL,
 315 };
 316
 317 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
 318         .smp            = smp_ops(imx_smp_ops),
 319         .map_io         = imx6q_map_io,
 320         .init_irq       = imx6q_init_irq,
 321         .init_machine   = imx6q_init_machine,
 322         .init_late      = imx6q_init_late,
 323         .dt_compat      = imx6q_dt_compat,
 324         .restart        = mxc_restart,
 325 MACHINE_END