2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
8 * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
9 * Copyright 1999 Hewlett Packard Co.
14 #include <linux/ptrace.h>
15 #include <linux/sched.h>
16 #include <linux/sched/debug.h>
17 #include <linux/interrupt.h>
18 #include <linux/extable.h>
19 #include <linux/uaccess.h>
20 #include <linux/hugetlb.h>
22 #include <asm/traps.h>
24 /* Various important other fields */
25 #define bit22set(x) (x & 0x00000200)
26 #define bits23_25set(x) (x & 0x000001c0)
27 #define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80)
28 /* extended opcode is 0x6a */
30 #define BITSSET 0x1c0 /* for identifying LDCW */
33 int show_unhandled_signals
= 1;
36 * parisc_acctyp(unsigned int inst) --
37 * Given a PA-RISC memory access instruction, determine if the
38 * the instruction would perform a memory read or memory write
41 * This function assumes that the given instruction is a memory access
42 * instruction (i.e. you should really only call it if you know that
43 * the instruction has generated some sort of a memory access fault).
46 * VM_READ if read operation
47 * VM_WRITE if write operation
48 * VM_EXEC if execute operation
51 parisc_acctyp(unsigned long code
, unsigned int inst
)
53 if (code
== 6 || code
== 16)
56 switch (inst
& 0xf0000000) {
57 case 0x40000000: /* load */
58 case 0x50000000: /* new load */
61 case 0x60000000: /* store */
62 case 0x70000000: /* new store */
65 case 0x20000000: /* coproc */
66 case 0x30000000: /* coproc2 */
71 case 0x0: /* indexed/memory management */
74 * Check for the 'Graphics Flush Read' instruction.
75 * It resembles an FDC instruction, except for bits
76 * 20 and 21. Any combination other than zero will
77 * utilize the block mover functionality on some
78 * older PA-RISC platforms. The case where a block
79 * move is performed from VM to graphics IO space
80 * should be treated as a READ.
82 * The significance of bits 20,21 in the FDC
85 * 00 Flush data cache (normal instruction behavior)
86 * 01 Graphics flush write (IO space -> VM)
87 * 10 Graphics flush read (VM -> IO space)
88 * 11 Graphics flush read/write (VM <-> IO space)
90 if (isGraphicsFlushRead(inst
))
95 * Check for LDCWX and LDCWS (semaphore instructions).
96 * If bits 23 through 25 are all 1's it is one of
97 * the above two instructions and is a write.
99 * Note: With the limited bits we are looking at,
100 * this will also catch PROBEW and PROBEWI. However,
101 * these should never get in here because they don't
102 * generate exceptions of the type:
103 * Data TLB miss fault/data page fault
104 * Data memory protection trap
106 if (bits23_25set(inst
) == BITSSET
)
109 return VM_READ
; /* Default */
111 return VM_READ
; /* Default */
116 #undef isGraphicsFlushRead
121 /* This is the treewalk to find a vma which is the highest that has
122 * a start < addr. We're using find_vma_prev instead right now, but
123 * we might want to use this at some point in the future. Probably
124 * not, but I want it committed to CVS so I don't lose it :-)
126 while (tree
!= vm_avl_empty
) {
127 if (tree
->vm_start
> addr
) {
128 tree
= tree
->vm_avl_left
;
131 if (prev
->vm_next
== NULL
)
133 if (prev
->vm_next
->vm_start
> addr
)
135 tree
= tree
->vm_avl_right
;
140 int fixup_exception(struct pt_regs
*regs
)
142 const struct exception_table_entry
*fix
;
144 fix
= search_exception_tables(regs
->iaoq
[0]);
147 * Fix up get_user() and put_user().
148 * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant
149 * bit in the relative address of the fixup routine to indicate
150 * that %r8 should be loaded with -EFAULT to report a userspace
153 if (fix
->fixup
& 1) {
154 regs
->gr
[8] = -EFAULT
;
156 /* zero target register for get_user() */
157 if (parisc_acctyp(0, regs
->iir
) == VM_READ
) {
158 int treg
= regs
->iir
& 0x1f;
164 regs
->iaoq
[0] = (unsigned long)&fix
->fixup
+ fix
->fixup
;
167 * NOTE: In some cases the faulting instruction
168 * may be in the delay slot of a branch. We
169 * don't want to take the branch, so we don't
170 * increment iaoq[1], instead we set it to be
171 * iaoq[0]+4, and clear the B bit in the PSW
173 regs
->iaoq
[1] = regs
->iaoq
[0] + 4;
174 regs
->gr
[0] &= ~PSW_B
; /* IPSW in gr[0] */
183 * parisc hardware trap list
185 * Documented in section 3 "Addressing and Access Control" of the
186 * "PA-RISC 1.1 Architecture and Instruction Set Reference Manual"
187 * https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf
189 * For implementation see handle_interruption() in traps.c
191 static const char * const trap_description
[] = {
192 [1] "High-priority machine check (HPMC)",
193 [2] "Power failure interrupt",
194 [3] "Recovery counter trap",
195 [5] "Low-priority machine check",
196 [6] "Instruction TLB miss fault",
197 [7] "Instruction access rights / protection trap",
198 [8] "Illegal instruction trap",
199 [9] "Break instruction trap",
200 [10] "Privileged operation trap",
201 [11] "Privileged register trap",
202 [12] "Overflow trap",
203 [13] "Conditional trap",
204 [14] "FP Assist Exception trap",
205 [15] "Data TLB miss fault",
206 [16] "Non-access ITLB miss fault",
207 [17] "Non-access DTLB miss fault",
208 [18] "Data memory protection/unaligned access trap",
209 [19] "Data memory break trap",
210 [20] "TLB dirty bit trap",
211 [21] "Page reference trap",
212 [22] "Assist emulation trap",
213 [25] "Taken branch trap",
214 [26] "Data memory access rights trap",
215 [27] "Data memory protection ID trap",
216 [28] "Unaligned data reference trap",
219 const char *trap_name(unsigned long code
)
221 const char *t
= NULL
;
223 if (code
< ARRAY_SIZE(trap_description
))
224 t
= trap_description
[code
];
226 return t
? t
: "Unknown trap";
230 * Print out info about fatal segfaults, if the show_unhandled_signals
234 show_signal_msg(struct pt_regs
*regs
, unsigned long code
,
235 unsigned long address
, struct task_struct
*tsk
,
236 struct vm_area_struct
*vma
)
238 if (!unhandled_signal(tsk
, SIGSEGV
))
241 if (!printk_ratelimit())
245 pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx",
246 tsk
->comm
, code
, address
);
247 print_vma_addr(KERN_CONT
" in ", regs
->iaoq
[0]);
249 pr_cont("\ntrap #%lu: %s%c", code
, trap_name(code
),
253 pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
254 vma
->vm_start
, vma
->vm_end
);
259 void do_page_fault(struct pt_regs
*regs
, unsigned long code
,
260 unsigned long address
)
262 struct vm_area_struct
*vma
, *prev_vma
;
263 struct task_struct
*tsk
;
264 struct mm_struct
*mm
;
265 unsigned long acc_type
;
266 vm_fault_t fault
= 0;
269 if (faulthandler_disabled())
277 flags
= FAULT_FLAG_DEFAULT
;
279 flags
|= FAULT_FLAG_USER
;
281 acc_type
= parisc_acctyp(code
, regs
->iir
);
282 if (acc_type
& VM_WRITE
)
283 flags
|= FAULT_FLAG_WRITE
;
285 down_read(&mm
->mmap_sem
);
286 vma
= find_vma_prev(mm
, address
, &prev_vma
);
287 if (!vma
|| address
< vma
->vm_start
)
288 goto check_expansion
;
290 * Ok, we have a good vm_area for this memory access. We still need to
291 * check the access permissions.
296 if ((vma
->vm_flags
& acc_type
) != acc_type
)
300 * If for any reason at all we couldn't handle the fault, make
301 * sure we exit gracefully rather than endlessly redo the
305 fault
= handle_mm_fault(vma
, address
, flags
);
307 if (fault_signal_pending(fault
, regs
))
310 if (unlikely(fault
& VM_FAULT_ERROR
)) {
312 * We hit a shared mapping outside of the file, or some
313 * other thing happened to us that made us unable to
314 * handle the page fault gracefully.
316 if (fault
& VM_FAULT_OOM
)
318 else if (fault
& VM_FAULT_SIGSEGV
)
320 else if (fault
& (VM_FAULT_SIGBUS
|VM_FAULT_HWPOISON
|
321 VM_FAULT_HWPOISON_LARGE
))
325 if (flags
& FAULT_FLAG_ALLOW_RETRY
) {
326 if (fault
& VM_FAULT_MAJOR
)
330 if (fault
& VM_FAULT_RETRY
) {
332 * No need to up_read(&mm->mmap_sem) as we would
333 * have already released it in __lock_page_or_retry
336 flags
|= FAULT_FLAG_TRIED
;
340 up_read(&mm
->mmap_sem
);
345 if (vma
&& (expand_stack(vma
, address
) == 0))
349 * Something tried to access memory that isn't in our memory map..
352 up_read(&mm
->mmap_sem
);
354 if (user_mode(regs
)) {
358 case 15: /* Data TLB miss fault/Data page fault */
359 /* send SIGSEGV when outside of vma */
361 address
< vma
->vm_start
|| address
>= vma
->vm_end
) {
363 si_code
= SEGV_MAPERR
;
367 /* send SIGSEGV for wrong permissions */
368 if ((vma
->vm_flags
& acc_type
) != acc_type
) {
370 si_code
= SEGV_ACCERR
;
374 /* probably address is outside of mapped file */
376 case 17: /* NA data TLB miss / page fault */
377 case 18: /* Unaligned access - PCXS only */
379 si_code
= (code
== 18) ? BUS_ADRALN
: BUS_ADRERR
;
381 case 16: /* Non-access instruction TLB miss fault */
382 case 26: /* PCXL: Data memory access rights trap */
385 si_code
= (code
== 26) ? SEGV_ACCERR
: SEGV_MAPERR
;
388 #ifdef CONFIG_MEMORY_FAILURE
389 if (fault
& (VM_FAULT_HWPOISON
|VM_FAULT_HWPOISON_LARGE
)) {
390 unsigned int lsb
= 0;
392 "MCE: Killing %s:%d due to hardware memory corruption fault at %08lx\n",
393 tsk
->comm
, tsk
->pid
, address
);
395 * Either small page or large page may be poisoned.
396 * In other words, VM_FAULT_HWPOISON_LARGE and
397 * VM_FAULT_HWPOISON are mutually exclusive.
399 if (fault
& VM_FAULT_HWPOISON_LARGE
)
400 lsb
= hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault
));
401 else if (fault
& VM_FAULT_HWPOISON
)
404 force_sig_mceerr(BUS_MCEERR_AR
, (void __user
*) address
,
409 show_signal_msg(regs
, code
, address
, tsk
, vma
);
411 force_sig_fault(signo
, si_code
, (void __user
*) address
);
417 if (!user_mode(regs
) && fixup_exception(regs
)) {
421 parisc_terminate("Bad Address (null pointer deref?)", regs
, code
, address
);
424 up_read(&mm
->mmap_sem
);
425 if (!user_mode(regs
))
427 pagefault_out_of_memory();