drivers/thermal/qcom/tsens.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef __QCOM_TSENS_H__
   7 #define __QCOM_TSENS_H__
   8
   9 #define ONE_PT_CALIB            0x1
  10 #define ONE_PT_CALIB2           0x2
  11 #define TWO_PT_CALIB            0x3
  12 #define CAL_DEGC_PT1            30
  13 #define CAL_DEGC_PT2            120
  14 #define SLOPE_FACTOR            1000
  15 #define SLOPE_DEFAULT           3200
  16 #define THRESHOLD_MAX_ADC_CODE  0x3ff
  17 #define THRESHOLD_MIN_ADC_CODE  0x0
  18
  19 #include <linux/interrupt.h>
  20 #include <linux/thermal.h>
  21 #include <linux/regmap.h>
  22 #include <linux/slab.h>
  23
  24 struct tsens_priv;
  25
  26 /* IP version numbers in ascending order */
  27 enum tsens_ver {
  28         VER_0_1 = 0,
  29         VER_1_X,
  30         VER_2_X,
  31 };
  32
  33 enum tsens_irq_type {
  34         LOWER,
  35         UPPER,
  36         CRITICAL,
  37 };
  38
  39 /**
  40  * struct tsens_sensor - data for each sensor connected to the tsens device
  41  * @priv: tsens device instance that this sensor is connected to
  42  * @tzd: pointer to the thermal zone that this sensor is in
  43  * @offset: offset of temperature adjustment curve
  44  * @hw_id: HW ID can be used in case of platform-specific IDs
  45  * @slope: slope of temperature adjustment curve
  46  * @status: 8960-specific variable to track 8960 and 8660 status register offset
  47  */
  48 struct tsens_sensor {
  49         struct tsens_priv               *priv;
  50         struct thermal_zone_device      *tzd;
  51         int                             offset;
  52         unsigned int                    hw_id;
  53         int                             slope;
  54         u32                             status;
  55 };
  56
  57 /**
  58  * struct tsens_ops - operations as supported by the tsens device
  59  * @init: Function to initialize the tsens device
  60  * @calibrate: Function to calibrate the tsens device
  61  * @get_temp: Function which returns the temp in millidegC
  62  * @enable: Function to enable (clocks/power) tsens device
  63  * @disable: Function to disable the tsens device
  64  * @suspend: Function to suspend the tsens device
  65  * @resume: Function to resume the tsens device
  66  * @get_trend: Function to get the thermal/temp trend
  67  */
  68 struct tsens_ops {
  69         /* mandatory callbacks */
  70         int (*init)(struct tsens_priv *priv);
  71         int (*calibrate)(struct tsens_priv *priv);
  72         int (*get_temp)(const struct tsens_sensor *s, int *temp);
  73         /* optional callbacks */
  74         int (*enable)(struct tsens_priv *priv, int i);
  75         void (*disable)(struct tsens_priv *priv);
  76         int (*suspend)(struct tsens_priv *priv);
  77         int (*resume)(struct tsens_priv *priv);
  78         int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend);
  79 };
  80
  81 #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
  82         [_name##_##0]  = REG_FIELD(_offset,      _startbit, _stopbit),  \
  83         [_name##_##1]  = REG_FIELD(_offset +  4, _startbit, _stopbit), \
  84         [_name##_##2]  = REG_FIELD(_offset +  8, _startbit, _stopbit), \
  85         [_name##_##3]  = REG_FIELD(_offset + 12, _startbit, _stopbit), \
  86         [_name##_##4]  = REG_FIELD(_offset + 16, _startbit, _stopbit), \
  87         [_name##_##5]  = REG_FIELD(_offset + 20, _startbit, _stopbit), \
  88         [_name##_##6]  = REG_FIELD(_offset + 24, _startbit, _stopbit), \
  89         [_name##_##7]  = REG_FIELD(_offset + 28, _startbit, _stopbit), \
  90         [_name##_##8]  = REG_FIELD(_offset + 32, _startbit, _stopbit), \
  91         [_name##_##9]  = REG_FIELD(_offset + 36, _startbit, _stopbit), \
  92         [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit)
  93
  94 #define REG_FIELD_FOR_EACH_SENSOR16(_name, _offset, _startbit, _stopbit) \
  95         [_name##_##0]  = REG_FIELD(_offset,      _startbit, _stopbit),  \
  96         [_name##_##1]  = REG_FIELD(_offset +  4, _startbit, _stopbit), \
  97         [_name##_##2]  = REG_FIELD(_offset +  8, _startbit, _stopbit), \
  98         [_name##_##3]  = REG_FIELD(_offset + 12, _startbit, _stopbit), \
  99         [_name##_##4]  = REG_FIELD(_offset + 16, _startbit, _stopbit), \
 100         [_name##_##5]  = REG_FIELD(_offset + 20, _startbit, _stopbit), \
 101         [_name##_##6]  = REG_FIELD(_offset + 24, _startbit, _stopbit), \
 102         [_name##_##7]  = REG_FIELD(_offset + 28, _startbit, _stopbit), \
 103         [_name##_##8]  = REG_FIELD(_offset + 32, _startbit, _stopbit), \
 104         [_name##_##9]  = REG_FIELD(_offset + 36, _startbit, _stopbit), \
 105         [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit), \
 106         [_name##_##11] = REG_FIELD(_offset + 44, _startbit, _stopbit), \
 107         [_name##_##12] = REG_FIELD(_offset + 48, _startbit, _stopbit), \
 108         [_name##_##13] = REG_FIELD(_offset + 52, _startbit, _stopbit), \
 109         [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \
 110         [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit)
 111
 112 #define REG_FIELD_SPLIT_BITS_0_15(_name, _offset)               \
 113         [_name##_##0]  = REG_FIELD(_offset,  0,  0),            \
 114         [_name##_##1]  = REG_FIELD(_offset,  1,  1),    \
 115         [_name##_##2]  = REG_FIELD(_offset,  2,  2),    \
 116         [_name##_##3]  = REG_FIELD(_offset,  3,  3),    \
 117         [_name##_##4]  = REG_FIELD(_offset,  4,  4),    \
 118         [_name##_##5]  = REG_FIELD(_offset,  5,  5),    \
 119         [_name##_##6]  = REG_FIELD(_offset,  6,  6),    \
 120         [_name##_##7]  = REG_FIELD(_offset,  7,  7),    \
 121         [_name##_##8]  = REG_FIELD(_offset,  8,  8),    \
 122         [_name##_##9]  = REG_FIELD(_offset,  9,  9),    \
 123         [_name##_##10] = REG_FIELD(_offset, 10, 10),    \
 124         [_name##_##11] = REG_FIELD(_offset, 11, 11),    \
 125         [_name##_##12] = REG_FIELD(_offset, 12, 12),    \
 126         [_name##_##13] = REG_FIELD(_offset, 13, 13),    \
 127         [_name##_##14] = REG_FIELD(_offset, 14, 14),    \
 128         [_name##_##15] = REG_FIELD(_offset, 15, 15)
 129
 130 #define REG_FIELD_SPLIT_BITS_16_31(_name, _offset)              \
 131         [_name##_##0]  = REG_FIELD(_offset, 16, 16),            \
 132         [_name##_##1]  = REG_FIELD(_offset, 17, 17),    \
 133         [_name##_##2]  = REG_FIELD(_offset, 18, 18),    \
 134         [_name##_##3]  = REG_FIELD(_offset, 19, 19),    \
 135         [_name##_##4]  = REG_FIELD(_offset, 20, 20),    \
 136         [_name##_##5]  = REG_FIELD(_offset, 21, 21),    \
 137         [_name##_##6]  = REG_FIELD(_offset, 22, 22),    \
 138         [_name##_##7]  = REG_FIELD(_offset, 23, 23),    \
 139         [_name##_##8]  = REG_FIELD(_offset, 24, 24),    \
 140         [_name##_##9]  = REG_FIELD(_offset, 25, 25),    \
 141         [_name##_##10] = REG_FIELD(_offset, 26, 26),    \
 142         [_name##_##11] = REG_FIELD(_offset, 27, 27),    \
 143         [_name##_##12] = REG_FIELD(_offset, 28, 28),    \
 144         [_name##_##13] = REG_FIELD(_offset, 29, 29),    \
 145         [_name##_##14] = REG_FIELD(_offset, 30, 30),    \
 146         [_name##_##15] = REG_FIELD(_offset, 31, 31)
 147
 148 /*
 149  * reg_field IDs to use as an index into an array
 150  * If you change the order of the entries, check the devm_regmap_field_alloc()
 151  * calls in init_common()
 152  */
 153 enum regfield_ids {
 154         /* ----- SROT ------ */
 155         /* HW_VER */
 156         VER_MAJOR,
 157         VER_MINOR,
 158         VER_STEP,
 159         /* CTRL_OFFSET */
 160         TSENS_EN,
 161         TSENS_SW_RST,
 162         SENSOR_EN,
 163         CODE_OR_TEMP,
 164
 165         /* ----- TM ------ */
 166         /* TRDY */
 167         TRDY,
 168         /* INTERRUPT ENABLE */
 169         INT_EN, /* v2+ has separate enables for crit, upper and lower irq */
 170         /* STATUS */
 171         LAST_TEMP_0,    /* Last temperature reading */
 172         LAST_TEMP_1,
 173         LAST_TEMP_2,
 174         LAST_TEMP_3,
 175         LAST_TEMP_4,
 176         LAST_TEMP_5,
 177         LAST_TEMP_6,
 178         LAST_TEMP_7,
 179         LAST_TEMP_8,
 180         LAST_TEMP_9,
 181         LAST_TEMP_10,
 182         LAST_TEMP_11,
 183         LAST_TEMP_12,
 184         LAST_TEMP_13,
 185         LAST_TEMP_14,
 186         LAST_TEMP_15,
 187         VALID_0,                /* VALID reading or not */
 188         VALID_1,
 189         VALID_2,
 190         VALID_3,
 191         VALID_4,
 192         VALID_5,
 193         VALID_6,
 194         VALID_7,
 195         VALID_8,
 196         VALID_9,
 197         VALID_10,
 198         VALID_11,
 199         VALID_12,
 200         VALID_13,
 201         VALID_14,
 202         VALID_15,
 203         LOWER_STATUS_0, /* LOWER threshold violated */
 204         LOWER_STATUS_1,
 205         LOWER_STATUS_2,
 206         LOWER_STATUS_3,
 207         LOWER_STATUS_4,
 208         LOWER_STATUS_5,
 209         LOWER_STATUS_6,
 210         LOWER_STATUS_7,
 211         LOWER_STATUS_8,
 212         LOWER_STATUS_9,
 213         LOWER_STATUS_10,
 214         LOWER_STATUS_11,
 215         LOWER_STATUS_12,
 216         LOWER_STATUS_13,
 217         LOWER_STATUS_14,
 218         LOWER_STATUS_15,
 219         LOW_INT_STATUS_0,       /* LOWER interrupt status */
 220         LOW_INT_STATUS_1,
 221         LOW_INT_STATUS_2,
 222         LOW_INT_STATUS_3,
 223         LOW_INT_STATUS_4,
 224         LOW_INT_STATUS_5,
 225         LOW_INT_STATUS_6,
 226         LOW_INT_STATUS_7,
 227         LOW_INT_STATUS_8,
 228         LOW_INT_STATUS_9,
 229         LOW_INT_STATUS_10,
 230         LOW_INT_STATUS_11,
 231         LOW_INT_STATUS_12,
 232         LOW_INT_STATUS_13,
 233         LOW_INT_STATUS_14,
 234         LOW_INT_STATUS_15,
 235         LOW_INT_CLEAR_0,        /* LOWER interrupt clear */
 236         LOW_INT_CLEAR_1,
 237         LOW_INT_CLEAR_2,
 238         LOW_INT_CLEAR_3,
 239         LOW_INT_CLEAR_4,
 240         LOW_INT_CLEAR_5,
 241         LOW_INT_CLEAR_6,
 242         LOW_INT_CLEAR_7,
 243         LOW_INT_CLEAR_8,
 244         LOW_INT_CLEAR_9,
 245         LOW_INT_CLEAR_10,
 246         LOW_INT_CLEAR_11,
 247         LOW_INT_CLEAR_12,
 248         LOW_INT_CLEAR_13,
 249         LOW_INT_CLEAR_14,
 250         LOW_INT_CLEAR_15,
 251         LOW_INT_MASK_0, /* LOWER interrupt mask */
 252         LOW_INT_MASK_1,
 253         LOW_INT_MASK_2,
 254         LOW_INT_MASK_3,
 255         LOW_INT_MASK_4,
 256         LOW_INT_MASK_5,
 257         LOW_INT_MASK_6,
 258         LOW_INT_MASK_7,
 259         LOW_INT_MASK_8,
 260         LOW_INT_MASK_9,
 261         LOW_INT_MASK_10,
 262         LOW_INT_MASK_11,
 263         LOW_INT_MASK_12,
 264         LOW_INT_MASK_13,
 265         LOW_INT_MASK_14,
 266         LOW_INT_MASK_15,
 267         LOW_THRESH_0,           /* LOWER threshold values */
 268         LOW_THRESH_1,
 269         LOW_THRESH_2,
 270         LOW_THRESH_3,
 271         LOW_THRESH_4,
 272         LOW_THRESH_5,
 273         LOW_THRESH_6,
 274         LOW_THRESH_7,
 275         LOW_THRESH_8,
 276         LOW_THRESH_9,
 277         LOW_THRESH_10,
 278         LOW_THRESH_11,
 279         LOW_THRESH_12,
 280         LOW_THRESH_13,
 281         LOW_THRESH_14,
 282         LOW_THRESH_15,
 283         UPPER_STATUS_0, /* UPPER threshold violated */
 284         UPPER_STATUS_1,
 285         UPPER_STATUS_2,
 286         UPPER_STATUS_3,
 287         UPPER_STATUS_4,
 288         UPPER_STATUS_5,
 289         UPPER_STATUS_6,
 290         UPPER_STATUS_7,
 291         UPPER_STATUS_8,
 292         UPPER_STATUS_9,
 293         UPPER_STATUS_10,
 294         UPPER_STATUS_11,
 295         UPPER_STATUS_12,
 296         UPPER_STATUS_13,
 297         UPPER_STATUS_14,
 298         UPPER_STATUS_15,
 299         UP_INT_STATUS_0,        /* UPPER interrupt status */
 300         UP_INT_STATUS_1,
 301         UP_INT_STATUS_2,
 302         UP_INT_STATUS_3,
 303         UP_INT_STATUS_4,
 304         UP_INT_STATUS_5,
 305         UP_INT_STATUS_6,
 306         UP_INT_STATUS_7,
 307         UP_INT_STATUS_8,
 308         UP_INT_STATUS_9,
 309         UP_INT_STATUS_10,
 310         UP_INT_STATUS_11,
 311         UP_INT_STATUS_12,
 312         UP_INT_STATUS_13,
 313         UP_INT_STATUS_14,
 314         UP_INT_STATUS_15,
 315         UP_INT_CLEAR_0, /* UPPER interrupt clear */
 316         UP_INT_CLEAR_1,
 317         UP_INT_CLEAR_2,
 318         UP_INT_CLEAR_3,
 319         UP_INT_CLEAR_4,
 320         UP_INT_CLEAR_5,
 321         UP_INT_CLEAR_6,
 322         UP_INT_CLEAR_7,
 323         UP_INT_CLEAR_8,
 324         UP_INT_CLEAR_9,
 325         UP_INT_CLEAR_10,
 326         UP_INT_CLEAR_11,
 327         UP_INT_CLEAR_12,
 328         UP_INT_CLEAR_13,
 329         UP_INT_CLEAR_14,
 330         UP_INT_CLEAR_15,
 331         UP_INT_MASK_0,          /* UPPER interrupt mask */
 332         UP_INT_MASK_1,
 333         UP_INT_MASK_2,
 334         UP_INT_MASK_3,
 335         UP_INT_MASK_4,
 336         UP_INT_MASK_5,
 337         UP_INT_MASK_6,
 338         UP_INT_MASK_7,
 339         UP_INT_MASK_8,
 340         UP_INT_MASK_9,
 341         UP_INT_MASK_10,
 342         UP_INT_MASK_11,
 343         UP_INT_MASK_12,
 344         UP_INT_MASK_13,
 345         UP_INT_MASK_14,
 346         UP_INT_MASK_15,
 347         UP_THRESH_0,            /* UPPER threshold values */
 348         UP_THRESH_1,
 349         UP_THRESH_2,
 350         UP_THRESH_3,
 351         UP_THRESH_4,
 352         UP_THRESH_5,
 353         UP_THRESH_6,
 354         UP_THRESH_7,
 355         UP_THRESH_8,
 356         UP_THRESH_9,
 357         UP_THRESH_10,
 358         UP_THRESH_11,
 359         UP_THRESH_12,
 360         UP_THRESH_13,
 361         UP_THRESH_14,
 362         UP_THRESH_15,
 363         CRITICAL_STATUS_0,      /* CRITICAL threshold violated */
 364         CRITICAL_STATUS_1,
 365         CRITICAL_STATUS_2,
 366         CRITICAL_STATUS_3,
 367         CRITICAL_STATUS_4,
 368         CRITICAL_STATUS_5,
 369         CRITICAL_STATUS_6,
 370         CRITICAL_STATUS_7,
 371         CRITICAL_STATUS_8,
 372         CRITICAL_STATUS_9,
 373         CRITICAL_STATUS_10,
 374         CRITICAL_STATUS_11,
 375         CRITICAL_STATUS_12,
 376         CRITICAL_STATUS_13,
 377         CRITICAL_STATUS_14,
 378         CRITICAL_STATUS_15,
 379         CRIT_INT_STATUS_0,      /* CRITICAL interrupt status */
 380         CRIT_INT_STATUS_1,
 381         CRIT_INT_STATUS_2,
 382         CRIT_INT_STATUS_3,
 383         CRIT_INT_STATUS_4,
 384         CRIT_INT_STATUS_5,
 385         CRIT_INT_STATUS_6,
 386         CRIT_INT_STATUS_7,
 387         CRIT_INT_STATUS_8,
 388         CRIT_INT_STATUS_9,
 389         CRIT_INT_STATUS_10,
 390         CRIT_INT_STATUS_11,
 391         CRIT_INT_STATUS_12,
 392         CRIT_INT_STATUS_13,
 393         CRIT_INT_STATUS_14,
 394         CRIT_INT_STATUS_15,
 395         CRIT_INT_CLEAR_0,       /* CRITICAL interrupt clear */
 396         CRIT_INT_CLEAR_1,
 397         CRIT_INT_CLEAR_2,
 398         CRIT_INT_CLEAR_3,
 399         CRIT_INT_CLEAR_4,
 400         CRIT_INT_CLEAR_5,
 401         CRIT_INT_CLEAR_6,
 402         CRIT_INT_CLEAR_7,
 403         CRIT_INT_CLEAR_8,
 404         CRIT_INT_CLEAR_9,
 405         CRIT_INT_CLEAR_10,
 406         CRIT_INT_CLEAR_11,
 407         CRIT_INT_CLEAR_12,
 408         CRIT_INT_CLEAR_13,
 409         CRIT_INT_CLEAR_14,
 410         CRIT_INT_CLEAR_15,
 411         CRIT_INT_MASK_0,        /* CRITICAL interrupt mask */
 412         CRIT_INT_MASK_1,
 413         CRIT_INT_MASK_2,
 414         CRIT_INT_MASK_3,
 415         CRIT_INT_MASK_4,
 416         CRIT_INT_MASK_5,
 417         CRIT_INT_MASK_6,
 418         CRIT_INT_MASK_7,
 419         CRIT_INT_MASK_8,
 420         CRIT_INT_MASK_9,
 421         CRIT_INT_MASK_10,
 422         CRIT_INT_MASK_11,
 423         CRIT_INT_MASK_12,
 424         CRIT_INT_MASK_13,
 425         CRIT_INT_MASK_14,
 426         CRIT_INT_MASK_15,
 427         CRIT_THRESH_0,          /* CRITICAL threshold values */
 428         CRIT_THRESH_1,
 429         CRIT_THRESH_2,
 430         CRIT_THRESH_3,
 431         CRIT_THRESH_4,
 432         CRIT_THRESH_5,
 433         CRIT_THRESH_6,
 434         CRIT_THRESH_7,
 435         CRIT_THRESH_8,
 436         CRIT_THRESH_9,
 437         CRIT_THRESH_10,
 438         CRIT_THRESH_11,
 439         CRIT_THRESH_12,
 440         CRIT_THRESH_13,
 441         CRIT_THRESH_14,
 442         CRIT_THRESH_15,
 443
 444         /* WATCHDOG */
 445         WDOG_BARK_STATUS,
 446         WDOG_BARK_CLEAR,
 447         WDOG_BARK_MASK,
 448         WDOG_BARK_COUNT,
 449
 450         /* CYCLE COMPLETION MONITOR */
 451         CC_MON_STATUS,
 452         CC_MON_CLEAR,
 453         CC_MON_MASK,
 454
 455         MIN_STATUS_0,           /* MIN threshold violated */
 456         MIN_STATUS_1,
 457         MIN_STATUS_2,
 458         MIN_STATUS_3,
 459         MIN_STATUS_4,
 460         MIN_STATUS_5,
 461         MIN_STATUS_6,
 462         MIN_STATUS_7,
 463         MIN_STATUS_8,
 464         MIN_STATUS_9,
 465         MIN_STATUS_10,
 466         MIN_STATUS_11,
 467         MIN_STATUS_12,
 468         MIN_STATUS_13,
 469         MIN_STATUS_14,
 470         MIN_STATUS_15,
 471         MAX_STATUS_0,           /* MAX threshold violated */
 472         MAX_STATUS_1,
 473         MAX_STATUS_2,
 474         MAX_STATUS_3,
 475         MAX_STATUS_4,
 476         MAX_STATUS_5,
 477         MAX_STATUS_6,
 478         MAX_STATUS_7,
 479         MAX_STATUS_8,
 480         MAX_STATUS_9,
 481         MAX_STATUS_10,
 482         MAX_STATUS_11,
 483         MAX_STATUS_12,
 484         MAX_STATUS_13,
 485         MAX_STATUS_14,
 486         MAX_STATUS_15,
 487
 488         /* Keep last */
 489         MAX_REGFIELDS
 490 };
 491
 492 /**
 493  * struct tsens_features - Features supported by the IP
 494  * @ver_major: Major number of IP version
 495  * @crit_int: does the IP support critical interrupts?
 496  * @adc:      do the sensors only output adc code (instead of temperature)?
 497  * @srot_split: does the IP neatly splits the register space into SROT and TM,
 498  *              with SROT only being available to secure boot firmware?
 499  * @has_watchdog: does this IP support watchdog functionality?
 500  * @max_sensors: maximum sensors supported by this version of the IP
 501  */
 502 struct tsens_features {
 503         unsigned int ver_major;
 504         unsigned int crit_int:1;
 505         unsigned int adc:1;
 506         unsigned int srot_split:1;
 507         unsigned int has_watchdog:1;
 508         unsigned int max_sensors;
 509 };
 510
 511 /**
 512  * struct tsens_plat_data - tsens compile-time platform data
 513  * @num_sensors: Number of sensors supported by platform
 514  * @ops: operations the tsens instance supports
 515  * @hw_ids: Subset of sensors ids supported by platform, if not the first n
 516  * @feat: features of the IP
 517  * @fields: bitfield locations
 518  */
 519 struct tsens_plat_data {
 520         const u32               num_sensors;
 521         const struct tsens_ops  *ops;
 522         unsigned int            *hw_ids;
 523         struct tsens_features   *feat;
 524         const struct reg_field          *fields;
 525 };
 526
 527 /**
 528  * struct tsens_context - Registers to be saved/restored across a context loss
 529  * @threshold: Threshold register value
 530  * @control: Control register value
 531  */
 532 struct tsens_context {
 533         int     threshold;
 534         int     control;
 535 };
 536
 537 /**
 538  * struct tsens_priv - private data for each instance of the tsens IP
 539  * @dev: pointer to struct device
 540  * @num_sensors: number of sensors enabled on this device
 541  * @tm_map: pointer to TM register address space
 542  * @srot_map: pointer to SROT register address space
 543  * @tm_offset: deal with old device trees that don't address TM and SROT
 544  *             address space separately
 545  * @ul_lock: lock while processing upper/lower threshold interrupts
 546  * @crit_lock: lock while processing critical threshold interrupts
 547  * @rf: array of regmap_fields used to store value of the field
 548  * @ctx: registers to be saved and restored during suspend/resume
 549  * @feat: features of the IP
 550  * @fields: bitfield locations
 551  * @ops: pointer to list of callbacks supported by this device
 552  * @debug_root: pointer to debugfs dentry for all tsens
 553  * @debug: pointer to debugfs dentry for tsens controller
 554  * @sensor: list of sensors attached to this device
 555  */
 556 struct tsens_priv {
 557         struct device                   *dev;
 558         u32                             num_sensors;
 559         struct regmap                   *tm_map;
 560         struct regmap                   *srot_map;
 561         u32                             tm_offset;
 562
 563         /* lock for upper/lower threshold interrupts */
 564         spinlock_t                      ul_lock;
 565
 566         struct regmap_field             *rf[MAX_REGFIELDS];
 567         struct tsens_context            ctx;
 568         struct tsens_features           *feat;
 569         const struct reg_field          *fields;
 570         const struct tsens_ops          *ops;
 571
 572         struct dentry                   *debug_root;
 573         struct dentry                   *debug;
 574
 575         struct tsens_sensor             sensor[];
 576 };
 577
 578 char *qfprom_read(struct device *dev, const char *cname);
 579 void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode);
 580 int init_common(struct tsens_priv *priv);
 581 int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp);
 582 int get_temp_common(const struct tsens_sensor *s, int *temp);
 583 int tsens_enable_irq(struct tsens_priv *priv);
 584 void tsens_disable_irq(struct tsens_priv *priv);
 585 int tsens_set_trips(void *_sensor, int low, int high);
 586 irqreturn_t tsens_irq_thread(int irq, void *data);
 587 irqreturn_t tsens_critical_irq_thread(int irq, void *data);
 588
 589 /* TSENS target */
 590 extern struct tsens_plat_data data_8960;
 591
 592 /* TSENS v0.1 targets */
 593 extern struct tsens_plat_data data_8916, data_8974;
 594
 595 /* TSENS v1 targets */
 596 extern struct tsens_plat_data data_tsens_v1, data_8976;
 597
 598 /* TSENS v2 targets */
 599 extern struct tsens_plat_data data_8996, data_tsens_v2;
 600
 601 #endif /* __QCOM_TSENS_H__ */