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isci: fix oem parameter validation on single controller skus
[linux/fpc-iii.git] / drivers / mmc / host / at91_mci.c
blob947faa5d2ce4ebb243f049bca62430541c286efa
1 /*
2 * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver
3 *
4 * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
5 *
6 * Copyright (C) 2006 Malcolm Noyes
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 /*
14 This is the AT91 MCI driver that has been tested with both MMC cards
15 and SD-cards. Boards that support write protect are now supported.
16 The CCAT91SBC001 board does not support SD cards.
17
18 The three entry points are at91_mci_request, at91_mci_set_ios
19 and at91_mci_get_ro.
20
21 SET IOS
22 This configures the device to put it into the correct mode and clock speed
23 required.
24
25 MCI REQUEST
26 MCI request processes the commands sent in the mmc_request structure. This
27 can consist of a processing command and a stop command in the case of
28 multiple block transfers.
29
30 There are three main types of request, commands, reads and writes.
31
32 Commands are straight forward. The command is submitted to the controller and
33 the request function returns. When the controller generates an interrupt to indicate
34 the command is finished, the response to the command are read and the mmc_request_done
35 function called to end the request.
36
37 Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
38 controller to manage the transfers.
39
40 A read is done from the controller directly to the scatterlist passed in from the request.
41 Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte
42 swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug.
43
44 The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
45
46 A write is slightly different in that the bytes to write are read from the scatterlist
47 into a dma memory buffer (this is in case the source buffer should be read only). The
48 entire write buffer is then done from this single dma memory buffer.
49
50 The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
51
52 GET RO
53 Gets the status of the write protect pin, if available.
54 */
55
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/init.h>
59 #include <linux/ioport.h>
60 #include <linux/platform_device.h>
61 #include <linux/interrupt.h>
62 #include <linux/blkdev.h>
63 #include <linux/delay.h>
64 #include <linux/err.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/clk.h>
67 #include <linux/atmel_pdc.h>
68 #include <linux/gfp.h>
69 #include <linux/highmem.h>
70
71 #include <linux/mmc/host.h>
72 #include <linux/mmc/sdio.h>
73
74 #include <asm/io.h>
75 #include <asm/irq.h>
76 #include <asm/gpio.h>
77
78 #include <mach/board.h>
79 #include <mach/cpu.h>
80
81 #include "at91_mci.h"
82
83 #define DRIVER_NAME "at91_mci"
84
85 static inline int at91mci_is_mci1rev2xx(void)
86 {
87 return ( cpu_is_at91sam9260()
88 || cpu_is_at91sam9263()
89 || cpu_is_at91cap9()
90 || cpu_is_at91sam9rl()
91 || cpu_is_at91sam9g10()
92 || cpu_is_at91sam9g20()
93 );
94 }
95
96 #define FL_SENT_COMMAND (1 << 0)
97 #define FL_SENT_STOP (1 << 1)
98
99 #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
100 | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
101 | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
102
103 #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg))
104 #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg))
105
106 #define MCI_BLKSIZE 512
107 #define MCI_MAXBLKSIZE 4095
108 #define MCI_BLKATONCE 256
109 #define MCI_BUFSIZE (MCI_BLKSIZE * MCI_BLKATONCE)
110
111 /*
112 * Low level type for this driver
113 */
114 struct at91mci_host
115 {
116 struct mmc_host *mmc;
117 struct mmc_command *cmd;
118 struct mmc_request *request;
119
120 void __iomem *baseaddr;
121 int irq;
122
123 struct at91_mmc_data *board;
124 int present;
125
126 struct clk *mci_clk;
127
128 /*
129 * Flag indicating when the command has been sent. This is used to
130 * work out whether or not to send the stop
131 */
132 unsigned int flags;
133 /* flag for current bus settings */
134 u32 bus_mode;
135
136 /* DMA buffer used for transmitting */
137 unsigned int* buffer;
138 dma_addr_t physical_address;
139 unsigned int total_length;
140
141 /* Latest in the scatterlist that has been enabled for transfer, but not freed */
142 int in_use_index;
143
144 /* Latest in the scatterlist that has been enabled for transfer */
145 int transfer_index;
146
147 /* Timer for timeouts */
148 struct timer_list timer;
149 };
150
151 /*
152 * Reset the controller and restore most of the state
153 */
154 static void at91_reset_host(struct at91mci_host *host)
155 {
156 unsigned long flags;
157 u32 mr;
158 u32 sdcr;
159 u32 dtor;
160 u32 imr;
161
162 local_irq_save(flags);
163 imr = at91_mci_read(host, AT91_MCI_IMR);
164
165 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
166
167 /* save current state */
168 mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff;
169 sdcr = at91_mci_read(host, AT91_MCI_SDCR);
170 dtor = at91_mci_read(host, AT91_MCI_DTOR);
171
172 /* reset the controller */
173 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
174
175 /* restore state */
176 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
177 at91_mci_write(host, AT91_MCI_MR, mr);
178 at91_mci_write(host, AT91_MCI_SDCR, sdcr);
179 at91_mci_write(host, AT91_MCI_DTOR, dtor);
180 at91_mci_write(host, AT91_MCI_IER, imr);
181
182 /* make sure sdio interrupts will fire */
183 at91_mci_read(host, AT91_MCI_SR);
184
185 local_irq_restore(flags);
186 }
187
188 static void at91_timeout_timer(unsigned long data)
189 {
190 struct at91mci_host *host;
191
192 host = (struct at91mci_host *)data;
193
194 if (host->request) {
195 dev_err(host->mmc->parent, "Timeout waiting end of packet\n");
196
197 if (host->cmd && host->cmd->data) {
198 host->cmd->data->error = -ETIMEDOUT;
199 } else {
200 if (host->cmd)
201 host->cmd->error = -ETIMEDOUT;
202 else
203 host->request->cmd->error = -ETIMEDOUT;
204 }
205
206 at91_reset_host(host);
207 mmc_request_done(host->mmc, host->request);
208 }
209 }
210
211 /*
212 * Copy from sg to a dma block - used for transfers
213 */
214 static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
215 {
216 unsigned int len, i, size;
217 unsigned *dmabuf = host->buffer;
218
219 size = data->blksz * data->blocks;
220 len = data->sg_len;
221
222 /* MCI1 rev2xx Data Write Operation and number of bytes erratum */
223 if (at91mci_is_mci1rev2xx())
224 if (host->total_length == 12)
225 memset(dmabuf, 0, 12);
226
227 /*
228 * Just loop through all entries. Size might not
229 * be the entire list though so make sure that
230 * we do not transfer too much.
231 */
232 for (i = 0; i < len; i++) {
233 struct scatterlist *sg;
234 int amount;
235 unsigned int *sgbuffer;
236
237 sg = &data->sg[i];
238
239 sgbuffer = kmap_atomic(sg_page(sg)) + sg->offset;
240 amount = min(size, sg->length);
241 size -= amount;
242
243 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
244 int index;
245
246 for (index = 0; index < (amount / 4); index++)
247 *dmabuf++ = swab32(sgbuffer[index]);
248 } else {
249 char *tmpv = (char *)dmabuf;
250 memcpy(tmpv, sgbuffer, amount);
251 tmpv += amount;
252 dmabuf = (unsigned *)tmpv;
253 }
254
255 kunmap_atomic(sgbuffer);
256
257 if (size == 0)
258 break;
259 }
260
261 /*
262 * Check that we didn't get a request to transfer
263 * more data than can fit into the SG list.
264 */
265 BUG_ON(size != 0);
266 }
267
268 /*
269 * Handle after a dma read
270 */
271 static void at91_mci_post_dma_read(struct at91mci_host *host)
272 {
273 struct mmc_command *cmd;
274 struct mmc_data *data;
275 unsigned int len, i, size;
276 unsigned *dmabuf = host->buffer;
277
278 pr_debug("post dma read\n");
279
280 cmd = host->cmd;
281 if (!cmd) {
282 pr_debug("no command\n");
283 return;
284 }
285
286 data = cmd->data;
287 if (!data) {
288 pr_debug("no data\n");
289 return;
290 }
291
292 size = data->blksz * data->blocks;
293 len = data->sg_len;
294
295 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX);
296 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
297
298 for (i = 0; i < len; i++) {
299 struct scatterlist *sg;
300 int amount;
301 unsigned int *sgbuffer;
302
303 sg = &data->sg[i];
304
305 sgbuffer = kmap_atomic(sg_page(sg)) + sg->offset;
306 amount = min(size, sg->length);
307 size -= amount;
308
309 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
310 int index;
311 for (index = 0; index < (amount / 4); index++)
312 sgbuffer[index] = swab32(*dmabuf++);
313 } else {
314 char *tmpv = (char *)dmabuf;
315 memcpy(sgbuffer, tmpv, amount);
316 tmpv += amount;
317 dmabuf = (unsigned *)tmpv;
318 }
319
320 flush_kernel_dcache_page(sg_page(sg));
321 kunmap_atomic(sgbuffer);
322 data->bytes_xfered += amount;
323 if (size == 0)
324 break;
325 }
326
327 pr_debug("post dma read done\n");
328 }
329
330 /*
331 * Handle transmitted data
332 */
333 static void at91_mci_handle_transmitted(struct at91mci_host *host)
334 {
335 struct mmc_command *cmd;
336 struct mmc_data *data;
337
338 pr_debug("Handling the transmit\n");
339
340 /* Disable the transfer */
341 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
342
343 /* Now wait for cmd ready */
344 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
345
346 cmd = host->cmd;
347 if (!cmd) return;
348
349 data = cmd->data;
350 if (!data) return;
351
352 if (cmd->data->blocks > 1) {
353 pr_debug("multiple write : wait for BLKE...\n");
354 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE);
355 } else
356 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
357 }
358
359 /*
360 * Update bytes tranfered count during a write operation
361 */
362 static void at91_mci_update_bytes_xfered(struct at91mci_host *host)
363 {
364 struct mmc_data *data;
365
366 /* always deal with the effective request (and not the current cmd) */
367
368 if (host->request->cmd && host->request->cmd->error != 0)
369 return;
370
371 if (host->request->data) {
372 data = host->request->data;
373 if (data->flags & MMC_DATA_WRITE) {
374 /* card is in IDLE mode now */
375 pr_debug("-> bytes_xfered %d, total_length = %d\n",
376 data->bytes_xfered, host->total_length);
377 data->bytes_xfered = data->blksz * data->blocks;
378 }
379 }
380 }
381
382
383 /*Handle after command sent ready*/
384 static int at91_mci_handle_cmdrdy(struct at91mci_host *host)
385 {
386 if (!host->cmd)
387 return 1;
388 else if (!host->cmd->data) {
389 if (host->flags & FL_SENT_STOP) {
390 /*After multi block write, we must wait for NOTBUSY*/
391 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
392 } else return 1;
393 } else if (host->cmd->data->flags & MMC_DATA_WRITE) {
394 /*After sendding multi-block-write command, start DMA transfer*/
395 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE);
396 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
397 }
398
399 /* command not completed, have to wait */
400 return 0;
401 }
402
403
404 /*
405 * Enable the controller
406 */
407 static void at91_mci_enable(struct at91mci_host *host)
408 {
409 unsigned int mr;
410
411 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
412 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
413 at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
414 mr = AT91_MCI_PDCMODE | 0x34a;
415
416 if (at91mci_is_mci1rev2xx())
417 mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
418
419 at91_mci_write(host, AT91_MCI_MR, mr);
420
421 /* use Slot A or B (only one at same time) */
422 at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b);
423 }
424
425 /*
426 * Disable the controller
427 */
428 static void at91_mci_disable(struct at91mci_host *host)
429 {
430 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
431 }
432
433 /*
434 * Send a command
435 */
436 static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
437 {
438 unsigned int cmdr, mr;
439 unsigned int block_length;
440 struct mmc_data *data = cmd->data;
441
442 unsigned int blocks;
443 unsigned int ier = 0;
444
445 host->cmd = cmd;
446
447 /* Needed for leaving busy state before CMD1 */
448 if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
449 pr_debug("Clearing timeout\n");
450 at91_mci_write(host, AT91_MCI_ARGR, 0);
451 at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD);
452 while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
453 /* spin */
454 pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR));
455 }
456 }
457
458 cmdr = cmd->opcode;
459
460 if (mmc_resp_type(cmd) == MMC_RSP_NONE)
461 cmdr |= AT91_MCI_RSPTYP_NONE;
462 else {
463 /* if a response is expected then allow maximum response latancy */
464 cmdr |= AT91_MCI_MAXLAT;
465 /* set 136 bit response for R2, 48 bit response otherwise */
466 if (mmc_resp_type(cmd) == MMC_RSP_R2)
467 cmdr |= AT91_MCI_RSPTYP_136;
468 else
469 cmdr |= AT91_MCI_RSPTYP_48;
470 }
471
472 if (data) {
473
474 if (cpu_is_at91rm9200() || cpu_is_at91sam9261()) {
475 if (data->blksz & 0x3) {
476 pr_debug("Unsupported block size\n");
477 cmd->error = -EINVAL;
478 mmc_request_done(host->mmc, host->request);
479 return;
480 }
481 if (data->flags & MMC_DATA_STREAM) {
482 pr_debug("Stream commands not supported\n");
483 cmd->error = -EINVAL;
484 mmc_request_done(host->mmc, host->request);
485 return;
486 }
487 }
488
489 block_length = data->blksz;
490 blocks = data->blocks;
491
492 /* always set data start - also set direction flag for read */
493 if (data->flags & MMC_DATA_READ)
494 cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
495 else if (data->flags & MMC_DATA_WRITE)
496 cmdr |= AT91_MCI_TRCMD_START;
497
498 if (cmd->opcode == SD_IO_RW_EXTENDED) {
499 cmdr |= AT91_MCI_TRTYP_SDIO_BLOCK;
500 } else {
501 if (data->flags & MMC_DATA_STREAM)
502 cmdr |= AT91_MCI_TRTYP_STREAM;
503 if (data->blocks > 1)
504 cmdr |= AT91_MCI_TRTYP_MULTIPLE;
505 }
506 }
507 else {
508 block_length = 0;
509 blocks = 0;
510 }
511
512 if (host->flags & FL_SENT_STOP)
513 cmdr |= AT91_MCI_TRCMD_STOP;
514
515 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
516 cmdr |= AT91_MCI_OPDCMD;
517
518 /*
519 * Set the arguments and send the command
520 */
521 pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
522 cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR));
523
524 if (!data) {
525 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS);
526 at91_mci_write(host, ATMEL_PDC_RPR, 0);
527 at91_mci_write(host, ATMEL_PDC_RCR, 0);
528 at91_mci_write(host, ATMEL_PDC_RNPR, 0);
529 at91_mci_write(host, ATMEL_PDC_RNCR, 0);
530 at91_mci_write(host, ATMEL_PDC_TPR, 0);
531 at91_mci_write(host, ATMEL_PDC_TCR, 0);
532 at91_mci_write(host, ATMEL_PDC_TNPR, 0);
533 at91_mci_write(host, ATMEL_PDC_TNCR, 0);
534 ier = AT91_MCI_CMDRDY;
535 } else {
536 /* zero block length and PDC mode */
537 mr = at91_mci_read(host, AT91_MCI_MR) & 0x5fff;
538 mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0;
539 mr |= (block_length << 16);
540 mr |= AT91_MCI_PDCMODE;
541 at91_mci_write(host, AT91_MCI_MR, mr);
542
543 if (!(cpu_is_at91rm9200() || cpu_is_at91sam9261()))
544 at91_mci_write(host, AT91_MCI_BLKR,
545 AT91_MCI_BLKR_BCNT(blocks) |
546 AT91_MCI_BLKR_BLKLEN(block_length));
547
548 /*
549 * Disable the PDC controller
550 */
551 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
552
553 if (cmdr & AT91_MCI_TRCMD_START) {
554 data->bytes_xfered = 0;
555 host->transfer_index = 0;
556 host->in_use_index = 0;
557 if (cmdr & AT91_MCI_TRDIR) {
558 /*
559 * Handle a read
560 */
561 host->total_length = 0;
562
563 at91_mci_write(host, ATMEL_PDC_RPR, host->physical_address);
564 at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ?
565 (blocks * block_length) : (blocks * block_length) / 4);
566 at91_mci_write(host, ATMEL_PDC_RNPR, 0);
567 at91_mci_write(host, ATMEL_PDC_RNCR, 0);
568
569 ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
570 }
571 else {
572 /*
573 * Handle a write
574 */
575 host->total_length = block_length * blocks;
576 /*
577 * MCI1 rev2xx Data Write Operation and
578 * number of bytes erratum
579 */
580 if (at91mci_is_mci1rev2xx())
581 if (host->total_length < 12)
582 host->total_length = 12;
583
584 at91_mci_sg_to_dma(host, data);
585
586 pr_debug("Transmitting %d bytes\n", host->total_length);
587
588 at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address);
589 at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ?
590 host->total_length : host->total_length / 4);
591
592 ier = AT91_MCI_CMDRDY;
593 }
594 }
595 }
596
597 /*
598 * Send the command and then enable the PDC - not the other way round as
599 * the data sheet says
600 */
601
602 at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
603 at91_mci_write(host, AT91_MCI_CMDR, cmdr);
604
605 if (cmdr & AT91_MCI_TRCMD_START) {
606 if (cmdr & AT91_MCI_TRDIR)
607 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
608 }
609
610 /* Enable selected interrupts */
611 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier);
612 }
613
614 /*
615 * Process the next step in the request
616 */
617 static void at91_mci_process_next(struct at91mci_host *host)
618 {
619 if (!(host->flags & FL_SENT_COMMAND)) {
620 host->flags |= FL_SENT_COMMAND;
621 at91_mci_send_command(host, host->request->cmd);
622 }
623 else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
624 host->flags |= FL_SENT_STOP;
625 at91_mci_send_command(host, host->request->stop);
626 } else {
627 del_timer(&host->timer);
628 /* the at91rm9200 mci controller hangs after some transfers,
629 * and the workaround is to reset it after each transfer.
630 */
631 if (cpu_is_at91rm9200())
632 at91_reset_host(host);
633 mmc_request_done(host->mmc, host->request);
634 }
635 }
636
637 /*
638 * Handle a command that has been completed
639 */
640 static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status)
641 {
642 struct mmc_command *cmd = host->cmd;
643 struct mmc_data *data = cmd->data;
644
645 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
646
647 cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0));
648 cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1));
649 cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2));
650 cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3));
651
652 pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n",
653 status, at91_mci_read(host, AT91_MCI_SR),
654 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
655
656 if (status & AT91_MCI_ERRORS) {
657 if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) {
658 cmd->error = 0;
659 }
660 else {
661 if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) {
662 if (data) {
663 if (status & AT91_MCI_DTOE)
664 data->error = -ETIMEDOUT;
665 else if (status & AT91_MCI_DCRCE)
666 data->error = -EILSEQ;
667 }
668 } else {
669 if (status & AT91_MCI_RTOE)
670 cmd->error = -ETIMEDOUT;
671 else if (status & AT91_MCI_RCRCE)
672 cmd->error = -EILSEQ;
673 else
674 cmd->error = -EIO;
675 }
676
677 pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n",
678 cmd->error, data ? data->error : 0,
679 cmd->opcode, cmd->retries);
680 }
681 }
682 else
683 cmd->error = 0;
684
685 at91_mci_process_next(host);
686 }
687
688 /*
689 * Handle an MMC request
690 */
691 static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
692 {
693 struct at91mci_host *host = mmc_priv(mmc);
694 host->request = mrq;
695 host->flags = 0;
696
697 /* more than 1s timeout needed with slow SD cards */
698 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
699
700 at91_mci_process_next(host);
701 }
702
703 /*
704 * Set the IOS
705 */
706 static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
707 {
708 int clkdiv;
709 struct at91mci_host *host = mmc_priv(mmc);
710 unsigned long at91_master_clock = clk_get_rate(host->mci_clk);
711
712 host->bus_mode = ios->bus_mode;
713
714 if (ios->clock == 0) {
715 /* Disable the MCI controller */
716 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS);
717 clkdiv = 0;
718 }
719 else {
720 /* Enable the MCI controller */
721 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
722
723 if ((at91_master_clock % (ios->clock * 2)) == 0)
724 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
725 else
726 clkdiv = (at91_master_clock / ios->clock) / 2;
727
728 pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv,
729 at91_master_clock / (2 * (clkdiv + 1)));
730 }
731 if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
732 pr_debug("MMC: Setting controller bus width to 4\n");
733 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
734 }
735 else {
736 pr_debug("MMC: Setting controller bus width to 1\n");
737 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
738 }
739
740 /* Set the clock divider */
741 at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
742
743 /* maybe switch power to the card */
744 if (gpio_is_valid(host->board->vcc_pin)) {
745 switch (ios->power_mode) {
746 case MMC_POWER_OFF:
747 gpio_set_value(host->board->vcc_pin, 0);
748 break;
749 case MMC_POWER_UP:
750 gpio_set_value(host->board->vcc_pin, 1);
751 break;
752 case MMC_POWER_ON:
753 break;
754 default:
755 WARN_ON(1);
756 }
757 }
758 }
759
760 /*
761 * Handle an interrupt
762 */
763 static irqreturn_t at91_mci_irq(int irq, void *devid)
764 {
765 struct at91mci_host *host = devid;
766 int completed = 0;
767 unsigned int int_status, int_mask;
768
769 int_status = at91_mci_read(host, AT91_MCI_SR);
770 int_mask = at91_mci_read(host, AT91_MCI_IMR);
771
772 pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
773 int_status & int_mask);
774
775 int_status = int_status & int_mask;
776
777 if (int_status & AT91_MCI_ERRORS) {
778 completed = 1;
779
780 if (int_status & AT91_MCI_UNRE)
781 pr_debug("MMC: Underrun error\n");
782 if (int_status & AT91_MCI_OVRE)
783 pr_debug("MMC: Overrun error\n");
784 if (int_status & AT91_MCI_DTOE)
785 pr_debug("MMC: Data timeout\n");
786 if (int_status & AT91_MCI_DCRCE)
787 pr_debug("MMC: CRC error in data\n");
788 if (int_status & AT91_MCI_RTOE)
789 pr_debug("MMC: Response timeout\n");
790 if (int_status & AT91_MCI_RENDE)
791 pr_debug("MMC: Response end bit error\n");
792 if (int_status & AT91_MCI_RCRCE)
793 pr_debug("MMC: Response CRC error\n");
794 if (int_status & AT91_MCI_RDIRE)
795 pr_debug("MMC: Response direction error\n");
796 if (int_status & AT91_MCI_RINDE)
797 pr_debug("MMC: Response index error\n");
798 } else {
799 /* Only continue processing if no errors */
800
801 if (int_status & AT91_MCI_TXBUFE) {
802 pr_debug("TX buffer empty\n");
803 at91_mci_handle_transmitted(host);
804 }
805
806 if (int_status & AT91_MCI_ENDRX) {
807 pr_debug("ENDRX\n");
808 at91_mci_post_dma_read(host);
809 }
810
811 if (int_status & AT91_MCI_RXBUFF) {
812 pr_debug("RX buffer full\n");
813 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
814 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
815 completed = 1;
816 }
817
818 if (int_status & AT91_MCI_ENDTX)
819 pr_debug("Transmit has ended\n");
820
821 if (int_status & AT91_MCI_NOTBUSY) {
822 pr_debug("Card is ready\n");
823 at91_mci_update_bytes_xfered(host);
824 completed = 1;
825 }
826
827 if (int_status & AT91_MCI_DTIP)
828 pr_debug("Data transfer in progress\n");
829
830 if (int_status & AT91_MCI_BLKE) {
831 pr_debug("Block transfer has ended\n");
832 if (host->request->data && host->request->data->blocks > 1) {
833 /* multi block write : complete multi write
834 * command and send stop */
835 completed = 1;
836 } else {
837 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
838 }
839 }
840
841 if (int_status & AT91_MCI_SDIOIRQA)
842 mmc_signal_sdio_irq(host->mmc);
843
844 if (int_status & AT91_MCI_SDIOIRQB)
845 mmc_signal_sdio_irq(host->mmc);
846
847 if (int_status & AT91_MCI_TXRDY)
848 pr_debug("Ready to transmit\n");
849
850 if (int_status & AT91_MCI_RXRDY)
851 pr_debug("Ready to receive\n");
852
853 if (int_status & AT91_MCI_CMDRDY) {
854 pr_debug("Command ready\n");
855 completed = at91_mci_handle_cmdrdy(host);
856 }
857 }
858
859 if (completed) {
860 pr_debug("Completed command\n");
861 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
862 at91_mci_completed_command(host, int_status);
863 } else
864 at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
865
866 return IRQ_HANDLED;
867 }
868
869 static irqreturn_t at91_mmc_det_irq(int irq, void *_host)
870 {
871 struct at91mci_host *host = _host;
872 int present;
873
874 /* entering this ISR means that we have configured det_pin:
875 * we can use its value in board structure */
876 present = !gpio_get_value(host->board->det_pin);
877
878 /*
879 * we expect this irq on both insert and remove,
880 * and use a short delay to debounce.
881 */
882 if (present != host->present) {
883 host->present = present;
884 pr_debug("%s: card %s\n", mmc_hostname(host->mmc),
885 present ? "insert" : "remove");
886 if (!present) {
887 pr_debug("****** Resetting SD-card bus width ******\n");
888 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
889 }
890 /* 0.5s needed because of early card detect switch firing */
891 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
892 }
893 return IRQ_HANDLED;
894 }
895
896 static int at91_mci_get_ro(struct mmc_host *mmc)
897 {
898 struct at91mci_host *host = mmc_priv(mmc);
899
900 if (gpio_is_valid(host->board->wp_pin))
901 return !!gpio_get_value(host->board->wp_pin);
902 /*
903 * Board doesn't support read only detection; let the mmc core
904 * decide what to do.
905 */
906 return -ENOSYS;
907 }
908
909 static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable)
910 {
911 struct at91mci_host *host = mmc_priv(mmc);
912
913 pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc),
914 host->board->slot_b ? 'B':'A', enable ? "enable" : "disable");
915 at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR,
916 host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA);
917
918 }
919
920 static const struct mmc_host_ops at91_mci_ops = {
921 .request = at91_mci_request,
922 .set_ios = at91_mci_set_ios,
923 .get_ro = at91_mci_get_ro,
924 .enable_sdio_irq = at91_mci_enable_sdio_irq,
925 };
926
927 /*
928 * Probe for the device
929 */
930 static int __init at91_mci_probe(struct platform_device *pdev)
931 {
932 struct mmc_host *mmc;
933 struct at91mci_host *host;
934 struct resource *res;
935 int ret;
936
937 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
938 if (!res)
939 return -ENXIO;
940
941 if (!request_mem_region(res->start, resource_size(res), DRIVER_NAME))
942 return -EBUSY;
943
944 mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
945 if (!mmc) {
946 ret = -ENOMEM;
947 dev_dbg(&pdev->dev, "couldn't allocate mmc host\n");
948 goto fail6;
949 }
950
951 mmc->ops = &at91_mci_ops;
952 mmc->f_min = 375000;
953 mmc->f_max = 25000000;
954 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
955 mmc->caps = 0;
956
957 mmc->max_blk_size = MCI_MAXBLKSIZE;
958 mmc->max_blk_count = MCI_BLKATONCE;
959 mmc->max_req_size = MCI_BUFSIZE;
960 mmc->max_segs = MCI_BLKATONCE;
961 mmc->max_seg_size = MCI_BUFSIZE;
962
963 host = mmc_priv(mmc);
964 host->mmc = mmc;
965 host->bus_mode = 0;
966 host->board = pdev->dev.platform_data;
967 if (host->board->wire4) {
968 if (at91mci_is_mci1rev2xx())
969 mmc->caps |= MMC_CAP_4_BIT_DATA;
970 else
971 dev_warn(&pdev->dev, "4 wire bus mode not supported"
972 " - using 1 wire\n");
973 }
974
975 host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE,
976 &host->physical_address, GFP_KERNEL);
977 if (!host->buffer) {
978 ret = -ENOMEM;
979 dev_err(&pdev->dev, "Can't allocate transmit buffer\n");
980 goto fail5;
981 }
982
983 /* Add SDIO capability when available */
984 if (at91mci_is_mci1rev2xx()) {
985 /* at91mci MCI1 rev2xx sdio interrupt erratum */
986 if (host->board->wire4 || !host->board->slot_b)
987 mmc->caps |= MMC_CAP_SDIO_IRQ;
988 }
989
990 /*
991 * Reserve GPIOs ... board init code makes sure these pins are set
992 * up as GPIOs with the right direction (input, except for vcc)
993 */
994 if (gpio_is_valid(host->board->det_pin)) {
995 ret = gpio_request(host->board->det_pin, "mmc_detect");
996 if (ret < 0) {
997 dev_dbg(&pdev->dev, "couldn't claim card detect pin\n");
998 goto fail4b;
999 }
1000 }
1001 if (gpio_is_valid(host->board->wp_pin)) {
1002 ret = gpio_request(host->board->wp_pin, "mmc_wp");
1003 if (ret < 0) {
1004 dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n");
1005 goto fail4;
1006 }
1007 }
1008 if (gpio_is_valid(host->board->vcc_pin)) {
1009 ret = gpio_request(host->board->vcc_pin, "mmc_vcc");
1010 if (ret < 0) {
1011 dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n");
1012 goto fail3;
1013 }
1014 }
1015
1016 /*
1017 * Get Clock
1018 */
1019 host->mci_clk = clk_get(&pdev->dev, "mci_clk");
1020 if (IS_ERR(host->mci_clk)) {
1021 ret = -ENODEV;
1022 dev_dbg(&pdev->dev, "no mci_clk?\n");
1023 goto fail2;
1024 }
1025
1026 /*
1027 * Map I/O region
1028 */
1029 host->baseaddr = ioremap(res->start, resource_size(res));
1030 if (!host->baseaddr) {
1031 ret = -ENOMEM;
1032 goto fail1;
1033 }
1034
1035 /*
1036 * Reset hardware
1037 */
1038 clk_enable(host->mci_clk); /* Enable the peripheral clock */
1039 at91_mci_disable(host);
1040 at91_mci_enable(host);
1041
1042 /*
1043 * Allocate the MCI interrupt
1044 */
1045 host->irq = platform_get_irq(pdev, 0);
1046 ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED,
1047 mmc_hostname(mmc), host);
1048 if (ret) {
1049 dev_dbg(&pdev->dev, "request MCI interrupt failed\n");
1050 goto fail0;
1051 }
1052
1053 setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host);
1054
1055 platform_set_drvdata(pdev, mmc);
1056
1057 /*
1058 * Add host to MMC layer
1059 */
1060 if (gpio_is_valid(host->board->det_pin)) {
1061 host->present = !gpio_get_value(host->board->det_pin);
1062 }
1063 else
1064 host->present = -1;
1065
1066 mmc_add_host(mmc);
1067
1068 /*
1069 * monitor card insertion/removal if we can
1070 */
1071 if (gpio_is_valid(host->board->det_pin)) {
1072 ret = request_irq(gpio_to_irq(host->board->det_pin),
1073 at91_mmc_det_irq, 0, mmc_hostname(mmc), host);
1074 if (ret)
1075 dev_warn(&pdev->dev, "request MMC detect irq failed\n");
1076 else
1077 device_init_wakeup(&pdev->dev, 1);
1078 }
1079
1080 pr_debug("Added MCI driver\n");
1081
1082 return 0;
1083
1084 fail0:
1085 clk_disable(host->mci_clk);
1086 iounmap(host->baseaddr);
1087 fail1:
1088 clk_put(host->mci_clk);
1089 fail2:
1090 if (gpio_is_valid(host->board->vcc_pin))
1091 gpio_free(host->board->vcc_pin);
1092 fail3:
1093 if (gpio_is_valid(host->board->wp_pin))
1094 gpio_free(host->board->wp_pin);
1095 fail4:
1096 if (gpio_is_valid(host->board->det_pin))
1097 gpio_free(host->board->det_pin);
1098 fail4b:
1099 if (host->buffer)
1100 dma_free_coherent(&pdev->dev, MCI_BUFSIZE,
1101 host->buffer, host->physical_address);
1102 fail5:
1103 mmc_free_host(mmc);
1104 fail6:
1105 release_mem_region(res->start, resource_size(res));
1106 dev_err(&pdev->dev, "probe failed, err %d\n", ret);
1107 return ret;
1108 }
1109
1110 /*
1111 * Remove a device
1112 */
1113 static int __exit at91_mci_remove(struct platform_device *pdev)
1114 {
1115 struct mmc_host *mmc = platform_get_drvdata(pdev);
1116 struct at91mci_host *host;
1117 struct resource *res;
1118
1119 if (!mmc)
1120 return -1;
1121
1122 host = mmc_priv(mmc);
1123
1124 if (host->buffer)
1125 dma_free_coherent(&pdev->dev, MCI_BUFSIZE,
1126 host->buffer, host->physical_address);
1127
1128 if (gpio_is_valid(host->board->det_pin)) {
1129 if (device_can_wakeup(&pdev->dev))
1130 free_irq(gpio_to_irq(host->board->det_pin), host);
1131 device_init_wakeup(&pdev->dev, 0);
1132 gpio_free(host->board->det_pin);
1133 }
1134
1135 at91_mci_disable(host);
1136 del_timer_sync(&host->timer);
1137 mmc_remove_host(mmc);
1138 free_irq(host->irq, host);
1139
1140 clk_disable(host->mci_clk); /* Disable the peripheral clock */
1141 clk_put(host->mci_clk);
1142
1143 if (gpio_is_valid(host->board->vcc_pin))
1144 gpio_free(host->board->vcc_pin);
1145 if (gpio_is_valid(host->board->wp_pin))
1146 gpio_free(host->board->wp_pin);
1147
1148 iounmap(host->baseaddr);
1149 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1150 release_mem_region(res->start, resource_size(res));
1151
1152 mmc_free_host(mmc);
1153 platform_set_drvdata(pdev, NULL);
1154 pr_debug("MCI Removed\n");
1155
1156 return 0;
1157 }
1158
1159 #ifdef CONFIG_PM
1160 static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
1161 {
1162 struct mmc_host *mmc = platform_get_drvdata(pdev);
1163 struct at91mci_host *host = mmc_priv(mmc);
1164 int ret = 0;
1165
1166 if (gpio_is_valid(host->board->det_pin) && device_may_wakeup(&pdev->dev))
1167 enable_irq_wake(host->board->det_pin);
1168
1169 if (mmc)
1170 ret = mmc_suspend_host(mmc);
1171
1172 return ret;
1173 }
1174
1175 static int at91_mci_resume(struct platform_device *pdev)
1176 {
1177 struct mmc_host *mmc = platform_get_drvdata(pdev);
1178 struct at91mci_host *host = mmc_priv(mmc);
1179 int ret = 0;
1180
1181 if (gpio_is_valid(host->board->det_pin) && device_may_wakeup(&pdev->dev))
1182 disable_irq_wake(host->board->det_pin);
1183
1184 if (mmc)
1185 ret = mmc_resume_host(mmc);
1186
1187 return ret;
1188 }
1189 #else
1190 #define at91_mci_suspend NULL
1191 #define at91_mci_resume NULL
1192 #endif
1193
1194 static struct platform_driver at91_mci_driver = {
1195 .remove = __exit_p(at91_mci_remove),
1196 .suspend = at91_mci_suspend,
1197 .resume = at91_mci_resume,
1198 .driver = {
1199 .name = DRIVER_NAME,
1200 .owner = THIS_MODULE,
1201 },
1202 };
1203
1204 static int __init at91_mci_init(void)
1205 {
1206 return platform_driver_probe(&at91_mci_driver, at91_mci_probe);
1207 }
1208
1209 static void __exit at91_mci_exit(void)
1210 {
1211 platform_driver_unregister(&at91_mci_driver);
1212 }
1213
1214 module_init(at91_mci_init);
1215 module_exit(at91_mci_exit);
1216
1217 MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver");
1218 MODULE_AUTHOR("Nick Randell");
1219 MODULE_LICENSE("GPL");
1220 MODULE_ALIAS("platform:at91_mci");
Linux with added FPC-III support