?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'riscv-for-linus-4.15-rc2_cleanups' of git://git.kernel.org/pub/scm/linux...
[linux/fpc-iii.git] / drivers / crypto / s5p-sss.c
blob142c6020cec7e758762a98bc15bf80aa626bd939
1 /*
2 * Cryptographic API.
3 *
4 * Support for Samsung S5PV210 and Exynos HW acceleration.
5 *
6 * Copyright (C) 2011 NetUP Inc. All rights reserved.
7 * Copyright (c) 2017 Samsung Electronics Co., Ltd. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 * Hash part based on omap-sham.c driver.
14 */
15
16 #include <linux/clk.h>
17 #include <linux/crypto.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/platform_device.h>
28 #include <linux/scatterlist.h>
29
30 #include <crypto/ctr.h>
31 #include <crypto/aes.h>
32 #include <crypto/algapi.h>
33 #include <crypto/scatterwalk.h>
34
35 #include <crypto/hash.h>
36 #include <crypto/md5.h>
37 #include <crypto/sha.h>
38 #include <crypto/internal/hash.h>
39
40 #define _SBF(s, v) ((v) << (s))
41
42 /* Feed control registers */
43 #define SSS_REG_FCINTSTAT 0x0000
44 #define SSS_FCINTSTAT_HPARTINT BIT(7)
45 #define SSS_FCINTSTAT_HDONEINT BIT(5)
46 #define SSS_FCINTSTAT_BRDMAINT BIT(3)
47 #define SSS_FCINTSTAT_BTDMAINT BIT(2)
48 #define SSS_FCINTSTAT_HRDMAINT BIT(1)
49 #define SSS_FCINTSTAT_PKDMAINT BIT(0)
50
51 #define SSS_REG_FCINTENSET 0x0004
52 #define SSS_FCINTENSET_HPARTINTENSET BIT(7)
53 #define SSS_FCINTENSET_HDONEINTENSET BIT(5)
54 #define SSS_FCINTENSET_BRDMAINTENSET BIT(3)
55 #define SSS_FCINTENSET_BTDMAINTENSET BIT(2)
56 #define SSS_FCINTENSET_HRDMAINTENSET BIT(1)
57 #define SSS_FCINTENSET_PKDMAINTENSET BIT(0)
58
59 #define SSS_REG_FCINTENCLR 0x0008
60 #define SSS_FCINTENCLR_HPARTINTENCLR BIT(7)
61 #define SSS_FCINTENCLR_HDONEINTENCLR BIT(5)
62 #define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3)
63 #define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2)
64 #define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1)
65 #define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0)
66
67 #define SSS_REG_FCINTPEND 0x000C
68 #define SSS_FCINTPEND_HPARTINTP BIT(7)
69 #define SSS_FCINTPEND_HDONEINTP BIT(5)
70 #define SSS_FCINTPEND_BRDMAINTP BIT(3)
71 #define SSS_FCINTPEND_BTDMAINTP BIT(2)
72 #define SSS_FCINTPEND_HRDMAINTP BIT(1)
73 #define SSS_FCINTPEND_PKDMAINTP BIT(0)
74
75 #define SSS_REG_FCFIFOSTAT 0x0010
76 #define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7)
77 #define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6)
78 #define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5)
79 #define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4)
80 #define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3)
81 #define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2)
82 #define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1)
83 #define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0)
84
85 #define SSS_REG_FCFIFOCTRL 0x0014
86 #define SSS_FCFIFOCTRL_DESSEL BIT(2)
87 #define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00)
88 #define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01)
89 #define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02)
90 #define SSS_HASHIN_MASK _SBF(0, 0x03)
91
92 #define SSS_REG_FCBRDMAS 0x0020
93 #define SSS_REG_FCBRDMAL 0x0024
94 #define SSS_REG_FCBRDMAC 0x0028
95 #define SSS_FCBRDMAC_BYTESWAP BIT(1)
96 #define SSS_FCBRDMAC_FLUSH BIT(0)
97
98 #define SSS_REG_FCBTDMAS 0x0030
99 #define SSS_REG_FCBTDMAL 0x0034
100 #define SSS_REG_FCBTDMAC 0x0038
101 #define SSS_FCBTDMAC_BYTESWAP BIT(1)
102 #define SSS_FCBTDMAC_FLUSH BIT(0)
103
104 #define SSS_REG_FCHRDMAS 0x0040
105 #define SSS_REG_FCHRDMAL 0x0044
106 #define SSS_REG_FCHRDMAC 0x0048
107 #define SSS_FCHRDMAC_BYTESWAP BIT(1)
108 #define SSS_FCHRDMAC_FLUSH BIT(0)
109
110 #define SSS_REG_FCPKDMAS 0x0050
111 #define SSS_REG_FCPKDMAL 0x0054
112 #define SSS_REG_FCPKDMAC 0x0058
113 #define SSS_FCPKDMAC_BYTESWAP BIT(3)
114 #define SSS_FCPKDMAC_DESCEND BIT(2)
115 #define SSS_FCPKDMAC_TRANSMIT BIT(1)
116 #define SSS_FCPKDMAC_FLUSH BIT(0)
117
118 #define SSS_REG_FCPKDMAO 0x005C
119
120 /* AES registers */
121 #define SSS_REG_AES_CONTROL 0x00
122 #define SSS_AES_BYTESWAP_DI BIT(11)
123 #define SSS_AES_BYTESWAP_DO BIT(10)
124 #define SSS_AES_BYTESWAP_IV BIT(9)
125 #define SSS_AES_BYTESWAP_CNT BIT(8)
126 #define SSS_AES_BYTESWAP_KEY BIT(7)
127 #define SSS_AES_KEY_CHANGE_MODE BIT(6)
128 #define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00)
129 #define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01)
130 #define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02)
131 #define SSS_AES_FIFO_MODE BIT(3)
132 #define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00)
133 #define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01)
134 #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
135 #define SSS_AES_MODE_DECRYPT BIT(0)
136
137 #define SSS_REG_AES_STATUS 0x04
138 #define SSS_AES_BUSY BIT(2)
139 #define SSS_AES_INPUT_READY BIT(1)
140 #define SSS_AES_OUTPUT_READY BIT(0)
141
142 #define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2))
143 #define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2))
144 #define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2))
145 #define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2))
146 #define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2))
147
148 #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
149 #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
150 #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
151
152 #define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg)
153 #define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
154 SSS_AES_REG(dev, reg))
155
156 /* HW engine modes */
157 #define FLAGS_AES_DECRYPT BIT(0)
158 #define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
159 #define FLAGS_AES_CBC _SBF(1, 0x01)
160 #define FLAGS_AES_CTR _SBF(1, 0x02)
161
162 #define AES_KEY_LEN 16
163 #define CRYPTO_QUEUE_LEN 1
164
165 /* HASH registers */
166 #define SSS_REG_HASH_CTRL 0x00
167
168 #define SSS_HASH_USER_IV_EN BIT(5)
169 #define SSS_HASH_INIT_BIT BIT(4)
170 #define SSS_HASH_ENGINE_SHA1 _SBF(1, 0x00)
171 #define SSS_HASH_ENGINE_MD5 _SBF(1, 0x01)
172 #define SSS_HASH_ENGINE_SHA256 _SBF(1, 0x02)
173
174 #define SSS_HASH_ENGINE_MASK _SBF(1, 0x03)
175
176 #define SSS_REG_HASH_CTRL_PAUSE 0x04
177
178 #define SSS_HASH_PAUSE BIT(0)
179
180 #define SSS_REG_HASH_CTRL_FIFO 0x08
181
182 #define SSS_HASH_FIFO_MODE_DMA BIT(0)
183 #define SSS_HASH_FIFO_MODE_CPU 0
184
185 #define SSS_REG_HASH_CTRL_SWAP 0x0C
186
187 #define SSS_HASH_BYTESWAP_DI BIT(3)
188 #define SSS_HASH_BYTESWAP_DO BIT(2)
189 #define SSS_HASH_BYTESWAP_IV BIT(1)
190 #define SSS_HASH_BYTESWAP_KEY BIT(0)
191
192 #define SSS_REG_HASH_STATUS 0x10
193
194 #define SSS_HASH_STATUS_MSG_DONE BIT(6)
195 #define SSS_HASH_STATUS_PARTIAL_DONE BIT(4)
196 #define SSS_HASH_STATUS_BUFFER_READY BIT(0)
197
198 #define SSS_REG_HASH_MSG_SIZE_LOW 0x20
199 #define SSS_REG_HASH_MSG_SIZE_HIGH 0x24
200
201 #define SSS_REG_HASH_PRE_MSG_SIZE_LOW 0x28
202 #define SSS_REG_HASH_PRE_MSG_SIZE_HIGH 0x2C
203
204 #define SSS_REG_HASH_IV(s) (0xB0 + ((s) << 2))
205 #define SSS_REG_HASH_OUT(s) (0x100 + ((s) << 2))
206
207 #define HASH_BLOCK_SIZE 64
208 #define HASH_REG_SIZEOF 4
209 #define HASH_MD5_MAX_REG (MD5_DIGEST_SIZE / HASH_REG_SIZEOF)
210 #define HASH_SHA1_MAX_REG (SHA1_DIGEST_SIZE / HASH_REG_SIZEOF)
211 #define HASH_SHA256_MAX_REG (SHA256_DIGEST_SIZE / HASH_REG_SIZEOF)
212
213 /*
214 * HASH bit numbers, used by device, setting in dev->hash_flags with
215 * functions set_bit(), clear_bit() or tested with test_bit() or BIT(),
216 * to keep HASH state BUSY or FREE, or to signal state from irq_handler
217 * to hash_tasklet. SGS keep track of allocated memory for scatterlist
218 */
219 #define HASH_FLAGS_BUSY 0
220 #define HASH_FLAGS_FINAL 1
221 #define HASH_FLAGS_DMA_ACTIVE 2
222 #define HASH_FLAGS_OUTPUT_READY 3
223 #define HASH_FLAGS_DMA_READY 4
224 #define HASH_FLAGS_SGS_COPIED 5
225 #define HASH_FLAGS_SGS_ALLOCED 6
226
227 /* HASH HW constants */
228 #define BUFLEN HASH_BLOCK_SIZE
229
230 #define SSS_HASH_DMA_LEN_ALIGN 8
231 #define SSS_HASH_DMA_ALIGN_MASK (SSS_HASH_DMA_LEN_ALIGN - 1)
232
233 #define SSS_HASH_QUEUE_LENGTH 10
234
235 /**
236 * struct samsung_aes_variant - platform specific SSS driver data
237 * @aes_offset: AES register offset from SSS module's base.
238 * @hash_offset: HASH register offset from SSS module's base.
239 *
240 * Specifies platform specific configuration of SSS module.
241 * Note: A structure for driver specific platform data is used for future
242 * expansion of its usage.
243 */
244 struct samsung_aes_variant {
245 unsigned int aes_offset;
246 unsigned int hash_offset;
247 };
248
249 struct s5p_aes_reqctx {
250 unsigned long mode;
251 };
252
253 struct s5p_aes_ctx {
254 struct s5p_aes_dev *dev;
255
256 uint8_t aes_key[AES_MAX_KEY_SIZE];
257 uint8_t nonce[CTR_RFC3686_NONCE_SIZE];
258 int keylen;
259 };
260
261 /**
262 * struct s5p_aes_dev - Crypto device state container
263 * @dev: Associated device
264 * @clk: Clock for accessing hardware
265 * @ioaddr: Mapped IO memory region
266 * @aes_ioaddr: Per-varian offset for AES block IO memory
267 * @irq_fc: Feed control interrupt line
268 * @req: Crypto request currently handled by the device
269 * @ctx: Configuration for currently handled crypto request
270 * @sg_src: Scatter list with source data for currently handled block
271 * in device. This is DMA-mapped into device.
272 * @sg_dst: Scatter list with destination data for currently handled block
273 * in device. This is DMA-mapped into device.
274 * @sg_src_cpy: In case of unaligned access, copied scatter list
275 * with source data.
276 * @sg_dst_cpy: In case of unaligned access, copied scatter list
277 * with destination data.
278 * @tasklet: New request scheduling jib
279 * @queue: Crypto queue
280 * @busy: Indicates whether the device is currently handling some request
281 * thus it uses some of the fields from this state, like:
282 * req, ctx, sg_src/dst (and copies). This essentially
283 * protects against concurrent access to these fields.
284 * @lock: Lock for protecting both access to device hardware registers
285 * and fields related to current request (including the busy field).
286 * @res: Resources for hash.
287 * @io_hash_base: Per-variant offset for HASH block IO memory.
288 * @hash_lock: Lock for protecting hash_req, hash_queue and hash_flags
289 * variable.
290 * @hash_flags: Flags for current HASH op.
291 * @hash_queue: Async hash queue.
292 * @hash_tasklet: New HASH request scheduling job.
293 * @xmit_buf: Buffer for current HASH request transfer into SSS block.
294 * @hash_req: Current request sending to SSS HASH block.
295 * @hash_sg_iter: Scatterlist transferred through DMA into SSS HASH block.
296 * @hash_sg_cnt: Counter for hash_sg_iter.
297 *
298 * @use_hash: true if HASH algs enabled
299 */
300 struct s5p_aes_dev {
301 struct device *dev;
302 struct clk *clk;
303 void __iomem *ioaddr;
304 void __iomem *aes_ioaddr;
305 int irq_fc;
306
307 struct ablkcipher_request *req;
308 struct s5p_aes_ctx *ctx;
309 struct scatterlist *sg_src;
310 struct scatterlist *sg_dst;
311
312 struct scatterlist *sg_src_cpy;
313 struct scatterlist *sg_dst_cpy;
314
315 struct tasklet_struct tasklet;
316 struct crypto_queue queue;
317 bool busy;
318 spinlock_t lock;
319
320 struct resource *res;
321 void __iomem *io_hash_base;
322
323 spinlock_t hash_lock; /* protect hash_ vars */
324 unsigned long hash_flags;
325 struct crypto_queue hash_queue;
326 struct tasklet_struct hash_tasklet;
327
328 u8 xmit_buf[BUFLEN];
329 struct ahash_request *hash_req;
330 struct scatterlist *hash_sg_iter;
331 unsigned int hash_sg_cnt;
332
333 bool use_hash;
334 };
335
336 /**
337 * struct s5p_hash_reqctx - HASH request context
338 * @dd: Associated device
339 * @op_update: Current request operation (OP_UPDATE or OP_FINAL)
340 * @digcnt: Number of bytes processed by HW (without buffer[] ones)
341 * @digest: Digest message or IV for partial result
342 * @nregs: Number of HW registers for digest or IV read/write
343 * @engine: Bits for selecting type of HASH in SSS block
344 * @sg: sg for DMA transfer
345 * @sg_len: Length of sg for DMA transfer
346 * @sgl[]: sg for joining buffer and req->src scatterlist
347 * @skip: Skip offset in req->src for current op
348 * @total: Total number of bytes for current request
349 * @finup: Keep state for finup or final.
350 * @error: Keep track of error.
351 * @bufcnt: Number of bytes holded in buffer[]
352 * @buffer[]: For byte(s) from end of req->src in UPDATE op
353 */
354 struct s5p_hash_reqctx {
355 struct s5p_aes_dev *dd;
356 bool op_update;
357
358 u64 digcnt;
359 u8 digest[SHA256_DIGEST_SIZE];
360
361 unsigned int nregs; /* digest_size / sizeof(reg) */
362 u32 engine;
363
364 struct scatterlist *sg;
365 unsigned int sg_len;
366 struct scatterlist sgl[2];
367 unsigned int skip;
368 unsigned int total;
369 bool finup;
370 bool error;
371
372 u32 bufcnt;
373 u8 buffer[0];
374 };
375
376 /**
377 * struct s5p_hash_ctx - HASH transformation context
378 * @dd: Associated device
379 * @flags: Bits for algorithm HASH.
380 * @fallback: Software transformation for zero message or size < BUFLEN.
381 */
382 struct s5p_hash_ctx {
383 struct s5p_aes_dev *dd;
384 unsigned long flags;
385 struct crypto_shash *fallback;
386 };
387
388 static const struct samsung_aes_variant s5p_aes_data = {
389 .aes_offset = 0x4000,
390 .hash_offset = 0x6000,
391 };
392
393 static const struct samsung_aes_variant exynos_aes_data = {
394 .aes_offset = 0x200,
395 .hash_offset = 0x400,
396 };
397
398 static const struct of_device_id s5p_sss_dt_match[] = {
399 {
400 .compatible = "samsung,s5pv210-secss",
401 .data = &s5p_aes_data,
402 },
403 {
404 .compatible = "samsung,exynos4210-secss",
405 .data = &exynos_aes_data,
406 },
407 { },
408 };
409 MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
410
411 static inline struct samsung_aes_variant *find_s5p_sss_version
412 (struct platform_device *pdev)
413 {
414 if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
415 const struct of_device_id *match;
416
417 match = of_match_node(s5p_sss_dt_match,
418 pdev->dev.of_node);
419 return (struct samsung_aes_variant *)match->data;
420 }
421 return (struct samsung_aes_variant *)
422 platform_get_device_id(pdev)->driver_data;
423 }
424
425 static struct s5p_aes_dev *s5p_dev;
426
427 static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
428 {
429 SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
430 SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg));
431 }
432
433 static void s5p_set_dma_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg)
434 {
435 SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg));
436 SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg));
437 }
438
439 static void s5p_free_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist **sg)
440 {
441 int len;
442
443 if (!*sg)
444 return;
445
446 len = ALIGN(dev->req->nbytes, AES_BLOCK_SIZE);
447 free_pages((unsigned long)sg_virt(*sg), get_order(len));
448
449 kfree(*sg);
450 *sg = NULL;
451 }
452
453 static void s5p_sg_copy_buf(void *buf, struct scatterlist *sg,
454 unsigned int nbytes, int out)
455 {
456 struct scatter_walk walk;
457
458 if (!nbytes)
459 return;
460
461 scatterwalk_start(&walk, sg);
462 scatterwalk_copychunks(buf, &walk, nbytes, out);
463 scatterwalk_done(&walk, out, 0);
464 }
465
466 static void s5p_sg_done(struct s5p_aes_dev *dev)
467 {
468 if (dev->sg_dst_cpy) {
469 dev_dbg(dev->dev,
470 "Copying %d bytes of output data back to original place\n",
471 dev->req->nbytes);
472 s5p_sg_copy_buf(sg_virt(dev->sg_dst_cpy), dev->req->dst,
473 dev->req->nbytes, 1);
474 }
475 s5p_free_sg_cpy(dev, &dev->sg_src_cpy);
476 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy);
477 }
478
479 /* Calls the completion. Cannot be called with dev->lock hold. */
480 static void s5p_aes_complete(struct s5p_aes_dev *dev, int err)
481 {
482 dev->req->base.complete(&dev->req->base, err);
483 }
484
485 static void s5p_unset_outdata(struct s5p_aes_dev *dev)
486 {
487 dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE);
488 }
489
490 static void s5p_unset_indata(struct s5p_aes_dev *dev)
491 {
492 dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE);
493 }
494
495 static int s5p_make_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist *src,
496 struct scatterlist **dst)
497 {
498 void *pages;
499 int len;
500
501 *dst = kmalloc(sizeof(**dst), GFP_ATOMIC);
502 if (!*dst)
503 return -ENOMEM;
504
505 len = ALIGN(dev->req->nbytes, AES_BLOCK_SIZE);
506 pages = (void *)__get_free_pages(GFP_ATOMIC, get_order(len));
507 if (!pages) {
508 kfree(*dst);
509 *dst = NULL;
510 return -ENOMEM;
511 }
512
513 s5p_sg_copy_buf(pages, src, dev->req->nbytes, 0);
514
515 sg_init_table(*dst, 1);
516 sg_set_buf(*dst, pages, len);
517
518 return 0;
519 }
520
521 static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg)
522 {
523 int err;
524
525 if (!sg->length) {
526 err = -EINVAL;
527 goto exit;
528 }
529
530 err = dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE);
531 if (!err) {
532 err = -ENOMEM;
533 goto exit;
534 }
535
536 dev->sg_dst = sg;
537 err = 0;
538
539 exit:
540 return err;
541 }
542
543 static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
544 {
545 int err;
546
547 if (!sg->length) {
548 err = -EINVAL;
549 goto exit;
550 }
551
552 err = dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE);
553 if (!err) {
554 err = -ENOMEM;
555 goto exit;
556 }
557
558 dev->sg_src = sg;
559 err = 0;
560
561 exit:
562 return err;
563 }
564
565 /*
566 * Returns -ERRNO on error (mapping of new data failed).
567 * On success returns:
568 * - 0 if there is no more data,
569 * - 1 if new transmitting (output) data is ready and its address+length
570 * have to be written to device (by calling s5p_set_dma_outdata()).
571 */
572 static int s5p_aes_tx(struct s5p_aes_dev *dev)
573 {
574 int ret = 0;
575
576 s5p_unset_outdata(dev);
577
578 if (!sg_is_last(dev->sg_dst)) {
579 ret = s5p_set_outdata(dev, sg_next(dev->sg_dst));
580 if (!ret)
581 ret = 1;
582 }
583
584 return ret;
585 }
586
587 /*
588 * Returns -ERRNO on error (mapping of new data failed).
589 * On success returns:
590 * - 0 if there is no more data,
591 * - 1 if new receiving (input) data is ready and its address+length
592 * have to be written to device (by calling s5p_set_dma_indata()).
593 */
594 static int s5p_aes_rx(struct s5p_aes_dev *dev/*, bool *set_dma*/)
595 {
596 int ret = 0;
597
598 s5p_unset_indata(dev);
599
600 if (!sg_is_last(dev->sg_src)) {
601 ret = s5p_set_indata(dev, sg_next(dev->sg_src));
602 if (!ret)
603 ret = 1;
604 }
605
606 return ret;
607 }
608
609 static inline u32 s5p_hash_read(struct s5p_aes_dev *dd, u32 offset)
610 {
611 return __raw_readl(dd->io_hash_base + offset);
612 }
613
614 static inline void s5p_hash_write(struct s5p_aes_dev *dd,
615 u32 offset, u32 value)
616 {
617 __raw_writel(value, dd->io_hash_base + offset);
618 }
619
620 /**
621 * s5p_set_dma_hashdata() - start DMA with sg
622 * @dev: device
623 * @sg: scatterlist ready to DMA transmit
624 */
625 static void s5p_set_dma_hashdata(struct s5p_aes_dev *dev,
626 struct scatterlist *sg)
627 {
628 dev->hash_sg_cnt--;
629 SSS_WRITE(dev, FCHRDMAS, sg_dma_address(sg));
630 SSS_WRITE(dev, FCHRDMAL, sg_dma_len(sg)); /* DMA starts */
631 }
632
633 /**
634 * s5p_hash_rx() - get next hash_sg_iter
635 * @dev: device
636 *
637 * Return:
638 * 2 if there is no more data and it is UPDATE op
639 * 1 if new receiving (input) data is ready and can be written to device
640 * 0 if there is no more data and it is FINAL op
641 */
642 static int s5p_hash_rx(struct s5p_aes_dev *dev)
643 {
644 if (dev->hash_sg_cnt > 0) {
645 dev->hash_sg_iter = sg_next(dev->hash_sg_iter);
646 return 1;
647 }
648
649 set_bit(HASH_FLAGS_DMA_READY, &dev->hash_flags);
650 if (test_bit(HASH_FLAGS_FINAL, &dev->hash_flags))
651 return 0;
652
653 return 2;
654 }
655
656 static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id)
657 {
658 struct platform_device *pdev = dev_id;
659 struct s5p_aes_dev *dev = platform_get_drvdata(pdev);
660 int err_dma_tx = 0;
661 int err_dma_rx = 0;
662 int err_dma_hx = 0;
663 bool tx_end = false;
664 bool hx_end = false;
665 unsigned long flags;
666 uint32_t status;
667 u32 st_bits;
668 int err;
669
670 spin_lock_irqsave(&dev->lock, flags);
671
672 /*
673 * Handle rx or tx interrupt. If there is still data (scatterlist did not
674 * reach end), then map next scatterlist entry.
675 * In case of such mapping error, s5p_aes_complete() should be called.
676 *
677 * If there is no more data in tx scatter list, call s5p_aes_complete()
678 * and schedule new tasklet.
679 *
680 * Handle hx interrupt. If there is still data map next entry.
681 */
682 status = SSS_READ(dev, FCINTSTAT);
683 if (status & SSS_FCINTSTAT_BRDMAINT)
684 err_dma_rx = s5p_aes_rx(dev);
685
686 if (status & SSS_FCINTSTAT_BTDMAINT) {
687 if (sg_is_last(dev->sg_dst))
688 tx_end = true;
689 err_dma_tx = s5p_aes_tx(dev);
690 }
691
692 if (status & SSS_FCINTSTAT_HRDMAINT)
693 err_dma_hx = s5p_hash_rx(dev);
694
695 st_bits = status & (SSS_FCINTSTAT_BRDMAINT | SSS_FCINTSTAT_BTDMAINT |
696 SSS_FCINTSTAT_HRDMAINT);
697 /* clear DMA bits */
698 SSS_WRITE(dev, FCINTPEND, st_bits);
699
700 /* clear HASH irq bits */
701 if (status & (SSS_FCINTSTAT_HDONEINT | SSS_FCINTSTAT_HPARTINT)) {
702 /* cannot have both HPART and HDONE */
703 if (status & SSS_FCINTSTAT_HPARTINT)
704 st_bits = SSS_HASH_STATUS_PARTIAL_DONE;
705
706 if (status & SSS_FCINTSTAT_HDONEINT)
707 st_bits = SSS_HASH_STATUS_MSG_DONE;
708
709 set_bit(HASH_FLAGS_OUTPUT_READY, &dev->hash_flags);
710 s5p_hash_write(dev, SSS_REG_HASH_STATUS, st_bits);
711 hx_end = true;
712 /* when DONE or PART, do not handle HASH DMA */
713 err_dma_hx = 0;
714 }
715
716 if (err_dma_rx < 0) {
717 err = err_dma_rx;
718 goto error;
719 }
720 if (err_dma_tx < 0) {
721 err = err_dma_tx;
722 goto error;
723 }
724
725 if (tx_end) {
726 s5p_sg_done(dev);
727 if (err_dma_hx == 1)
728 s5p_set_dma_hashdata(dev, dev->hash_sg_iter);
729
730 spin_unlock_irqrestore(&dev->lock, flags);
731
732 s5p_aes_complete(dev, 0);
733 /* Device is still busy */
734 tasklet_schedule(&dev->tasklet);
735 } else {
736 /*
737 * Writing length of DMA block (either receiving or
738 * transmitting) will start the operation immediately, so this
739 * should be done at the end (even after clearing pending
740 * interrupts to not miss the interrupt).
741 */
742 if (err_dma_tx == 1)
743 s5p_set_dma_outdata(dev, dev->sg_dst);
744 if (err_dma_rx == 1)
745 s5p_set_dma_indata(dev, dev->sg_src);
746 if (err_dma_hx == 1)
747 s5p_set_dma_hashdata(dev, dev->hash_sg_iter);
748
749 spin_unlock_irqrestore(&dev->lock, flags);
750 }
751
752 goto hash_irq_end;
753
754 error:
755 s5p_sg_done(dev);
756 dev->busy = false;
757 if (err_dma_hx == 1)
758 s5p_set_dma_hashdata(dev, dev->hash_sg_iter);
759
760 spin_unlock_irqrestore(&dev->lock, flags);
761 s5p_aes_complete(dev, err);
762
763 hash_irq_end:
764 /*
765 * Note about else if:
766 * when hash_sg_iter reaches end and its UPDATE op,
767 * issue SSS_HASH_PAUSE and wait for HPART irq
768 */
769 if (hx_end)
770 tasklet_schedule(&dev->hash_tasklet);
771 else if (err_dma_hx == 2)
772 s5p_hash_write(dev, SSS_REG_HASH_CTRL_PAUSE,
773 SSS_HASH_PAUSE);
774
775 return IRQ_HANDLED;
776 }
777
778 /**
779 * s5p_hash_read_msg() - read message or IV from HW
780 * @req: AHASH request
781 */
782 static void s5p_hash_read_msg(struct ahash_request *req)
783 {
784 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
785 struct s5p_aes_dev *dd = ctx->dd;
786 u32 *hash = (u32 *)ctx->digest;
787 unsigned int i;
788
789 for (i = 0; i < ctx->nregs; i++)
790 hash[i] = s5p_hash_read(dd, SSS_REG_HASH_OUT(i));
791 }
792
793 /**
794 * s5p_hash_write_ctx_iv() - write IV for next partial/finup op.
795 * @dd: device
796 * @ctx: request context
797 */
798 static void s5p_hash_write_ctx_iv(struct s5p_aes_dev *dd,
799 struct s5p_hash_reqctx *ctx)
800 {
801 u32 *hash = (u32 *)ctx->digest;
802 unsigned int i;
803
804 for (i = 0; i < ctx->nregs; i++)
805 s5p_hash_write(dd, SSS_REG_HASH_IV(i), hash[i]);
806 }
807
808 /**
809 * s5p_hash_write_iv() - write IV for next partial/finup op.
810 * @req: AHASH request
811 */
812 static void s5p_hash_write_iv(struct ahash_request *req)
813 {
814 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
815
816 s5p_hash_write_ctx_iv(ctx->dd, ctx);
817 }
818
819 /**
820 * s5p_hash_copy_result() - copy digest into req->result
821 * @req: AHASH request
822 */
823 static void s5p_hash_copy_result(struct ahash_request *req)
824 {
825 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
826
827 if (!req->result)
828 return;
829
830 memcpy(req->result, ctx->digest, ctx->nregs * HASH_REG_SIZEOF);
831 }
832
833 /**
834 * s5p_hash_dma_flush() - flush HASH DMA
835 * @dev: secss device
836 */
837 static void s5p_hash_dma_flush(struct s5p_aes_dev *dev)
838 {
839 SSS_WRITE(dev, FCHRDMAC, SSS_FCHRDMAC_FLUSH);
840 }
841
842 /**
843 * s5p_hash_dma_enable() - enable DMA mode for HASH
844 * @dev: secss device
845 *
846 * enable DMA mode for HASH
847 */
848 static void s5p_hash_dma_enable(struct s5p_aes_dev *dev)
849 {
850 s5p_hash_write(dev, SSS_REG_HASH_CTRL_FIFO, SSS_HASH_FIFO_MODE_DMA);
851 }
852
853 /**
854 * s5p_hash_irq_disable() - disable irq HASH signals
855 * @dev: secss device
856 * @flags: bitfield with irq's to be disabled
857 */
858 static void s5p_hash_irq_disable(struct s5p_aes_dev *dev, u32 flags)
859 {
860 SSS_WRITE(dev, FCINTENCLR, flags);
861 }
862
863 /**
864 * s5p_hash_irq_enable() - enable irq signals
865 * @dev: secss device
866 * @flags: bitfield with irq's to be enabled
867 */
868 static void s5p_hash_irq_enable(struct s5p_aes_dev *dev, int flags)
869 {
870 SSS_WRITE(dev, FCINTENSET, flags);
871 }
872
873 /**
874 * s5p_hash_set_flow() - set flow inside SecSS AES/DES with/without HASH
875 * @dev: secss device
876 * @hashflow: HASH stream flow with/without crypto AES/DES
877 */
878 static void s5p_hash_set_flow(struct s5p_aes_dev *dev, u32 hashflow)
879 {
880 unsigned long flags;
881 u32 flow;
882
883 spin_lock_irqsave(&dev->lock, flags);
884
885 flow = SSS_READ(dev, FCFIFOCTRL);
886 flow &= ~SSS_HASHIN_MASK;
887 flow |= hashflow;
888 SSS_WRITE(dev, FCFIFOCTRL, flow);
889
890 spin_unlock_irqrestore(&dev->lock, flags);
891 }
892
893 /**
894 * s5p_ahash_dma_init() - enable DMA and set HASH flow inside SecSS
895 * @dev: secss device
896 * @hashflow: HASH stream flow with/without AES/DES
897 *
898 * flush HASH DMA and enable DMA, set HASH stream flow inside SecSS HW,
899 * enable HASH irq's HRDMA, HDONE, HPART
900 */
901 static void s5p_ahash_dma_init(struct s5p_aes_dev *dev, u32 hashflow)
902 {
903 s5p_hash_irq_disable(dev, SSS_FCINTENCLR_HRDMAINTENCLR |
904 SSS_FCINTENCLR_HDONEINTENCLR |
905 SSS_FCINTENCLR_HPARTINTENCLR);
906 s5p_hash_dma_flush(dev);
907
908 s5p_hash_dma_enable(dev);
909 s5p_hash_set_flow(dev, hashflow & SSS_HASHIN_MASK);
910 s5p_hash_irq_enable(dev, SSS_FCINTENSET_HRDMAINTENSET |
911 SSS_FCINTENSET_HDONEINTENSET |
912 SSS_FCINTENSET_HPARTINTENSET);
913 }
914
915 /**
916 * s5p_hash_write_ctrl() - prepare HASH block in SecSS for processing
917 * @dd: secss device
918 * @length: length for request
919 * @final: true if final op
920 *
921 * Prepare SSS HASH block for processing bytes in DMA mode. If it is called
922 * after previous updates, fill up IV words. For final, calculate and set
923 * lengths for HASH so SecSS can finalize hash. For partial, set SSS HASH
924 * length as 2^63 so it will be never reached and set to zero prelow and
925 * prehigh.
926 *
927 * This function does not start DMA transfer.
928 */
929 static void s5p_hash_write_ctrl(struct s5p_aes_dev *dd, size_t length,
930 bool final)
931 {
932 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req);
933 u32 prelow, prehigh, low, high;
934 u32 configflags, swapflags;
935 u64 tmplen;
936
937 configflags = ctx->engine | SSS_HASH_INIT_BIT;
938
939 if (likely(ctx->digcnt)) {
940 s5p_hash_write_ctx_iv(dd, ctx);
941 configflags |= SSS_HASH_USER_IV_EN;
942 }
943
944 if (final) {
945 /* number of bytes for last part */
946 low = length;
947 high = 0;
948 /* total number of bits prev hashed */
949 tmplen = ctx->digcnt * 8;
950 prelow = (u32)tmplen;
951 prehigh = (u32)(tmplen >> 32);
952 } else {
953 prelow = 0;
954 prehigh = 0;
955 low = 0;
956 high = BIT(31);
957 }
958
959 swapflags = SSS_HASH_BYTESWAP_DI | SSS_HASH_BYTESWAP_DO |
960 SSS_HASH_BYTESWAP_IV | SSS_HASH_BYTESWAP_KEY;
961
962 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_LOW, low);
963 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_HIGH, high);
964 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_LOW, prelow);
965 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_HIGH, prehigh);
966
967 s5p_hash_write(dd, SSS_REG_HASH_CTRL_SWAP, swapflags);
968 s5p_hash_write(dd, SSS_REG_HASH_CTRL, configflags);
969 }
970
971 /**
972 * s5p_hash_xmit_dma() - start DMA hash processing
973 * @dd: secss device
974 * @length: length for request
975 * @final: true if final op
976 *
977 * Update digcnt here, as it is needed for finup/final op.
978 */
979 static int s5p_hash_xmit_dma(struct s5p_aes_dev *dd, size_t length,
980 bool final)
981 {
982 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req);
983 unsigned int cnt;
984
985 cnt = dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
986 if (!cnt) {
987 dev_err(dd->dev, "dma_map_sg error\n");
988 ctx->error = true;
989 return -EINVAL;
990 }
991
992 set_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags);
993 dd->hash_sg_iter = ctx->sg;
994 dd->hash_sg_cnt = cnt;
995 s5p_hash_write_ctrl(dd, length, final);
996 ctx->digcnt += length;
997 ctx->total -= length;
998
999 /* catch last interrupt */
1000 if (final)
1001 set_bit(HASH_FLAGS_FINAL, &dd->hash_flags);
1002
1003 s5p_set_dma_hashdata(dd, dd->hash_sg_iter); /* DMA starts */
1004
1005 return -EINPROGRESS;
1006 }
1007
1008 /**
1009 * s5p_hash_copy_sgs() - copy request's bytes into new buffer
1010 * @ctx: request context
1011 * @sg: source scatterlist request
1012 * @new_len: number of bytes to process from sg
1013 *
1014 * Allocate new buffer, copy data for HASH into it. If there was xmit_buf
1015 * filled, copy it first, then copy data from sg into it. Prepare one sgl[0]
1016 * with allocated buffer.
1017 *
1018 * Set bit in dd->hash_flag so we can free it after irq ends processing.
1019 */
1020 static int s5p_hash_copy_sgs(struct s5p_hash_reqctx *ctx,
1021 struct scatterlist *sg, unsigned int new_len)
1022 {
1023 unsigned int pages, len;
1024 void *buf;
1025
1026 len = new_len + ctx->bufcnt;
1027 pages = get_order(len);
1028
1029 buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
1030 if (!buf) {
1031 dev_err(ctx->dd->dev, "alloc pages for unaligned case.\n");
1032 ctx->error = true;
1033 return -ENOMEM;
1034 }
1035
1036 if (ctx->bufcnt)
1037 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
1038
1039 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->skip,
1040 new_len, 0);
1041 sg_init_table(ctx->sgl, 1);
1042 sg_set_buf(ctx->sgl, buf, len);
1043 ctx->sg = ctx->sgl;
1044 ctx->sg_len = 1;
1045 ctx->bufcnt = 0;
1046 ctx->skip = 0;
1047 set_bit(HASH_FLAGS_SGS_COPIED, &ctx->dd->hash_flags);
1048
1049 return 0;
1050 }
1051
1052 /**
1053 * s5p_hash_copy_sg_lists() - copy sg list and make fixes in copy
1054 * @ctx: request context
1055 * @sg: source scatterlist request
1056 * @new_len: number of bytes to process from sg
1057 *
1058 * Allocate new scatterlist table, copy data for HASH into it. If there was
1059 * xmit_buf filled, prepare it first, then copy page, length and offset from
1060 * source sg into it, adjusting begin and/or end for skip offset and
1061 * hash_later value.
1062 *
1063 * Resulting sg table will be assigned to ctx->sg. Set flag so we can free
1064 * it after irq ends processing.
1065 */
1066 static int s5p_hash_copy_sg_lists(struct s5p_hash_reqctx *ctx,
1067 struct scatterlist *sg, unsigned int new_len)
1068 {
1069 unsigned int skip = ctx->skip, n = sg_nents(sg);
1070 struct scatterlist *tmp;
1071 unsigned int len;
1072
1073 if (ctx->bufcnt)
1074 n++;
1075
1076 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
1077 if (!ctx->sg) {
1078 ctx->error = true;
1079 return -ENOMEM;
1080 }
1081
1082 sg_init_table(ctx->sg, n);
1083
1084 tmp = ctx->sg;
1085
1086 ctx->sg_len = 0;
1087
1088 if (ctx->bufcnt) {
1089 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
1090 tmp = sg_next(tmp);
1091 ctx->sg_len++;
1092 }
1093
1094 while (sg && skip >= sg->length) {
1095 skip -= sg->length;
1096 sg = sg_next(sg);
1097 }
1098
1099 while (sg && new_len) {
1100 len = sg->length - skip;
1101 if (new_len < len)
1102 len = new_len;
1103
1104 new_len -= len;
1105 sg_set_page(tmp, sg_page(sg), len, sg->offset + skip);
1106 skip = 0;
1107 if (new_len <= 0)
1108 sg_mark_end(tmp);
1109
1110 tmp = sg_next(tmp);
1111 ctx->sg_len++;
1112 sg = sg_next(sg);
1113 }
1114
1115 set_bit(HASH_FLAGS_SGS_ALLOCED, &ctx->dd->hash_flags);
1116
1117 return 0;
1118 }
1119
1120 /**
1121 * s5p_hash_prepare_sgs() - prepare sg for processing
1122 * @ctx: request context
1123 * @sg: source scatterlist request
1124 * @nbytes: number of bytes to process from sg
1125 * @final: final flag
1126 *
1127 * Check two conditions: (1) if buffers in sg have len aligned data, and (2)
1128 * sg table have good aligned elements (list_ok). If one of this checks fails,
1129 * then either (1) allocates new buffer for data with s5p_hash_copy_sgs, copy
1130 * data into this buffer and prepare request in sgl, or (2) allocates new sg
1131 * table and prepare sg elements.
1132 *
1133 * For digest or finup all conditions can be good, and we may not need any
1134 * fixes.
1135 */
1136 static int s5p_hash_prepare_sgs(struct s5p_hash_reqctx *ctx,
1137 struct scatterlist *sg,
1138 unsigned int new_len, bool final)
1139 {
1140 unsigned int skip = ctx->skip, nbytes = new_len, n = 0;
1141 bool aligned = true, list_ok = true;
1142 struct scatterlist *sg_tmp = sg;
1143
1144 if (!sg || !sg->length || !new_len)
1145 return 0;
1146
1147 if (skip || !final)
1148 list_ok = false;
1149
1150 while (nbytes > 0 && sg_tmp) {
1151 n++;
1152 if (skip >= sg_tmp->length) {
1153 skip -= sg_tmp->length;
1154 if (!sg_tmp->length) {
1155 aligned = false;
1156 break;
1157 }
1158 } else {
1159 if (!IS_ALIGNED(sg_tmp->length - skip, BUFLEN)) {
1160 aligned = false;
1161 break;
1162 }
1163
1164 if (nbytes < sg_tmp->length - skip) {
1165 list_ok = false;
1166 break;
1167 }
1168
1169 nbytes -= sg_tmp->length - skip;
1170 skip = 0;
1171 }
1172
1173 sg_tmp = sg_next(sg_tmp);
1174 }
1175
1176 if (!aligned)
1177 return s5p_hash_copy_sgs(ctx, sg, new_len);
1178 else if (!list_ok)
1179 return s5p_hash_copy_sg_lists(ctx, sg, new_len);
1180
1181 /*
1182 * Have aligned data from previous operation and/or current
1183 * Note: will enter here only if (digest or finup) and aligned
1184 */
1185 if (ctx->bufcnt) {
1186 ctx->sg_len = n;
1187 sg_init_table(ctx->sgl, 2);
1188 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, ctx->bufcnt);
1189 sg_chain(ctx->sgl, 2, sg);
1190 ctx->sg = ctx->sgl;
1191 ctx->sg_len++;
1192 } else {
1193 ctx->sg = sg;
1194 ctx->sg_len = n;
1195 }
1196
1197 return 0;
1198 }
1199
1200 /**
1201 * s5p_hash_prepare_request() - prepare request for processing
1202 * @req: AHASH request
1203 * @update: true if UPDATE op
1204 *
1205 * Note 1: we can have update flag _and_ final flag at the same time.
1206 * Note 2: we enter here when digcnt > BUFLEN (=HASH_BLOCK_SIZE) or
1207 * either req->nbytes or ctx->bufcnt + req->nbytes is > BUFLEN or
1208 * we have final op
1209 */
1210 static int s5p_hash_prepare_request(struct ahash_request *req, bool update)
1211 {
1212 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1213 bool final = ctx->finup;
1214 int xmit_len, hash_later, nbytes;
1215 int ret;
1216
1217 if (!req)
1218 return 0;
1219
1220 if (update)
1221 nbytes = req->nbytes;
1222 else
1223 nbytes = 0;
1224
1225 ctx->total = nbytes + ctx->bufcnt;
1226 if (!ctx->total)
1227 return 0;
1228
1229 if (nbytes && (!IS_ALIGNED(ctx->bufcnt, BUFLEN))) {
1230 /* bytes left from previous request, so fill up to BUFLEN */
1231 int len = BUFLEN - ctx->bufcnt % BUFLEN;
1232
1233 if (len > nbytes)
1234 len = nbytes;
1235
1236 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1237 0, len, 0);
1238 ctx->bufcnt += len;
1239 nbytes -= len;
1240 ctx->skip = len;
1241 } else {
1242 ctx->skip = 0;
1243 }
1244
1245 if (ctx->bufcnt)
1246 memcpy(ctx->dd->xmit_buf, ctx->buffer, ctx->bufcnt);
1247
1248 xmit_len = ctx->total;
1249 if (final) {
1250 hash_later = 0;
1251 } else {
1252 if (IS_ALIGNED(xmit_len, BUFLEN))
1253 xmit_len -= BUFLEN;
1254 else
1255 xmit_len -= xmit_len & (BUFLEN - 1);
1256
1257 hash_later = ctx->total - xmit_len;
1258 /* copy hash_later bytes from end of req->src */
1259 /* previous bytes are in xmit_buf, so no overwrite */
1260 scatterwalk_map_and_copy(ctx->buffer, req->src,
1261 req->nbytes - hash_later,
1262 hash_later, 0);
1263 }
1264
1265 if (xmit_len > BUFLEN) {
1266 ret = s5p_hash_prepare_sgs(ctx, req->src, nbytes - hash_later,
1267 final);
1268 if (ret)
1269 return ret;
1270 } else {
1271 /* have buffered data only */
1272 if (unlikely(!ctx->bufcnt)) {
1273 /* first update didn't fill up buffer */
1274 scatterwalk_map_and_copy(ctx->dd->xmit_buf, req->src,
1275 0, xmit_len, 0);
1276 }
1277
1278 sg_init_table(ctx->sgl, 1);
1279 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, xmit_len);
1280
1281 ctx->sg = ctx->sgl;
1282 ctx->sg_len = 1;
1283 }
1284
1285 ctx->bufcnt = hash_later;
1286 if (!final)
1287 ctx->total = xmit_len;
1288
1289 return 0;
1290 }
1291
1292 /**
1293 * s5p_hash_update_dma_stop() - unmap DMA
1294 * @dd: secss device
1295 *
1296 * Unmap scatterlist ctx->sg.
1297 */
1298 static void s5p_hash_update_dma_stop(struct s5p_aes_dev *dd)
1299 {
1300 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req);
1301
1302 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
1303 clear_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags);
1304 }
1305
1306 /**
1307 * s5p_hash_finish() - copy calculated digest to crypto layer
1308 * @req: AHASH request
1309 */
1310 static void s5p_hash_finish(struct ahash_request *req)
1311 {
1312 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1313 struct s5p_aes_dev *dd = ctx->dd;
1314
1315 if (ctx->digcnt)
1316 s5p_hash_copy_result(req);
1317
1318 dev_dbg(dd->dev, "hash_finish digcnt: %lld\n", ctx->digcnt);
1319 }
1320
1321 /**
1322 * s5p_hash_finish_req() - finish request
1323 * @req: AHASH request
1324 * @err: error
1325 */
1326 static void s5p_hash_finish_req(struct ahash_request *req, int err)
1327 {
1328 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1329 struct s5p_aes_dev *dd = ctx->dd;
1330 unsigned long flags;
1331
1332 if (test_bit(HASH_FLAGS_SGS_COPIED, &dd->hash_flags))
1333 free_pages((unsigned long)sg_virt(ctx->sg),
1334 get_order(ctx->sg->length));
1335
1336 if (test_bit(HASH_FLAGS_SGS_ALLOCED, &dd->hash_flags))
1337 kfree(ctx->sg);
1338
1339 ctx->sg = NULL;
1340 dd->hash_flags &= ~(BIT(HASH_FLAGS_SGS_ALLOCED) |
1341 BIT(HASH_FLAGS_SGS_COPIED));
1342
1343 if (!err && !ctx->error) {
1344 s5p_hash_read_msg(req);
1345 if (test_bit(HASH_FLAGS_FINAL, &dd->hash_flags))
1346 s5p_hash_finish(req);
1347 } else {
1348 ctx->error = true;
1349 }
1350
1351 spin_lock_irqsave(&dd->hash_lock, flags);
1352 dd->hash_flags &= ~(BIT(HASH_FLAGS_BUSY) | BIT(HASH_FLAGS_FINAL) |
1353 BIT(HASH_FLAGS_DMA_READY) |
1354 BIT(HASH_FLAGS_OUTPUT_READY));
1355 spin_unlock_irqrestore(&dd->hash_lock, flags);
1356
1357 if (req->base.complete)
1358 req->base.complete(&req->base, err);
1359 }
1360
1361 /**
1362 * s5p_hash_handle_queue() - handle hash queue
1363 * @dd: device s5p_aes_dev
1364 * @req: AHASH request
1365 *
1366 * If req!=NULL enqueue it on dd->queue, if FLAGS_BUSY is not set on the
1367 * device then processes the first request from the dd->queue
1368 *
1369 * Returns: see s5p_hash_final below.
1370 */
1371 static int s5p_hash_handle_queue(struct s5p_aes_dev *dd,
1372 struct ahash_request *req)
1373 {
1374 struct crypto_async_request *async_req, *backlog;
1375 struct s5p_hash_reqctx *ctx;
1376 unsigned long flags;
1377 int err = 0, ret = 0;
1378
1379 retry:
1380 spin_lock_irqsave(&dd->hash_lock, flags);
1381 if (req)
1382 ret = ahash_enqueue_request(&dd->hash_queue, req);
1383
1384 if (test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) {
1385 spin_unlock_irqrestore(&dd->hash_lock, flags);
1386 return ret;
1387 }
1388
1389 backlog = crypto_get_backlog(&dd->hash_queue);
1390 async_req = crypto_dequeue_request(&dd->hash_queue);
1391 if (async_req)
1392 set_bit(HASH_FLAGS_BUSY, &dd->hash_flags);
1393
1394 spin_unlock_irqrestore(&dd->hash_lock, flags);
1395
1396 if (!async_req)
1397 return ret;
1398
1399 if (backlog)
1400 backlog->complete(backlog, -EINPROGRESS);
1401
1402 req = ahash_request_cast(async_req);
1403 dd->hash_req = req;
1404 ctx = ahash_request_ctx(req);
1405
1406 err = s5p_hash_prepare_request(req, ctx->op_update);
1407 if (err || !ctx->total)
1408 goto out;
1409
1410 dev_dbg(dd->dev, "handling new req, op_update: %u, nbytes: %d\n",
1411 ctx->op_update, req->nbytes);
1412
1413 s5p_ahash_dma_init(dd, SSS_HASHIN_INDEPENDENT);
1414 if (ctx->digcnt)
1415 s5p_hash_write_iv(req); /* restore hash IV */
1416
1417 if (ctx->op_update) { /* HASH_OP_UPDATE */
1418 err = s5p_hash_xmit_dma(dd, ctx->total, ctx->finup);
1419 if (err != -EINPROGRESS && ctx->finup && !ctx->error)
1420 /* no final() after finup() */
1421 err = s5p_hash_xmit_dma(dd, ctx->total, true);
1422 } else { /* HASH_OP_FINAL */
1423 err = s5p_hash_xmit_dma(dd, ctx->total, true);
1424 }
1425 out:
1426 if (err != -EINPROGRESS) {
1427 /* hash_tasklet_cb will not finish it, so do it here */
1428 s5p_hash_finish_req(req, err);
1429 req = NULL;
1430
1431 /*
1432 * Execute next request immediately if there is anything
1433 * in queue.
1434 */
1435 goto retry;
1436 }
1437
1438 return ret;
1439 }
1440
1441 /**
1442 * s5p_hash_tasklet_cb() - hash tasklet
1443 * @data: ptr to s5p_aes_dev
1444 */
1445 static void s5p_hash_tasklet_cb(unsigned long data)
1446 {
1447 struct s5p_aes_dev *dd = (struct s5p_aes_dev *)data;
1448
1449 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) {
1450 s5p_hash_handle_queue(dd, NULL);
1451 return;
1452 }
1453
1454 if (test_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags)) {
1455 if (test_and_clear_bit(HASH_FLAGS_DMA_ACTIVE,
1456 &dd->hash_flags)) {
1457 s5p_hash_update_dma_stop(dd);
1458 }
1459
1460 if (test_and_clear_bit(HASH_FLAGS_OUTPUT_READY,
1461 &dd->hash_flags)) {
1462 /* hash or semi-hash ready */
1463 clear_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags);
1464 goto finish;
1465 }
1466 }
1467
1468 return;
1469
1470 finish:
1471 /* finish curent request */
1472 s5p_hash_finish_req(dd->hash_req, 0);
1473
1474 /* If we are not busy, process next req */
1475 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags))
1476 s5p_hash_handle_queue(dd, NULL);
1477 }
1478
1479 /**
1480 * s5p_hash_enqueue() - enqueue request
1481 * @req: AHASH request
1482 * @op: operation UPDATE (true) or FINAL (false)
1483 *
1484 * Returns: see s5p_hash_final below.
1485 */
1486 static int s5p_hash_enqueue(struct ahash_request *req, bool op)
1487 {
1488 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1489 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1490
1491 ctx->op_update = op;
1492
1493 return s5p_hash_handle_queue(tctx->dd, req);
1494 }
1495
1496 /**
1497 * s5p_hash_update() - process the hash input data
1498 * @req: AHASH request
1499 *
1500 * If request will fit in buffer, copy it and return immediately
1501 * else enqueue it with OP_UPDATE.
1502 *
1503 * Returns: see s5p_hash_final below.
1504 */
1505 static int s5p_hash_update(struct ahash_request *req)
1506 {
1507 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1508
1509 if (!req->nbytes)
1510 return 0;
1511
1512 if (ctx->bufcnt + req->nbytes <= BUFLEN) {
1513 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1514 0, req->nbytes, 0);
1515 ctx->bufcnt += req->nbytes;
1516 return 0;
1517 }
1518
1519 return s5p_hash_enqueue(req, true); /* HASH_OP_UPDATE */
1520 }
1521
1522 /**
1523 * s5p_hash_shash_digest() - calculate shash digest
1524 * @tfm: crypto transformation
1525 * @flags: tfm flags
1526 * @data: input data
1527 * @len: length of data
1528 * @out: output buffer
1529 */
1530 static int s5p_hash_shash_digest(struct crypto_shash *tfm, u32 flags,
1531 const u8 *data, unsigned int len, u8 *out)
1532 {
1533 SHASH_DESC_ON_STACK(shash, tfm);
1534
1535 shash->tfm = tfm;
1536 shash->flags = flags & ~CRYPTO_TFM_REQ_MAY_SLEEP;
1537
1538 return crypto_shash_digest(shash, data, len, out);
1539 }
1540
1541 /**
1542 * s5p_hash_final_shash() - calculate shash digest
1543 * @req: AHASH request
1544 */
1545 static int s5p_hash_final_shash(struct ahash_request *req)
1546 {
1547 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1548 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1549
1550 return s5p_hash_shash_digest(tctx->fallback, req->base.flags,
1551 ctx->buffer, ctx->bufcnt, req->result);
1552 }
1553
1554 /**
1555 * s5p_hash_final() - close up hash and calculate digest
1556 * @req: AHASH request
1557 *
1558 * Note: in final req->src do not have any data, and req->nbytes can be
1559 * non-zero.
1560 *
1561 * If there were no input data processed yet and the buffered hash data is
1562 * less than BUFLEN (64) then calculate the final hash immediately by using
1563 * SW algorithm fallback.
1564 *
1565 * Otherwise enqueues the current AHASH request with OP_FINAL operation op
1566 * and finalize hash message in HW. Note that if digcnt!=0 then there were
1567 * previous update op, so there are always some buffered bytes in ctx->buffer,
1568 * which means that ctx->bufcnt!=0
1569 *
1570 * Returns:
1571 * 0 if the request has been processed immediately,
1572 * -EINPROGRESS if the operation has been queued for later execution or is set
1573 * to processing by HW,
1574 * -EBUSY if queue is full and request should be resubmitted later,
1575 * other negative values denotes an error.
1576 */
1577 static int s5p_hash_final(struct ahash_request *req)
1578 {
1579 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1580
1581 ctx->finup = true;
1582 if (ctx->error)
1583 return -EINVAL; /* uncompleted hash is not needed */
1584
1585 if (!ctx->digcnt && ctx->bufcnt < BUFLEN)
1586 return s5p_hash_final_shash(req);
1587
1588 return s5p_hash_enqueue(req, false); /* HASH_OP_FINAL */
1589 }
1590
1591 /**
1592 * s5p_hash_finup() - process last req->src and calculate digest
1593 * @req: AHASH request containing the last update data
1594 *
1595 * Return values: see s5p_hash_final above.
1596 */
1597 static int s5p_hash_finup(struct ahash_request *req)
1598 {
1599 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1600 int err1, err2;
1601
1602 ctx->finup = true;
1603
1604 err1 = s5p_hash_update(req);
1605 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1606 return err1;
1607
1608 /*
1609 * final() has to be always called to cleanup resources even if
1610 * update() failed, except EINPROGRESS or calculate digest for small
1611 * size
1612 */
1613 err2 = s5p_hash_final(req);
1614
1615 return err1 ?: err2;
1616 }
1617
1618 /**
1619 * s5p_hash_init() - initialize AHASH request contex
1620 * @req: AHASH request
1621 *
1622 * Init async hash request context.
1623 */
1624 static int s5p_hash_init(struct ahash_request *req)
1625 {
1626 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1627 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1628 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm);
1629
1630 ctx->dd = tctx->dd;
1631 ctx->error = false;
1632 ctx->finup = false;
1633 ctx->bufcnt = 0;
1634 ctx->digcnt = 0;
1635 ctx->total = 0;
1636 ctx->skip = 0;
1637
1638 dev_dbg(tctx->dd->dev, "init: digest size: %d\n",
1639 crypto_ahash_digestsize(tfm));
1640
1641 switch (crypto_ahash_digestsize(tfm)) {
1642 case MD5_DIGEST_SIZE:
1643 ctx->engine = SSS_HASH_ENGINE_MD5;
1644 ctx->nregs = HASH_MD5_MAX_REG;
1645 break;
1646 case SHA1_DIGEST_SIZE:
1647 ctx->engine = SSS_HASH_ENGINE_SHA1;
1648 ctx->nregs = HASH_SHA1_MAX_REG;
1649 break;
1650 case SHA256_DIGEST_SIZE:
1651 ctx->engine = SSS_HASH_ENGINE_SHA256;
1652 ctx->nregs = HASH_SHA256_MAX_REG;
1653 break;
1654 default:
1655 ctx->error = true;
1656 return -EINVAL;
1657 }
1658
1659 return 0;
1660 }
1661
1662 /**
1663 * s5p_hash_digest - calculate digest from req->src
1664 * @req: AHASH request
1665 *
1666 * Return values: see s5p_hash_final above.
1667 */
1668 static int s5p_hash_digest(struct ahash_request *req)
1669 {
1670 return s5p_hash_init(req) ?: s5p_hash_finup(req);
1671 }
1672
1673 /**
1674 * s5p_hash_cra_init_alg - init crypto alg transformation
1675 * @tfm: crypto transformation
1676 */
1677 static int s5p_hash_cra_init_alg(struct crypto_tfm *tfm)
1678 {
1679 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm);
1680 const char *alg_name = crypto_tfm_alg_name(tfm);
1681
1682 tctx->dd = s5p_dev;
1683 /* Allocate a fallback and abort if it failed. */
1684 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1685 CRYPTO_ALG_NEED_FALLBACK);
1686 if (IS_ERR(tctx->fallback)) {
1687 pr_err("fallback alloc fails for '%s'\n", alg_name);
1688 return PTR_ERR(tctx->fallback);
1689 }
1690
1691 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1692 sizeof(struct s5p_hash_reqctx) + BUFLEN);
1693
1694 return 0;
1695 }
1696
1697 /**
1698 * s5p_hash_cra_init - init crypto tfm
1699 * @tfm: crypto transformation
1700 */
1701 static int s5p_hash_cra_init(struct crypto_tfm *tfm)
1702 {
1703 return s5p_hash_cra_init_alg(tfm);
1704 }
1705
1706 /**
1707 * s5p_hash_cra_exit - exit crypto tfm
1708 * @tfm: crypto transformation
1709 *
1710 * free allocated fallback
1711 */
1712 static void s5p_hash_cra_exit(struct crypto_tfm *tfm)
1713 {
1714 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm);
1715
1716 crypto_free_shash(tctx->fallback);
1717 tctx->fallback = NULL;
1718 }
1719
1720 /**
1721 * s5p_hash_export - export hash state
1722 * @req: AHASH request
1723 * @out: buffer for exported state
1724 */
1725 static int s5p_hash_export(struct ahash_request *req, void *out)
1726 {
1727 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1728
1729 memcpy(out, ctx, sizeof(*ctx) + ctx->bufcnt);
1730
1731 return 0;
1732 }
1733
1734 /**
1735 * s5p_hash_import - import hash state
1736 * @req: AHASH request
1737 * @in: buffer with state to be imported from
1738 */
1739 static int s5p_hash_import(struct ahash_request *req, const void *in)
1740 {
1741 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1742 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1743 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm);
1744 const struct s5p_hash_reqctx *ctx_in = in;
1745
1746 memcpy(ctx, in, sizeof(*ctx) + BUFLEN);
1747 if (ctx_in->bufcnt > BUFLEN) {
1748 ctx->error = true;
1749 return -EINVAL;
1750 }
1751
1752 ctx->dd = tctx->dd;
1753 ctx->error = false;
1754
1755 return 0;
1756 }
1757
1758 static struct ahash_alg algs_sha1_md5_sha256[] = {
1759 {
1760 .init = s5p_hash_init,
1761 .update = s5p_hash_update,
1762 .final = s5p_hash_final,
1763 .finup = s5p_hash_finup,
1764 .digest = s5p_hash_digest,
1765 .export = s5p_hash_export,
1766 .import = s5p_hash_import,
1767 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN,
1768 .halg.digestsize = SHA1_DIGEST_SIZE,
1769 .halg.base = {
1770 .cra_name = "sha1",
1771 .cra_driver_name = "exynos-sha1",
1772 .cra_priority = 100,
1773 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1774 CRYPTO_ALG_KERN_DRIVER_ONLY |
1775 CRYPTO_ALG_ASYNC |
1776 CRYPTO_ALG_NEED_FALLBACK,
1777 .cra_blocksize = HASH_BLOCK_SIZE,
1778 .cra_ctxsize = sizeof(struct s5p_hash_ctx),
1779 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK,
1780 .cra_module = THIS_MODULE,
1781 .cra_init = s5p_hash_cra_init,
1782 .cra_exit = s5p_hash_cra_exit,
1783 }
1784 },
1785 {
1786 .init = s5p_hash_init,
1787 .update = s5p_hash_update,
1788 .final = s5p_hash_final,
1789 .finup = s5p_hash_finup,
1790 .digest = s5p_hash_digest,
1791 .export = s5p_hash_export,
1792 .import = s5p_hash_import,
1793 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN,
1794 .halg.digestsize = MD5_DIGEST_SIZE,
1795 .halg.base = {
1796 .cra_name = "md5",
1797 .cra_driver_name = "exynos-md5",
1798 .cra_priority = 100,
1799 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1800 CRYPTO_ALG_KERN_DRIVER_ONLY |
1801 CRYPTO_ALG_ASYNC |
1802 CRYPTO_ALG_NEED_FALLBACK,
1803 .cra_blocksize = HASH_BLOCK_SIZE,
1804 .cra_ctxsize = sizeof(struct s5p_hash_ctx),
1805 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK,
1806 .cra_module = THIS_MODULE,
1807 .cra_init = s5p_hash_cra_init,
1808 .cra_exit = s5p_hash_cra_exit,
1809 }
1810 },
1811 {
1812 .init = s5p_hash_init,
1813 .update = s5p_hash_update,
1814 .final = s5p_hash_final,
1815 .finup = s5p_hash_finup,
1816 .digest = s5p_hash_digest,
1817 .export = s5p_hash_export,
1818 .import = s5p_hash_import,
1819 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN,
1820 .halg.digestsize = SHA256_DIGEST_SIZE,
1821 .halg.base = {
1822 .cra_name = "sha256",
1823 .cra_driver_name = "exynos-sha256",
1824 .cra_priority = 100,
1825 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1826 CRYPTO_ALG_KERN_DRIVER_ONLY |
1827 CRYPTO_ALG_ASYNC |
1828 CRYPTO_ALG_NEED_FALLBACK,
1829 .cra_blocksize = HASH_BLOCK_SIZE,
1830 .cra_ctxsize = sizeof(struct s5p_hash_ctx),
1831 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK,
1832 .cra_module = THIS_MODULE,
1833 .cra_init = s5p_hash_cra_init,
1834 .cra_exit = s5p_hash_cra_exit,
1835 }
1836 }
1837
1838 };
1839
1840 static void s5p_set_aes(struct s5p_aes_dev *dev,
1841 uint8_t *key, uint8_t *iv, unsigned int keylen)
1842 {
1843 void __iomem *keystart;
1844
1845 if (iv)
1846 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
1847
1848 if (keylen == AES_KEYSIZE_256)
1849 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0);
1850 else if (keylen == AES_KEYSIZE_192)
1851 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2);
1852 else
1853 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4);
1854
1855 memcpy_toio(keystart, key, keylen);
1856 }
1857
1858 static bool s5p_is_sg_aligned(struct scatterlist *sg)
1859 {
1860 while (sg) {
1861 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE))
1862 return false;
1863 sg = sg_next(sg);
1864 }
1865
1866 return true;
1867 }
1868
1869 static int s5p_set_indata_start(struct s5p_aes_dev *dev,
1870 struct ablkcipher_request *req)
1871 {
1872 struct scatterlist *sg;
1873 int err;
1874
1875 dev->sg_src_cpy = NULL;
1876 sg = req->src;
1877 if (!s5p_is_sg_aligned(sg)) {
1878 dev_dbg(dev->dev,
1879 "At least one unaligned source scatter list, making a copy\n");
1880 err = s5p_make_sg_cpy(dev, sg, &dev->sg_src_cpy);
1881 if (err)
1882 return err;
1883
1884 sg = dev->sg_src_cpy;
1885 }
1886
1887 err = s5p_set_indata(dev, sg);
1888 if (err) {
1889 s5p_free_sg_cpy(dev, &dev->sg_src_cpy);
1890 return err;
1891 }
1892
1893 return 0;
1894 }
1895
1896 static int s5p_set_outdata_start(struct s5p_aes_dev *dev,
1897 struct ablkcipher_request *req)
1898 {
1899 struct scatterlist *sg;
1900 int err;
1901
1902 dev->sg_dst_cpy = NULL;
1903 sg = req->dst;
1904 if (!s5p_is_sg_aligned(sg)) {
1905 dev_dbg(dev->dev,
1906 "At least one unaligned dest scatter list, making a copy\n");
1907 err = s5p_make_sg_cpy(dev, sg, &dev->sg_dst_cpy);
1908 if (err)
1909 return err;
1910
1911 sg = dev->sg_dst_cpy;
1912 }
1913
1914 err = s5p_set_outdata(dev, sg);
1915 if (err) {
1916 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy);
1917 return err;
1918 }
1919
1920 return 0;
1921 }
1922
1923 static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
1924 {
1925 struct ablkcipher_request *req = dev->req;
1926 uint32_t aes_control;
1927 unsigned long flags;
1928 int err;
1929
1930 aes_control = SSS_AES_KEY_CHANGE_MODE;
1931 if (mode & FLAGS_AES_DECRYPT)
1932 aes_control |= SSS_AES_MODE_DECRYPT;
1933
1934 if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC)
1935 aes_control |= SSS_AES_CHAIN_MODE_CBC;
1936 else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR)
1937 aes_control |= SSS_AES_CHAIN_MODE_CTR;
1938
1939 if (dev->ctx->keylen == AES_KEYSIZE_192)
1940 aes_control |= SSS_AES_KEY_SIZE_192;
1941 else if (dev->ctx->keylen == AES_KEYSIZE_256)
1942 aes_control |= SSS_AES_KEY_SIZE_256;
1943
1944 aes_control |= SSS_AES_FIFO_MODE;
1945
1946 /* as a variant it is possible to use byte swapping on DMA side */
1947 aes_control |= SSS_AES_BYTESWAP_DI
1948 | SSS_AES_BYTESWAP_DO
1949 | SSS_AES_BYTESWAP_IV
1950 | SSS_AES_BYTESWAP_KEY
1951 | SSS_AES_BYTESWAP_CNT;
1952
1953 spin_lock_irqsave(&dev->lock, flags);
1954
1955 SSS_WRITE(dev, FCINTENCLR,
1956 SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR);
1957 SSS_WRITE(dev, FCFIFOCTRL, 0x00);
1958
1959 err = s5p_set_indata_start(dev, req);
1960 if (err)
1961 goto indata_error;
1962
1963 err = s5p_set_outdata_start(dev, req);
1964 if (err)
1965 goto outdata_error;
1966
1967 SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
1968 s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);
1969
1970 s5p_set_dma_indata(dev, dev->sg_src);
1971 s5p_set_dma_outdata(dev, dev->sg_dst);
1972
1973 SSS_WRITE(dev, FCINTENSET,
1974 SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET);
1975
1976 spin_unlock_irqrestore(&dev->lock, flags);
1977
1978 return;
1979
1980 outdata_error:
1981 s5p_unset_indata(dev);
1982
1983 indata_error:
1984 s5p_sg_done(dev);
1985 dev->busy = false;
1986 spin_unlock_irqrestore(&dev->lock, flags);
1987 s5p_aes_complete(dev, err);
1988 }
1989
1990 static void s5p_tasklet_cb(unsigned long data)
1991 {
1992 struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data;
1993 struct crypto_async_request *async_req, *backlog;
1994 struct s5p_aes_reqctx *reqctx;
1995 unsigned long flags;
1996
1997 spin_lock_irqsave(&dev->lock, flags);
1998 backlog = crypto_get_backlog(&dev->queue);
1999 async_req = crypto_dequeue_request(&dev->queue);
2000
2001 if (!async_req) {
2002 dev->busy = false;
2003 spin_unlock_irqrestore(&dev->lock, flags);
2004 return;
2005 }
2006 spin_unlock_irqrestore(&dev->lock, flags);
2007
2008 if (backlog)
2009 backlog->complete(backlog, -EINPROGRESS);
2010
2011 dev->req = ablkcipher_request_cast(async_req);
2012 dev->ctx = crypto_tfm_ctx(dev->req->base.tfm);
2013 reqctx = ablkcipher_request_ctx(dev->req);
2014
2015 s5p_aes_crypt_start(dev, reqctx->mode);
2016 }
2017
2018 static int s5p_aes_handle_req(struct s5p_aes_dev *dev,
2019 struct ablkcipher_request *req)
2020 {
2021 unsigned long flags;
2022 int err;
2023
2024 spin_lock_irqsave(&dev->lock, flags);
2025 err = ablkcipher_enqueue_request(&dev->queue, req);
2026 if (dev->busy) {
2027 spin_unlock_irqrestore(&dev->lock, flags);
2028 goto exit;
2029 }
2030 dev->busy = true;
2031
2032 spin_unlock_irqrestore(&dev->lock, flags);
2033
2034 tasklet_schedule(&dev->tasklet);
2035
2036 exit:
2037 return err;
2038 }
2039
2040 static int s5p_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
2041 {
2042 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
2043 struct s5p_aes_reqctx *reqctx = ablkcipher_request_ctx(req);
2044 struct s5p_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
2045 struct s5p_aes_dev *dev = ctx->dev;
2046
2047 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
2048 dev_err(dev->dev, "request size is not exact amount of AES blocks\n");
2049 return -EINVAL;
2050 }
2051
2052 reqctx->mode = mode;
2053
2054 return s5p_aes_handle_req(dev, req);
2055 }
2056
2057 static int s5p_aes_setkey(struct crypto_ablkcipher *cipher,
2058 const uint8_t *key, unsigned int keylen)
2059 {
2060 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
2061 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm);
2062
2063 if (keylen != AES_KEYSIZE_128 &&
2064 keylen != AES_KEYSIZE_192 &&
2065 keylen != AES_KEYSIZE_256)
2066 return -EINVAL;
2067
2068 memcpy(ctx->aes_key, key, keylen);
2069 ctx->keylen = keylen;
2070
2071 return 0;
2072 }
2073
2074 static int s5p_aes_ecb_encrypt(struct ablkcipher_request *req)
2075 {
2076 return s5p_aes_crypt(req, 0);
2077 }
2078
2079 static int s5p_aes_ecb_decrypt(struct ablkcipher_request *req)
2080 {
2081 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT);
2082 }
2083
2084 static int s5p_aes_cbc_encrypt(struct ablkcipher_request *req)
2085 {
2086 return s5p_aes_crypt(req, FLAGS_AES_CBC);
2087 }
2088
2089 static int s5p_aes_cbc_decrypt(struct ablkcipher_request *req)
2090 {
2091 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC);
2092 }
2093
2094 static int s5p_aes_cra_init(struct crypto_tfm *tfm)
2095 {
2096 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm);
2097
2098 ctx->dev = s5p_dev;
2099 tfm->crt_ablkcipher.reqsize = sizeof(struct s5p_aes_reqctx);
2100
2101 return 0;
2102 }
2103
2104 static struct crypto_alg algs[] = {
2105 {
2106 .cra_name = "ecb(aes)",
2107 .cra_driver_name = "ecb-aes-s5p",
2108 .cra_priority = 100,
2109 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2110 CRYPTO_ALG_ASYNC |
2111 CRYPTO_ALG_KERN_DRIVER_ONLY,
2112 .cra_blocksize = AES_BLOCK_SIZE,
2113 .cra_ctxsize = sizeof(struct s5p_aes_ctx),
2114 .cra_alignmask = 0x0f,
2115 .cra_type = &crypto_ablkcipher_type,
2116 .cra_module = THIS_MODULE,
2117 .cra_init = s5p_aes_cra_init,
2118 .cra_u.ablkcipher = {
2119 .min_keysize = AES_MIN_KEY_SIZE,
2120 .max_keysize = AES_MAX_KEY_SIZE,
2121 .setkey = s5p_aes_setkey,
2122 .encrypt = s5p_aes_ecb_encrypt,
2123 .decrypt = s5p_aes_ecb_decrypt,
2124 }
2125 },
2126 {
2127 .cra_name = "cbc(aes)",
2128 .cra_driver_name = "cbc-aes-s5p",
2129 .cra_priority = 100,
2130 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2131 CRYPTO_ALG_ASYNC |
2132 CRYPTO_ALG_KERN_DRIVER_ONLY,
2133 .cra_blocksize = AES_BLOCK_SIZE,
2134 .cra_ctxsize = sizeof(struct s5p_aes_ctx),
2135 .cra_alignmask = 0x0f,
2136 .cra_type = &crypto_ablkcipher_type,
2137 .cra_module = THIS_MODULE,
2138 .cra_init = s5p_aes_cra_init,
2139 .cra_u.ablkcipher = {
2140 .min_keysize = AES_MIN_KEY_SIZE,
2141 .max_keysize = AES_MAX_KEY_SIZE,
2142 .ivsize = AES_BLOCK_SIZE,
2143 .setkey = s5p_aes_setkey,
2144 .encrypt = s5p_aes_cbc_encrypt,
2145 .decrypt = s5p_aes_cbc_decrypt,
2146 }
2147 },
2148 };
2149
2150 static int s5p_aes_probe(struct platform_device *pdev)
2151 {
2152 struct device *dev = &pdev->dev;
2153 int i, j, err = -ENODEV;
2154 struct samsung_aes_variant *variant;
2155 struct s5p_aes_dev *pdata;
2156 struct resource *res;
2157 unsigned int hash_i;
2158
2159 if (s5p_dev)
2160 return -EEXIST;
2161
2162 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2163 if (!pdata)
2164 return -ENOMEM;
2165
2166 variant = find_s5p_sss_version(pdev);
2167 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2168
2169 /*
2170 * Note: HASH and PRNG uses the same registers in secss, avoid
2171 * overwrite each other. This will drop HASH when CONFIG_EXYNOS_RNG
2172 * is enabled in config. We need larger size for HASH registers in
2173 * secss, current describe only AES/DES
2174 */
2175 if (IS_ENABLED(CONFIG_CRYPTO_DEV_EXYNOS_HASH)) {
2176 if (variant == &exynos_aes_data) {
2177 res->end += 0x300;
2178 pdata->use_hash = true;
2179 }
2180 }
2181
2182 pdata->res = res;
2183 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
2184 if (IS_ERR(pdata->ioaddr)) {
2185 if (!pdata->use_hash)
2186 return PTR_ERR(pdata->ioaddr);
2187 /* try AES without HASH */
2188 res->end -= 0x300;
2189 pdata->use_hash = false;
2190 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
2191 if (IS_ERR(pdata->ioaddr))
2192 return PTR_ERR(pdata->ioaddr);
2193 }
2194
2195 pdata->clk = devm_clk_get(dev, "secss");
2196 if (IS_ERR(pdata->clk)) {
2197 dev_err(dev, "failed to find secss clock source\n");
2198 return -ENOENT;
2199 }
2200
2201 err = clk_prepare_enable(pdata->clk);
2202 if (err < 0) {
2203 dev_err(dev, "Enabling SSS clk failed, err %d\n", err);
2204 return err;
2205 }
2206
2207 spin_lock_init(&pdata->lock);
2208 spin_lock_init(&pdata->hash_lock);
2209
2210 pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset;
2211 pdata->io_hash_base = pdata->ioaddr + variant->hash_offset;
2212
2213 pdata->irq_fc = platform_get_irq(pdev, 0);
2214 if (pdata->irq_fc < 0) {
2215 err = pdata->irq_fc;
2216 dev_warn(dev, "feed control interrupt is not available.\n");
2217 goto err_irq;
2218 }
2219 err = devm_request_threaded_irq(dev, pdata->irq_fc, NULL,
2220 s5p_aes_interrupt, IRQF_ONESHOT,
2221 pdev->name, pdev);
2222 if (err < 0) {
2223 dev_warn(dev, "feed control interrupt is not available.\n");
2224 goto err_irq;
2225 }
2226
2227 pdata->busy = false;
2228 pdata->dev = dev;
2229 platform_set_drvdata(pdev, pdata);
2230 s5p_dev = pdata;
2231
2232 tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata);
2233 crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN);
2234
2235 for (i = 0; i < ARRAY_SIZE(algs); i++) {
2236 err = crypto_register_alg(&algs[i]);
2237 if (err)
2238 goto err_algs;
2239 }
2240
2241 if (pdata->use_hash) {
2242 tasklet_init(&pdata->hash_tasklet, s5p_hash_tasklet_cb,
2243 (unsigned long)pdata);
2244 crypto_init_queue(&pdata->hash_queue, SSS_HASH_QUEUE_LENGTH);
2245
2246 for (hash_i = 0; hash_i < ARRAY_SIZE(algs_sha1_md5_sha256);
2247 hash_i++) {
2248 struct ahash_alg *alg;
2249
2250 alg = &algs_sha1_md5_sha256[hash_i];
2251 err = crypto_register_ahash(alg);
2252 if (err) {
2253 dev_err(dev, "can't register '%s': %d\n",
2254 alg->halg.base.cra_driver_name, err);
2255 goto err_hash;
2256 }
2257 }
2258 }
2259
2260 dev_info(dev, "s5p-sss driver registered\n");
2261
2262 return 0;
2263
2264 err_hash:
2265 for (j = hash_i - 1; j >= 0; j--)
2266 crypto_unregister_ahash(&algs_sha1_md5_sha256[j]);
2267
2268 tasklet_kill(&pdata->hash_tasklet);
2269 res->end -= 0x300;
2270
2271 err_algs:
2272 if (i < ARRAY_SIZE(algs))
2273 dev_err(dev, "can't register '%s': %d\n", algs[i].cra_name,
2274 err);
2275
2276 for (j = 0; j < i; j++)
2277 crypto_unregister_alg(&algs[j]);
2278
2279 tasklet_kill(&pdata->tasklet);
2280
2281 err_irq:
2282 clk_disable_unprepare(pdata->clk);
2283
2284 s5p_dev = NULL;
2285
2286 return err;
2287 }
2288
2289 static int s5p_aes_remove(struct platform_device *pdev)
2290 {
2291 struct s5p_aes_dev *pdata = platform_get_drvdata(pdev);
2292 int i;
2293
2294 if (!pdata)
2295 return -ENODEV;
2296
2297 for (i = 0; i < ARRAY_SIZE(algs); i++)
2298 crypto_unregister_alg(&algs[i]);
2299
2300 tasklet_kill(&pdata->tasklet);
2301 if (pdata->use_hash) {
2302 for (i = ARRAY_SIZE(algs_sha1_md5_sha256) - 1; i >= 0; i--)
2303 crypto_unregister_ahash(&algs_sha1_md5_sha256[i]);
2304
2305 pdata->res->end -= 0x300;
2306 tasklet_kill(&pdata->hash_tasklet);
2307 pdata->use_hash = false;
2308 }
2309
2310 clk_disable_unprepare(pdata->clk);
2311 s5p_dev = NULL;
2312
2313 return 0;
2314 }
2315
2316 static struct platform_driver s5p_aes_crypto = {
2317 .probe = s5p_aes_probe,
2318 .remove = s5p_aes_remove,
2319 .driver = {
2320 .name = "s5p-secss",
2321 .of_match_table = s5p_sss_dt_match,
2322 },
2323 };
2324
2325 module_platform_driver(s5p_aes_crypto);
2326
2327 MODULE_DESCRIPTION("S5PV210 AES hw acceleration support.");
2328 MODULE_LICENSE("GPL v2");
2329 MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>");
2330 MODULE_AUTHOR("Kamil Konieczny <k.konieczny@partner.samsung.com>");
Linux with added FPC-III support