drivers/hwmon/k10temp.c

   1 /*
   2  * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
   3  *
   4  * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
   5  *
   6  *
   7  * This driver is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This driver is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  14  * See the GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this driver; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/err.h>
  21 #include <linux/hwmon.h>
  22 #include <linux/hwmon-sysfs.h>
  23 #include <linux/init.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <asm/processor.h>
  27
  28 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
  29 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  30 MODULE_LICENSE("GPL");
  31
  32 static bool force;
  33 module_param(force, bool, 0444);
  34 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
  35
  36 /* Provide lock for writing to NB_SMU_IND_ADDR */
  37 static DEFINE_MUTEX(nb_smu_ind_mutex);
  38
  39 #ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
  40 #define PCI_DEVICE_ID_AMD_17H_DF_F3     0x1463
  41 #endif
  42
  43 /* CPUID function 0x80000001, ebx */
  44 #define CPUID_PKGTYPE_MASK      0xf0000000
  45 #define CPUID_PKGTYPE_F         0x00000000
  46 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
  47
  48 /* DRAM controller (PCI function 2) */
  49 #define REG_DCT0_CONFIG_HIGH            0x094
  50 #define  DDR3_MODE                      0x00000100
  51
  52 /* miscellaneous (PCI function 3) */
  53 #define REG_HARDWARE_THERMAL_CONTROL    0x64
  54 #define  HTC_ENABLE                     0x00000001
  55
  56 #define REG_REPORTED_TEMPERATURE        0xa4
  57
  58 #define REG_NORTHBRIDGE_CAPABILITIES    0xe8
  59 #define  NB_CAP_HTC                     0x00000400
  60
  61 /*
  62  * For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
  63  * has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
  64  * Control]
  65  */
  66 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET     0xd8200ca4
  67
  68 /* F17h M01h Access througn SMN */
  69 #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET     0x00059800
  70
  71 struct k10temp_data {
  72         struct pci_dev *pdev;
  73         void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
  74         int temp_offset;
  75 };
  76
  77 struct tctl_offset {
  78         u8 model;
  79         char const *id;
  80         int offset;
  81 };
  82
  83 static const struct tctl_offset tctl_offset_table[] = {
  84         { 0x17, "AMD Ryzen 5 1600X", 20000 },
  85         { 0x17, "AMD Ryzen 7 1700X", 20000 },
  86         { 0x17, "AMD Ryzen 7 1800X", 20000 },
  87         { 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
  88         { 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
  89         { 0x17, "AMD Ryzen Threadripper 1950", 10000 },
  90         { 0x17, "AMD Ryzen Threadripper 1920", 10000 },
  91         { 0x17, "AMD Ryzen Threadripper 1910", 10000 },
  92 };
  93
  94 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
  95 {
  96         pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
  97 }
  98
  99 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
 100                               unsigned int base, int offset, u32 *val)
 101 {
 102         mutex_lock(&nb_smu_ind_mutex);
 103         pci_bus_write_config_dword(pdev->bus, devfn,
 104                                    base, offset);
 105         pci_bus_read_config_dword(pdev->bus, devfn,
 106                                   base + 4, val);
 107         mutex_unlock(&nb_smu_ind_mutex);
 108 }
 109
 110 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
 111 {
 112         amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
 113                           F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
 114 }
 115
 116 static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
 117 {
 118         amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0x60,
 119                           F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
 120 }
 121
 122 static ssize_t temp1_input_show(struct device *dev,
 123                                 struct device_attribute *attr, char *buf)
 124 {
 125         struct k10temp_data *data = dev_get_drvdata(dev);
 126         u32 regval;
 127         unsigned int temp;
 128
 129         data->read_tempreg(data->pdev, &regval);
 130         temp = (regval >> 21) * 125;
 131         temp -= data->temp_offset;
 132
 133         return sprintf(buf, "%u\n", temp);
 134 }
 135
 136 static ssize_t temp1_max_show(struct device *dev,
 137                               struct device_attribute *attr, char *buf)
 138 {
 139         return sprintf(buf, "%d\n", 70 * 1000);
 140 }
 141
 142 static ssize_t show_temp_crit(struct device *dev,
 143                               struct device_attribute *devattr, char *buf)
 144 {
 145         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
 146         struct k10temp_data *data = dev_get_drvdata(dev);
 147         int show_hyst = attr->index;
 148         u32 regval;
 149         int value;
 150
 151         pci_read_config_dword(data->pdev,
 152                               REG_HARDWARE_THERMAL_CONTROL, &regval);
 153         value = ((regval >> 16) & 0x7f) * 500 + 52000;
 154         if (show_hyst)
 155                 value -= ((regval >> 24) & 0xf) * 500;
 156         return sprintf(buf, "%d\n", value);
 157 }
 158
 159 static DEVICE_ATTR_RO(temp1_input);
 160 static DEVICE_ATTR_RO(temp1_max);
 161 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
 162 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
 163
 164 static umode_t k10temp_is_visible(struct kobject *kobj,
 165                                   struct attribute *attr, int index)
 166 {
 167         struct device *dev = container_of(kobj, struct device, kobj);
 168         struct k10temp_data *data = dev_get_drvdata(dev);
 169         struct pci_dev *pdev = data->pdev;
 170
 171         if (index >= 2) {
 172                 u32 reg_caps, reg_htc;
 173
 174                 pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
 175                                       &reg_caps);
 176                 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL,
 177                                       &reg_htc);
 178                 if (!(reg_caps & NB_CAP_HTC) || !(reg_htc & HTC_ENABLE))
 179                         return 0;
 180         }
 181         return attr->mode;
 182 }
 183
 184 static struct attribute *k10temp_attrs[] = {
 185         &dev_attr_temp1_input.attr,
 186         &dev_attr_temp1_max.attr,
 187         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 188         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 189         NULL
 190 };
 191
 192 static const struct attribute_group k10temp_group = {
 193         .attrs = k10temp_attrs,
 194         .is_visible = k10temp_is_visible,
 195 };
 196 __ATTRIBUTE_GROUPS(k10temp);
 197
 198 static bool has_erratum_319(struct pci_dev *pdev)
 199 {
 200         u32 pkg_type, reg_dram_cfg;
 201
 202         if (boot_cpu_data.x86 != 0x10)
 203                 return false;
 204
 205         /*
 206          * Erratum 319: The thermal sensor of Socket F/AM2+ processors
 207          *              may be unreliable.
 208          */
 209         pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
 210         if (pkg_type == CPUID_PKGTYPE_F)
 211                 return true;
 212         if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
 213                 return false;
 214
 215         /* DDR3 memory implies socket AM3, which is good */
 216         pci_bus_read_config_dword(pdev->bus,
 217                                   PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
 218                                   REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
 219         if (reg_dram_cfg & DDR3_MODE)
 220                 return false;
 221
 222         /*
 223          * Unfortunately it is possible to run a socket AM3 CPU with DDR2
 224          * memory. We blacklist all the cores which do exist in socket AM2+
 225          * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
 226          * and AM3 formats, but that's the best we can do.
 227          */
 228         return boot_cpu_data.x86_model < 4 ||
 229                (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
 230 }
 231
 232 static int k10temp_probe(struct pci_dev *pdev,
 233                                    const struct pci_device_id *id)
 234 {
 235         int unreliable = has_erratum_319(pdev);
 236         struct device *dev = &pdev->dev;
 237         struct k10temp_data *data;
 238         struct device *hwmon_dev;
 239         int i;
 240
 241         if (unreliable) {
 242                 if (!force) {
 243                         dev_err(dev,
 244                                 "unreliable CPU thermal sensor; monitoring disabled\n");
 245                         return -ENODEV;
 246                 }
 247                 dev_warn(dev,
 248                          "unreliable CPU thermal sensor; check erratum 319\n");
 249         }
 250
 251         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 252         if (!data)
 253                 return -ENOMEM;
 254
 255         data->pdev = pdev;
 256
 257         if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
 258                                           boot_cpu_data.x86_model == 0x70))
 259                 data->read_tempreg = read_tempreg_nb_f15;
 260         else if (boot_cpu_data.x86 == 0x17)
 261                 data->read_tempreg = read_tempreg_nb_f17;
 262         else
 263                 data->read_tempreg = read_tempreg_pci;
 264
 265         for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
 266                 const struct tctl_offset *entry = &tctl_offset_table[i];
 267
 268                 if (boot_cpu_data.x86 == entry->model &&
 269                     strstr(boot_cpu_data.x86_model_id, entry->id)) {
 270                         data->temp_offset = entry->offset;
 271                         break;
 272                 }
 273         }
 274
 275         hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
 276                                                            k10temp_groups);
 277         return PTR_ERR_OR_ZERO(hwmon_dev);
 278 }
 279
 280 static const struct pci_device_id k10temp_id_table[] = {
 281         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
 282         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
 283         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
 284         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
 285         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
 286         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
 287         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
 288         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
 289         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
 290         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 291         {}
 292 };
 293 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
 294
 295 static struct pci_driver k10temp_driver = {
 296         .name = "k10temp",
 297         .id_table = k10temp_id_table,
 298         .probe = k10temp_probe,
 299 };
 300
 301 module_pci_driver(k10temp_driver);