drivers/soc/samsung/exynos5420-pmu.c

   1 /*
   2  * Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com/
   4  *
   5  * EXYNOS5420 - CPU PMU (Power Management Unit) support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/pm.h>
  13 #include <linux/soc/samsung/exynos-regs-pmu.h>
  14 #include <linux/soc/samsung/exynos-pmu.h>
  15
  16 #include <asm/cputype.h>
  17
  18 #include "exynos-pmu.h"
  19
  20 static const struct exynos_pmu_conf exynos5420_pmu_config[] = {
  21         /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
  22         { EXYNOS5_ARM_CORE0_SYS_PWR_REG,                { 0x0, 0x0, 0x0} },
  23         { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
  24         { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  25         { EXYNOS5_ARM_CORE1_SYS_PWR_REG,                { 0x0, 0x0, 0x0} },
  26         { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
  27         { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  28         { EXYNOS5420_ARM_CORE2_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
  29         { EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  30         { EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  31         { EXYNOS5420_ARM_CORE3_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
  32         { EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  33         { EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  34         { EXYNOS5420_KFC_CORE0_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
  35         { EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  36         { EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  37         { EXYNOS5420_KFC_CORE1_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
  38         { EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  39         { EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  40         { EXYNOS5420_KFC_CORE2_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
  41         { EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  42         { EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  43         { EXYNOS5420_KFC_CORE3_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
  44         { EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  45         { EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  46         { EXYNOS5_ISP_ARM_SYS_PWR_REG,                  { 0x1, 0x0, 0x0} },
  47         { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,    { 0x1, 0x0, 0x0} },
  48         { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,  { 0x1, 0x0, 0x0} },
  49         { EXYNOS5420_ARM_COMMON_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
  50         { EXYNOS5420_KFC_COMMON_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
  51         { EXYNOS5_ARM_L2_SYS_PWR_REG,                   { 0x0, 0x0, 0x0} },
  52         { EXYNOS5420_KFC_L2_SYS_PWR_REG,                { 0x0, 0x0, 0x0} },
  53         { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,             { 0x1, 0x0, 0x0} },
  54         { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,             { 0x1, 0x0, 0x1} },
  55         { EXYNOS5_CMU_RESET_SYS_PWR_REG,                { 0x1, 0x1, 0x0} },
  56         { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
  57         { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,      { 0x1, 0x0, 0x1} },
  58         { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,         { 0x1, 0x1, 0x0} },
  59         { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,           { 0x1, 0x0, 0x1} },
  60         { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,            { 0x1, 0x1, 0x1} },
  61         { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,           { 0x1, 0x0, 0x1} },
  62         { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
  63         { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
  64         { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
  65         { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x1, 0x0} },
  66         { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
  67         { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
  68         { EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
  69         { EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
  70         { EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
  71         { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
  72         { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
  73         { EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
  74         { EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
  75         { EXYNOS5_TOP_BUS_SYS_PWR_REG,                  { 0x3, 0x0, 0x0} },
  76         { EXYNOS5_TOP_RETENTION_SYS_PWR_REG,            { 0x1, 0x1, 0x1} },
  77         { EXYNOS5_TOP_PWR_SYS_PWR_REG,                  { 0x3, 0x3, 0x0} },
  78         { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG,           { 0x3, 0x0, 0x0} },
  79         { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG,     { 0x1, 0x0, 0x1} },
  80         { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG,           { 0x3, 0x0, 0x0} },
  81         { EXYNOS5_LOGIC_RESET_SYS_PWR_REG,              { 0x1, 0x1, 0x0} },
  82         { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG,              { 0x1, 0x0, 0x1} },
  83         { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
  84         { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
  85         { EXYNOS5420_INTRAM_MEM_SYS_PWR_REG,            { 0x3, 0x0, 0x3} },
  86         { EXYNOS5420_INTROM_MEM_SYS_PWR_REG,            { 0x3, 0x0, 0x3} },
  87         { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
  88         { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
  89         { EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG,    { 0x1, 0x1, 0x0} },
  90         { EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG,    { 0x1, 0x0, 0x0} },
  91         { EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG,    { 0x1, 0x0, 0x0} },
  92         { EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG,    { 0x1, 0x0, 0x0} },
  93         { EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG,    { 0x1, 0x0, 0x0} },
  94         { EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG,    { 0x1, 0x0, 0x0} },
  95         { EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
  96         { EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG,    { 0x1, 0x0, 0x0} },
  97         { EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG,    { 0x1, 0x0, 0x0} },
  98         { EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
  99         { EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
 100         { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
 101         { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
 102         { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
 103         { EXYNOS5_XUSBXTI_SYS_PWR_REG,                  { 0x1, 0x1, 0x0} },
 104         { EXYNOS5_XXTI_SYS_PWR_REG,                     { 0x1, 0x1, 0x0} },
 105         { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
 106         { EXYNOS5_GPIO_MODE_SYS_PWR_REG,                { 0x1, 0x0, 0x0} },
 107         { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG,         { 0x1, 0x1, 0x0} },
 108         { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
 109         { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
 110         { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
 111         { EXYNOS5_GSCL_SYS_PWR_REG,                     { 0x7, 0x0, 0x0} },
 112         { EXYNOS5_ISP_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
 113         { EXYNOS5_MFC_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
 114         { EXYNOS5_G3D_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
 115         { EXYNOS5420_DISP1_SYS_PWR_REG,                 { 0x7, 0x0, 0x0} },
 116         { EXYNOS5420_MAU_SYS_PWR_REG,                   { 0x7, 0x7, 0x0} },
 117         { EXYNOS5420_G2D_SYS_PWR_REG,                   { 0x7, 0x0, 0x0} },
 118         { EXYNOS5420_MSC_SYS_PWR_REG,                   { 0x7, 0x0, 0x0} },
 119         { EXYNOS5420_FSYS_SYS_PWR_REG,                  { 0x7, 0x0, 0x0} },
 120         { EXYNOS5420_FSYS2_SYS_PWR_REG,                 { 0x7, 0x0, 0x0} },
 121         { EXYNOS5420_PSGEN_SYS_PWR_REG,                 { 0x7, 0x0, 0x0} },
 122         { EXYNOS5420_PERIC_SYS_PWR_REG,                 { 0x7, 0x0, 0x0} },
 123         { EXYNOS5420_WCORE_SYS_PWR_REG,                 { 0x7, 0x0, 0x0} },
 124         { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,         { 0x0, 0x0, 0x0} },
 125         { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
 126         { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
 127         { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
 128         { EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
 129         { EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 130         { EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 131         { EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 132         { EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG,      { 0x0, 0x0, 0x0} },
 133         { EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
 134         { EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
 135         { EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
 136         { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
 137         { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
 138         { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
 139         { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
 140         { EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG,      { 0x0, 0x0, 0x0} },
 141         { EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
 142         { EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
 143         { EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
 144         { EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 145         { EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG,      { 0x0, 0x0, 0x0} },
 146         { EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG,      { 0x0, 0x0, 0x0} },
 147         { EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG,      { 0x0, 0x0, 0x0} },
 148         { EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG,      { 0x0, 0x0, 0x0} },
 149         { EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 150         { EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 151         { EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 152         { EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 153         { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
 154         { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
 155         { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
 156         { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
 157         { EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 158         { EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG,         { 0x0, 0x0, 0x0} },
 159         { EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG,         { 0x0, 0x0, 0x0} },
 160         { EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG,         { 0x0, 0x0, 0x0} },
 161         { EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
 162         { PMU_TABLE_END,},
 163 };
 164
 165 static unsigned int const exynos5420_list_disable_pmu_reg[] = {
 166         EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
 167         EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
 168         EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
 169         EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
 170         EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG,
 171         EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG,
 172         EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG,
 173         EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG,
 174         EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG,
 175         EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG,
 176         EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG,
 177         EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
 178         EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
 179         EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
 180         EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG,
 181         EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG,
 182         EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG,
 183         EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG,
 184         EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG,
 185         EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG,
 186         EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG,
 187         EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG,
 188         EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG,
 189         EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG,
 190         EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG,
 191         EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG,
 192         EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG,
 193         EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
 194         EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,
 195         EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
 196         EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG,
 197         EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG,
 198         EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG,
 199         EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG,
 200         EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
 201 };
 202
 203 static void exynos5420_powerdown_conf(enum sys_powerdown mode)
 204 {
 205         u32 this_cluster;
 206
 207         this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
 208
 209         /*
 210          * set the cluster id to IROM register to ensure that we wake
 211          * up with the current cluster.
 212          */
 213         pmu_raw_writel(this_cluster, EXYNOS_IROM_DATA2);
 214 }
 215
 216 static void exynos5420_pmu_init(void)
 217 {
 218         unsigned int value;
 219         int i;
 220
 221         /*
 222          * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers
 223          * for local power blocks to Low initially as per Table 8-4:
 224          * "System-Level Power-Down Configuration Registers".
 225          */
 226         for (i = 0; i < ARRAY_SIZE(exynos5420_list_disable_pmu_reg); i++)
 227                 pmu_raw_writel(0, exynos5420_list_disable_pmu_reg[i]);
 228
 229         /* Enable USE_STANDBY_WFI for all CORE */
 230         pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
 231
 232         value  = pmu_raw_readl(EXYNOS_L2_OPTION(0));
 233         value &= ~EXYNOS_L2_USE_RETENTION;
 234         pmu_raw_writel(value, EXYNOS_L2_OPTION(0));
 235
 236         value = pmu_raw_readl(EXYNOS_L2_OPTION(1));
 237         value &= ~EXYNOS_L2_USE_RETENTION;
 238         pmu_raw_writel(value, EXYNOS_L2_OPTION(1));
 239
 240         /*
 241          * If L2_COMMON is turned off, clocks related to ATB async
 242          * bridge are gated. Thus, when ISP power is gated, LPI
 243          * may get stuck.
 244          */
 245         value = pmu_raw_readl(EXYNOS5420_LPI_MASK);
 246         value |= EXYNOS5420_ATB_ISP_ARM;
 247         pmu_raw_writel(value, EXYNOS5420_LPI_MASK);
 248
 249         value  = pmu_raw_readl(EXYNOS5420_LPI_MASK1);
 250         value |= EXYNOS5420_ATB_KFC;
 251         pmu_raw_writel(value, EXYNOS5420_LPI_MASK1);
 252
 253         /* Prevent issue of new bus request from L2 memory */
 254         value = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
 255         value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
 256         pmu_raw_writel(value, EXYNOS5420_ARM_COMMON_OPTION);
 257
 258         value = pmu_raw_readl(EXYNOS5420_KFC_COMMON_OPTION);
 259         value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
 260         pmu_raw_writel(value, EXYNOS5420_KFC_COMMON_OPTION);
 261
 262         /* This setting is to reduce suspend/resume time */
 263         pmu_raw_writel(DUR_WAIT_RESET, EXYNOS5420_LOGIC_RESET_DURATION3);
 264
 265         /* Serialized CPU wakeup of Eagle */
 266         pmu_raw_writel(SPREAD_ENABLE, EXYNOS5420_ARM_INTR_SPREAD_ENABLE);
 267
 268         pmu_raw_writel(SPREAD_USE_STANDWFI,
 269                         EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI);
 270
 271         pmu_raw_writel(0x1, EXYNOS5420_UP_SCHEDULER);
 272
 273         pr_info("EXYNOS5420 PMU initialized\n");
 274 }
 275
 276 const struct exynos_pmu_data exynos5420_pmu_data = {
 277         .pmu_config     = exynos5420_pmu_config,
 278         .pmu_init       = exynos5420_pmu_init,
 279         .powerdown_conf = exynos5420_powerdown_conf,
 280 };