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interconnect: qcom: Fix Kconfig indentation
[linux/fpc-iii.git] / drivers / gpio / gpio-mvebu.c
blob993bbeb3c0067f0f5c156ec5009d0799c36914e3
1 /*
2 * GPIO driver for Marvell SoCs
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
21 * block:
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
28 * registers.
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
33 * interrupts.
34 */
35
36 #include <linux/bitops.h>
37 #include <linux/clk.h>
38 #include <linux/err.h>
39 #include <linux/gpio/driver.h>
40 #include <linux/gpio/consumer.h>
41 #include <linux/gpio/machine.h>
42 #include <linux/init.h>
43 #include <linux/io.h>
44 #include <linux/irq.h>
45 #include <linux/irqchip/chained_irq.h>
46 #include <linux/irqdomain.h>
47 #include <linux/mfd/syscon.h>
48 #include <linux/of_device.h>
49 #include <linux/of_irq.h>
50 #include <linux/pinctrl/consumer.h>
51 #include <linux/platform_device.h>
52 #include <linux/pwm.h>
53 #include <linux/regmap.h>
54 #include <linux/slab.h>
55
56 /*
57 * GPIO unit register offsets.
58 */
59 #define GPIO_OUT_OFF 0x0000
60 #define GPIO_IO_CONF_OFF 0x0004
61 #define GPIO_BLINK_EN_OFF 0x0008
62 #define GPIO_IN_POL_OFF 0x000c
63 #define GPIO_DATA_IN_OFF 0x0010
64 #define GPIO_EDGE_CAUSE_OFF 0x0014
65 #define GPIO_EDGE_MASK_OFF 0x0018
66 #define GPIO_LEVEL_MASK_OFF 0x001c
67 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
68
69 /*
70 * PWM register offsets.
71 */
72 #define PWM_BLINK_ON_DURATION_OFF 0x0
73 #define PWM_BLINK_OFF_DURATION_OFF 0x4
74
75
76 /* The MV78200 has per-CPU registers for edge mask and level mask */
77 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
78 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
79
80 /*
81 * The Armada XP has per-CPU registers for interrupt cause, interrupt
82 * mask and interrupt level mask. Those are relative to the
83 * percpu_membase.
84 */
85 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
86 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
87 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
88
89 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
90 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
91 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
92 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
93
94 #define MVEBU_MAX_GPIO_PER_BANK 32
95
96 struct mvebu_pwm {
97 void __iomem *membase;
98 unsigned long clk_rate;
99 struct gpio_desc *gpiod;
100 struct pwm_chip chip;
101 spinlock_t lock;
102 struct mvebu_gpio_chip *mvchip;
103
104 /* Used to preserve GPIO/PWM registers across suspend/resume */
105 u32 blink_select;
106 u32 blink_on_duration;
107 u32 blink_off_duration;
108 };
109
110 struct mvebu_gpio_chip {
111 struct gpio_chip chip;
112 struct regmap *regs;
113 u32 offset;
114 struct regmap *percpu_regs;
115 int irqbase;
116 struct irq_domain *domain;
117 int soc_variant;
118
119 /* Used for PWM support */
120 struct clk *clk;
121 struct mvebu_pwm *mvpwm;
122
123 /* Used to preserve GPIO registers across suspend/resume */
124 u32 out_reg;
125 u32 io_conf_reg;
126 u32 blink_en_reg;
127 u32 in_pol_reg;
128 u32 edge_mask_regs[4];
129 u32 level_mask_regs[4];
130 };
131
132 /*
133 * Functions returning addresses of individual registers for a given
134 * GPIO controller.
135 */
136
137 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
138 struct regmap **map, unsigned int *offset)
139 {
140 int cpu;
141
142 switch (mvchip->soc_variant) {
143 case MVEBU_GPIO_SOC_VARIANT_ORION:
144 case MVEBU_GPIO_SOC_VARIANT_MV78200:
145 case MVEBU_GPIO_SOC_VARIANT_A8K:
146 *map = mvchip->regs;
147 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
148 break;
149 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
150 cpu = smp_processor_id();
151 *map = mvchip->percpu_regs;
152 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
153 break;
154 default:
155 BUG();
156 }
157 }
158
159 static u32
160 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
161 {
162 struct regmap *map;
163 unsigned int offset;
164 u32 val;
165
166 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
167 regmap_read(map, offset, &val);
168
169 return val;
170 }
171
172 static void
173 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
174 {
175 struct regmap *map;
176 unsigned int offset;
177
178 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
179 regmap_write(map, offset, val);
180 }
181
182 static inline void
183 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
184 struct regmap **map, unsigned int *offset)
185 {
186 int cpu;
187
188 switch (mvchip->soc_variant) {
189 case MVEBU_GPIO_SOC_VARIANT_ORION:
190 case MVEBU_GPIO_SOC_VARIANT_A8K:
191 *map = mvchip->regs;
192 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
193 break;
194 case MVEBU_GPIO_SOC_VARIANT_MV78200:
195 cpu = smp_processor_id();
196 *map = mvchip->regs;
197 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
198 break;
199 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
200 cpu = smp_processor_id();
201 *map = mvchip->percpu_regs;
202 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
203 break;
204 default:
205 BUG();
206 }
207 }
208
209 static u32
210 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
211 {
212 struct regmap *map;
213 unsigned int offset;
214 u32 val;
215
216 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
217 regmap_read(map, offset, &val);
218
219 return val;
220 }
221
222 static void
223 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
224 {
225 struct regmap *map;
226 unsigned int offset;
227
228 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
229 regmap_write(map, offset, val);
230 }
231
232 static void
233 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
234 struct regmap **map, unsigned int *offset)
235 {
236 int cpu;
237
238 switch (mvchip->soc_variant) {
239 case MVEBU_GPIO_SOC_VARIANT_ORION:
240 case MVEBU_GPIO_SOC_VARIANT_A8K:
241 *map = mvchip->regs;
242 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
243 break;
244 case MVEBU_GPIO_SOC_VARIANT_MV78200:
245 cpu = smp_processor_id();
246 *map = mvchip->regs;
247 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
248 break;
249 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
250 cpu = smp_processor_id();
251 *map = mvchip->percpu_regs;
252 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
253 break;
254 default:
255 BUG();
256 }
257 }
258
259 static u32
260 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
261 {
262 struct regmap *map;
263 unsigned int offset;
264 u32 val;
265
266 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
267 regmap_read(map, offset, &val);
268
269 return val;
270 }
271
272 static void
273 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
274 {
275 struct regmap *map;
276 unsigned int offset;
277
278 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
279 regmap_write(map, offset, val);
280 }
281
282 /*
283 * Functions returning addresses of individual registers for a given
284 * PWM controller.
285 */
286 static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
287 {
288 return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
289 }
290
291 static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
292 {
293 return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
294 }
295
296 /*
297 * Functions implementing the gpio_chip methods
298 */
299 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
300 {
301 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
302
303 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
304 BIT(pin), value ? BIT(pin) : 0);
305 }
306
307 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
308 {
309 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
310 u32 u;
311
312 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
313
314 if (u & BIT(pin)) {
315 u32 data_in, in_pol;
316
317 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
318 &data_in);
319 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
320 &in_pol);
321 u = data_in ^ in_pol;
322 } else {
323 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
324 }
325
326 return (u >> pin) & 1;
327 }
328
329 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
330 int value)
331 {
332 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
333
334 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
335 BIT(pin), value ? BIT(pin) : 0);
336 }
337
338 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
339 {
340 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
341 int ret;
342
343 /*
344 * Check with the pinctrl driver whether this pin is usable as
345 * an input GPIO
346 */
347 ret = pinctrl_gpio_direction_input(chip->base + pin);
348 if (ret)
349 return ret;
350
351 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
352 BIT(pin), BIT(pin));
353
354 return 0;
355 }
356
357 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
358 int value)
359 {
360 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
361 int ret;
362
363 /*
364 * Check with the pinctrl driver whether this pin is usable as
365 * an output GPIO
366 */
367 ret = pinctrl_gpio_direction_output(chip->base + pin);
368 if (ret)
369 return ret;
370
371 mvebu_gpio_blink(chip, pin, 0);
372 mvebu_gpio_set(chip, pin, value);
373
374 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
375 BIT(pin), 0);
376
377 return 0;
378 }
379
380 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
381 {
382 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
383 u32 u;
384
385 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
386
387 if (u & BIT(pin))
388 return GPIO_LINE_DIRECTION_IN;
389
390 return GPIO_LINE_DIRECTION_OUT;
391 }
392
393 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
394 {
395 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
396
397 return irq_create_mapping(mvchip->domain, pin);
398 }
399
400 /*
401 * Functions implementing the irq_chip methods
402 */
403 static void mvebu_gpio_irq_ack(struct irq_data *d)
404 {
405 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
406 struct mvebu_gpio_chip *mvchip = gc->private;
407 u32 mask = d->mask;
408
409 irq_gc_lock(gc);
410 mvebu_gpio_write_edge_cause(mvchip, ~mask);
411 irq_gc_unlock(gc);
412 }
413
414 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
415 {
416 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
417 struct mvebu_gpio_chip *mvchip = gc->private;
418 struct irq_chip_type *ct = irq_data_get_chip_type(d);
419 u32 mask = d->mask;
420
421 irq_gc_lock(gc);
422 ct->mask_cache_priv &= ~mask;
423 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
424 irq_gc_unlock(gc);
425 }
426
427 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
428 {
429 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
430 struct mvebu_gpio_chip *mvchip = gc->private;
431 struct irq_chip_type *ct = irq_data_get_chip_type(d);
432 u32 mask = d->mask;
433
434 irq_gc_lock(gc);
435 ct->mask_cache_priv |= mask;
436 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
437 irq_gc_unlock(gc);
438 }
439
440 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
441 {
442 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
443 struct mvebu_gpio_chip *mvchip = gc->private;
444 struct irq_chip_type *ct = irq_data_get_chip_type(d);
445 u32 mask = d->mask;
446
447 irq_gc_lock(gc);
448 ct->mask_cache_priv &= ~mask;
449 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
450 irq_gc_unlock(gc);
451 }
452
453 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
454 {
455 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
456 struct mvebu_gpio_chip *mvchip = gc->private;
457 struct irq_chip_type *ct = irq_data_get_chip_type(d);
458 u32 mask = d->mask;
459
460 irq_gc_lock(gc);
461 ct->mask_cache_priv |= mask;
462 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
463 irq_gc_unlock(gc);
464 }
465
466 /*****************************************************************************
467 * MVEBU GPIO IRQ
468 *
469 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
470 * value of the line or the opposite value.
471 *
472 * Level IRQ handlers: DATA_IN is used directly as cause register.
473 * Interrupt are masked by LEVEL_MASK registers.
474 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
475 * Interrupt are masked by EDGE_MASK registers.
476 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
477 * the polarity to catch the next line transaction.
478 * This is a race condition that might not perfectly
479 * work on some use cases.
480 *
481 * Every eight GPIO lines are grouped (OR'ed) before going up to main
482 * cause register.
483 *
484 * EDGE cause mask
485 * data-in /--------| |-----| |----\
486 * -----| |----- ---- to main cause reg
487 * X \----------------| |----/
488 * polarity LEVEL mask
489 *
490 ****************************************************************************/
491
492 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
493 {
494 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
495 struct irq_chip_type *ct = irq_data_get_chip_type(d);
496 struct mvebu_gpio_chip *mvchip = gc->private;
497 int pin;
498 u32 u;
499
500 pin = d->hwirq;
501
502 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
503 if ((u & BIT(pin)) == 0)
504 return -EINVAL;
505
506 type &= IRQ_TYPE_SENSE_MASK;
507 if (type == IRQ_TYPE_NONE)
508 return -EINVAL;
509
510 /* Check if we need to change chip and handler */
511 if (!(ct->type & type))
512 if (irq_setup_alt_chip(d, type))
513 return -EINVAL;
514
515 /*
516 * Configure interrupt polarity.
517 */
518 switch (type) {
519 case IRQ_TYPE_EDGE_RISING:
520 case IRQ_TYPE_LEVEL_HIGH:
521 regmap_update_bits(mvchip->regs,
522 GPIO_IN_POL_OFF + mvchip->offset,
523 BIT(pin), 0);
524 break;
525 case IRQ_TYPE_EDGE_FALLING:
526 case IRQ_TYPE_LEVEL_LOW:
527 regmap_update_bits(mvchip->regs,
528 GPIO_IN_POL_OFF + mvchip->offset,
529 BIT(pin), BIT(pin));
530 break;
531 case IRQ_TYPE_EDGE_BOTH: {
532 u32 data_in, in_pol, val;
533
534 regmap_read(mvchip->regs,
535 GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
536 regmap_read(mvchip->regs,
537 GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
538
539 /*
540 * set initial polarity based on current input level
541 */
542 if ((data_in ^ in_pol) & BIT(pin))
543 val = BIT(pin); /* falling */
544 else
545 val = 0; /* raising */
546
547 regmap_update_bits(mvchip->regs,
548 GPIO_IN_POL_OFF + mvchip->offset,
549 BIT(pin), val);
550 break;
551 }
552 }
553 return 0;
554 }
555
556 static void mvebu_gpio_irq_handler(struct irq_desc *desc)
557 {
558 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
559 struct irq_chip *chip = irq_desc_get_chip(desc);
560 u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
561 int i;
562
563 if (mvchip == NULL)
564 return;
565
566 chained_irq_enter(chip, desc);
567
568 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
569 level_mask = mvebu_gpio_read_level_mask(mvchip);
570 edge_cause = mvebu_gpio_read_edge_cause(mvchip);
571 edge_mask = mvebu_gpio_read_edge_mask(mvchip);
572
573 cause = (data_in & level_mask) | (edge_cause & edge_mask);
574
575 for (i = 0; i < mvchip->chip.ngpio; i++) {
576 int irq;
577
578 irq = irq_find_mapping(mvchip->domain, i);
579
580 if (!(cause & BIT(i)))
581 continue;
582
583 type = irq_get_trigger_type(irq);
584 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
585 /* Swap polarity (race with GPIO line) */
586 u32 polarity;
587
588 regmap_read(mvchip->regs,
589 GPIO_IN_POL_OFF + mvchip->offset,
590 &polarity);
591 polarity ^= BIT(i);
592 regmap_write(mvchip->regs,
593 GPIO_IN_POL_OFF + mvchip->offset,
594 polarity);
595 }
596
597 generic_handle_irq(irq);
598 }
599
600 chained_irq_exit(chip, desc);
601 }
602
603 /*
604 * Functions implementing the pwm_chip methods
605 */
606 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
607 {
608 return container_of(chip, struct mvebu_pwm, chip);
609 }
610
611 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
612 {
613 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
614 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
615 struct gpio_desc *desc;
616 unsigned long flags;
617 int ret = 0;
618
619 spin_lock_irqsave(&mvpwm->lock, flags);
620
621 if (mvpwm->gpiod) {
622 ret = -EBUSY;
623 } else {
624 desc = gpiochip_request_own_desc(&mvchip->chip,
625 pwm->hwpwm, "mvebu-pwm",
626 GPIO_ACTIVE_HIGH,
627 GPIOD_OUT_LOW);
628 if (IS_ERR(desc)) {
629 ret = PTR_ERR(desc);
630 goto out;
631 }
632
633 mvpwm->gpiod = desc;
634 }
635 out:
636 spin_unlock_irqrestore(&mvpwm->lock, flags);
637 return ret;
638 }
639
640 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
641 {
642 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
643 unsigned long flags;
644
645 spin_lock_irqsave(&mvpwm->lock, flags);
646 gpiochip_free_own_desc(mvpwm->gpiod);
647 mvpwm->gpiod = NULL;
648 spin_unlock_irqrestore(&mvpwm->lock, flags);
649 }
650
651 static void mvebu_pwm_get_state(struct pwm_chip *chip,
652 struct pwm_device *pwm,
653 struct pwm_state *state) {
654
655 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
656 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
657 unsigned long long val;
658 unsigned long flags;
659 u32 u;
660
661 spin_lock_irqsave(&mvpwm->lock, flags);
662
663 val = (unsigned long long)
664 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
665 val *= NSEC_PER_SEC;
666 do_div(val, mvpwm->clk_rate);
667 if (val > UINT_MAX)
668 state->duty_cycle = UINT_MAX;
669 else if (val)
670 state->duty_cycle = val;
671 else
672 state->duty_cycle = 1;
673
674 val = (unsigned long long)
675 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
676 val *= NSEC_PER_SEC;
677 do_div(val, mvpwm->clk_rate);
678 if (val < state->duty_cycle) {
679 state->period = 1;
680 } else {
681 val -= state->duty_cycle;
682 if (val > UINT_MAX)
683 state->period = UINT_MAX;
684 else if (val)
685 state->period = val;
686 else
687 state->period = 1;
688 }
689
690 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
691 if (u)
692 state->enabled = true;
693 else
694 state->enabled = false;
695
696 spin_unlock_irqrestore(&mvpwm->lock, flags);
697 }
698
699 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
700 const struct pwm_state *state)
701 {
702 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
703 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
704 unsigned long long val;
705 unsigned long flags;
706 unsigned int on, off;
707
708 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
709 do_div(val, NSEC_PER_SEC);
710 if (val > UINT_MAX)
711 return -EINVAL;
712 if (val)
713 on = val;
714 else
715 on = 1;
716
717 val = (unsigned long long) mvpwm->clk_rate *
718 (state->period - state->duty_cycle);
719 do_div(val, NSEC_PER_SEC);
720 if (val > UINT_MAX)
721 return -EINVAL;
722 if (val)
723 off = val;
724 else
725 off = 1;
726
727 spin_lock_irqsave(&mvpwm->lock, flags);
728
729 writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
730 writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
731 if (state->enabled)
732 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
733 else
734 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
735
736 spin_unlock_irqrestore(&mvpwm->lock, flags);
737
738 return 0;
739 }
740
741 static const struct pwm_ops mvebu_pwm_ops = {
742 .request = mvebu_pwm_request,
743 .free = mvebu_pwm_free,
744 .get_state = mvebu_pwm_get_state,
745 .apply = mvebu_pwm_apply,
746 .owner = THIS_MODULE,
747 };
748
749 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
750 {
751 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
752
753 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
754 &mvpwm->blink_select);
755 mvpwm->blink_on_duration =
756 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
757 mvpwm->blink_off_duration =
758 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
759 }
760
761 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
762 {
763 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
764
765 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
766 mvpwm->blink_select);
767 writel_relaxed(mvpwm->blink_on_duration,
768 mvebu_pwmreg_blink_on_duration(mvpwm));
769 writel_relaxed(mvpwm->blink_off_duration,
770 mvebu_pwmreg_blink_off_duration(mvpwm));
771 }
772
773 static int mvebu_pwm_probe(struct platform_device *pdev,
774 struct mvebu_gpio_chip *mvchip,
775 int id)
776 {
777 struct device *dev = &pdev->dev;
778 struct mvebu_pwm *mvpwm;
779 u32 set;
780
781 if (!of_device_is_compatible(mvchip->chip.of_node,
782 "marvell,armada-370-gpio"))
783 return 0;
784
785 if (IS_ERR(mvchip->clk))
786 return PTR_ERR(mvchip->clk);
787
788 /*
789 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
790 * with id 1. Don't allow further GPIO chips to be used for PWM.
791 */
792 if (id == 0)
793 set = 0;
794 else if (id == 1)
795 set = U32_MAX;
796 else
797 return -EINVAL;
798 regmap_write(mvchip->regs,
799 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
800
801 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
802 if (!mvpwm)
803 return -ENOMEM;
804 mvchip->mvpwm = mvpwm;
805 mvpwm->mvchip = mvchip;
806
807 /*
808 * There are only two sets of PWM configuration registers for
809 * all the GPIO lines on those SoCs which this driver reserves
810 * for the first two GPIO chips. So if the resource is missing
811 * we can't treat it as an error.
812 */
813 mvpwm->membase = devm_platform_ioremap_resource_byname(pdev, "pwm");
814 if (IS_ERR(mvpwm->membase))
815 return PTR_ERR(mvpwm->membase);
816
817 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
818 if (!mvpwm->clk_rate) {
819 dev_err(dev, "failed to get clock rate\n");
820 return -EINVAL;
821 }
822
823 mvpwm->chip.dev = dev;
824 mvpwm->chip.ops = &mvebu_pwm_ops;
825 mvpwm->chip.npwm = mvchip->chip.ngpio;
826 /*
827 * There may already be some PWM allocated, so we can't force
828 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
829 * So, we let pwmchip_add() do the numbering and take the next free
830 * region.
831 */
832 mvpwm->chip.base = -1;
833
834 spin_lock_init(&mvpwm->lock);
835
836 return pwmchip_add(&mvpwm->chip);
837 }
838
839 #ifdef CONFIG_DEBUG_FS
840 #include <linux/seq_file.h>
841
842 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
843 {
844 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
845 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
846 int i;
847
848 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
849 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
850 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
851 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
852 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
853 cause = mvebu_gpio_read_edge_cause(mvchip);
854 edg_msk = mvebu_gpio_read_edge_mask(mvchip);
855 lvl_msk = mvebu_gpio_read_level_mask(mvchip);
856
857 for (i = 0; i < chip->ngpio; i++) {
858 const char *label;
859 u32 msk;
860 bool is_out;
861
862 label = gpiochip_is_requested(chip, i);
863 if (!label)
864 continue;
865
866 msk = BIT(i);
867 is_out = !(io_conf & msk);
868
869 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
870
871 if (is_out) {
872 seq_printf(s, " out %s %s\n",
873 out & msk ? "hi" : "lo",
874 blink & msk ? "(blink )" : "");
875 continue;
876 }
877
878 seq_printf(s, " in %s (act %s) - IRQ",
879 (data_in ^ in_pol) & msk ? "hi" : "lo",
880 in_pol & msk ? "lo" : "hi");
881 if (!((edg_msk | lvl_msk) & msk)) {
882 seq_puts(s, " disabled\n");
883 continue;
884 }
885 if (edg_msk & msk)
886 seq_puts(s, " edge ");
887 if (lvl_msk & msk)
888 seq_puts(s, " level");
889 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
890 }
891 }
892 #else
893 #define mvebu_gpio_dbg_show NULL
894 #endif
895
896 static const struct of_device_id mvebu_gpio_of_match[] = {
897 {
898 .compatible = "marvell,orion-gpio",
899 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
900 },
901 {
902 .compatible = "marvell,mv78200-gpio",
903 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
904 },
905 {
906 .compatible = "marvell,armadaxp-gpio",
907 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
908 },
909 {
910 .compatible = "marvell,armada-370-gpio",
911 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
912 },
913 {
914 .compatible = "marvell,armada-8k-gpio",
915 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
916 },
917 {
918 /* sentinel */
919 },
920 };
921
922 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
923 {
924 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
925 int i;
926
927 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
928 &mvchip->out_reg);
929 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
930 &mvchip->io_conf_reg);
931 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
932 &mvchip->blink_en_reg);
933 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
934 &mvchip->in_pol_reg);
935
936 switch (mvchip->soc_variant) {
937 case MVEBU_GPIO_SOC_VARIANT_ORION:
938 case MVEBU_GPIO_SOC_VARIANT_A8K:
939 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
940 &mvchip->edge_mask_regs[0]);
941 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
942 &mvchip->level_mask_regs[0]);
943 break;
944 case MVEBU_GPIO_SOC_VARIANT_MV78200:
945 for (i = 0; i < 2; i++) {
946 regmap_read(mvchip->regs,
947 GPIO_EDGE_MASK_MV78200_OFF(i),
948 &mvchip->edge_mask_regs[i]);
949 regmap_read(mvchip->regs,
950 GPIO_LEVEL_MASK_MV78200_OFF(i),
951 &mvchip->level_mask_regs[i]);
952 }
953 break;
954 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
955 for (i = 0; i < 4; i++) {
956 regmap_read(mvchip->regs,
957 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
958 &mvchip->edge_mask_regs[i]);
959 regmap_read(mvchip->regs,
960 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
961 &mvchip->level_mask_regs[i]);
962 }
963 break;
964 default:
965 BUG();
966 }
967
968 if (IS_ENABLED(CONFIG_PWM))
969 mvebu_pwm_suspend(mvchip);
970
971 return 0;
972 }
973
974 static int mvebu_gpio_resume(struct platform_device *pdev)
975 {
976 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
977 int i;
978
979 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
980 mvchip->out_reg);
981 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
982 mvchip->io_conf_reg);
983 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
984 mvchip->blink_en_reg);
985 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
986 mvchip->in_pol_reg);
987
988 switch (mvchip->soc_variant) {
989 case MVEBU_GPIO_SOC_VARIANT_ORION:
990 case MVEBU_GPIO_SOC_VARIANT_A8K:
991 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
992 mvchip->edge_mask_regs[0]);
993 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
994 mvchip->level_mask_regs[0]);
995 break;
996 case MVEBU_GPIO_SOC_VARIANT_MV78200:
997 for (i = 0; i < 2; i++) {
998 regmap_write(mvchip->regs,
999 GPIO_EDGE_MASK_MV78200_OFF(i),
1000 mvchip->edge_mask_regs[i]);
1001 regmap_write(mvchip->regs,
1002 GPIO_LEVEL_MASK_MV78200_OFF(i),
1003 mvchip->level_mask_regs[i]);
1004 }
1005 break;
1006 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1007 for (i = 0; i < 4; i++) {
1008 regmap_write(mvchip->regs,
1009 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1010 mvchip->edge_mask_regs[i]);
1011 regmap_write(mvchip->regs,
1012 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1013 mvchip->level_mask_regs[i]);
1014 }
1015 break;
1016 default:
1017 BUG();
1018 }
1019
1020 if (IS_ENABLED(CONFIG_PWM))
1021 mvebu_pwm_resume(mvchip);
1022
1023 return 0;
1024 }
1025
1026 static const struct regmap_config mvebu_gpio_regmap_config = {
1027 .reg_bits = 32,
1028 .reg_stride = 4,
1029 .val_bits = 32,
1030 .fast_io = true,
1031 };
1032
1033 static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1034 struct mvebu_gpio_chip *mvchip)
1035 {
1036 void __iomem *base;
1037
1038 base = devm_platform_ioremap_resource(pdev, 0);
1039 if (IS_ERR(base))
1040 return PTR_ERR(base);
1041
1042 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1043 &mvebu_gpio_regmap_config);
1044 if (IS_ERR(mvchip->regs))
1045 return PTR_ERR(mvchip->regs);
1046
1047 /*
1048 * For the legacy SoCs, the regmap directly maps to the GPIO
1049 * registers, so no offset is needed.
1050 */
1051 mvchip->offset = 0;
1052
1053 /*
1054 * The Armada XP has a second range of registers for the
1055 * per-CPU registers
1056 */
1057 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1058 base = devm_platform_ioremap_resource(pdev, 1);
1059 if (IS_ERR(base))
1060 return PTR_ERR(base);
1061
1062 mvchip->percpu_regs =
1063 devm_regmap_init_mmio(&pdev->dev, base,
1064 &mvebu_gpio_regmap_config);
1065 if (IS_ERR(mvchip->percpu_regs))
1066 return PTR_ERR(mvchip->percpu_regs);
1067 }
1068
1069 return 0;
1070 }
1071
1072 static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1073 struct mvebu_gpio_chip *mvchip)
1074 {
1075 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1076 if (IS_ERR(mvchip->regs))
1077 return PTR_ERR(mvchip->regs);
1078
1079 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
1080 return -EINVAL;
1081
1082 return 0;
1083 }
1084
1085 static int mvebu_gpio_probe(struct platform_device *pdev)
1086 {
1087 struct mvebu_gpio_chip *mvchip;
1088 const struct of_device_id *match;
1089 struct device_node *np = pdev->dev.of_node;
1090 struct irq_chip_generic *gc;
1091 struct irq_chip_type *ct;
1092 unsigned int ngpios;
1093 bool have_irqs;
1094 int soc_variant;
1095 int i, cpu, id;
1096 int err;
1097
1098 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
1099 if (match)
1100 soc_variant = (unsigned long) match->data;
1101 else
1102 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
1103
1104 /* Some gpio controllers do not provide irq support */
1105 have_irqs = of_irq_count(np) != 0;
1106
1107 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1108 GFP_KERNEL);
1109 if (!mvchip)
1110 return -ENOMEM;
1111
1112 platform_set_drvdata(pdev, mvchip);
1113
1114 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
1115 dev_err(&pdev->dev, "Missing ngpios OF property\n");
1116 return -ENODEV;
1117 }
1118
1119 id = of_alias_get_id(pdev->dev.of_node, "gpio");
1120 if (id < 0) {
1121 dev_err(&pdev->dev, "Couldn't get OF id\n");
1122 return id;
1123 }
1124
1125 mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1126 /* Not all SoCs require a clock.*/
1127 if (!IS_ERR(mvchip->clk))
1128 clk_prepare_enable(mvchip->clk);
1129
1130 mvchip->soc_variant = soc_variant;
1131 mvchip->chip.label = dev_name(&pdev->dev);
1132 mvchip->chip.parent = &pdev->dev;
1133 mvchip->chip.request = gpiochip_generic_request;
1134 mvchip->chip.free = gpiochip_generic_free;
1135 mvchip->chip.get_direction = mvebu_gpio_get_direction;
1136 mvchip->chip.direction_input = mvebu_gpio_direction_input;
1137 mvchip->chip.get = mvebu_gpio_get;
1138 mvchip->chip.direction_output = mvebu_gpio_direction_output;
1139 mvchip->chip.set = mvebu_gpio_set;
1140 if (have_irqs)
1141 mvchip->chip.to_irq = mvebu_gpio_to_irq;
1142 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1143 mvchip->chip.ngpio = ngpios;
1144 mvchip->chip.can_sleep = false;
1145 mvchip->chip.of_node = np;
1146 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1147
1148 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1149 err = mvebu_gpio_probe_syscon(pdev, mvchip);
1150 else
1151 err = mvebu_gpio_probe_raw(pdev, mvchip);
1152
1153 if (err)
1154 return err;
1155
1156 /*
1157 * Mask and clear GPIO interrupts.
1158 */
1159 switch (soc_variant) {
1160 case MVEBU_GPIO_SOC_VARIANT_ORION:
1161 case MVEBU_GPIO_SOC_VARIANT_A8K:
1162 regmap_write(mvchip->regs,
1163 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1164 regmap_write(mvchip->regs,
1165 GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1166 regmap_write(mvchip->regs,
1167 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1168 break;
1169 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1170 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1171 for (cpu = 0; cpu < 2; cpu++) {
1172 regmap_write(mvchip->regs,
1173 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
1174 regmap_write(mvchip->regs,
1175 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1176 }
1177 break;
1178 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1179 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1180 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1181 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1182 for (cpu = 0; cpu < 4; cpu++) {
1183 regmap_write(mvchip->percpu_regs,
1184 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
1185 regmap_write(mvchip->percpu_regs,
1186 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
1187 regmap_write(mvchip->percpu_regs,
1188 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1189 }
1190 break;
1191 default:
1192 BUG();
1193 }
1194
1195 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1196
1197 /* Some gpio controllers do not provide irq support */
1198 if (!have_irqs)
1199 return 0;
1200
1201 mvchip->domain =
1202 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
1203 if (!mvchip->domain) {
1204 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1205 mvchip->chip.label);
1206 return -ENODEV;
1207 }
1208
1209 err = irq_alloc_domain_generic_chips(
1210 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1211 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1212 if (err) {
1213 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1214 mvchip->chip.label);
1215 goto err_domain;
1216 }
1217
1218 /*
1219 * NOTE: The common accessors cannot be used because of the percpu
1220 * access to the mask registers
1221 */
1222 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1223 gc->private = mvchip;
1224 ct = &gc->chip_types[0];
1225 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1226 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1227 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1228 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1229 ct->chip.name = mvchip->chip.label;
1230
1231 ct = &gc->chip_types[1];
1232 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1233 ct->chip.irq_ack = mvebu_gpio_irq_ack;
1234 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1235 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1236 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1237 ct->handler = handle_edge_irq;
1238 ct->chip.name = mvchip->chip.label;
1239
1240 /*
1241 * Setup the interrupt handlers. Each chip can have up to 4
1242 * interrupt handlers, with each handler dealing with 8 GPIO
1243 * pins.
1244 */
1245 for (i = 0; i < 4; i++) {
1246 int irq = platform_get_irq(pdev, i);
1247
1248 if (irq < 0)
1249 continue;
1250 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1251 mvchip);
1252 }
1253
1254 /* Some MVEBU SoCs have simple PWM support for GPIO lines */
1255 if (IS_ENABLED(CONFIG_PWM))
1256 return mvebu_pwm_probe(pdev, mvchip, id);
1257
1258 return 0;
1259
1260 err_domain:
1261 irq_domain_remove(mvchip->domain);
1262
1263 return err;
1264 }
1265
1266 static struct platform_driver mvebu_gpio_driver = {
1267 .driver = {
1268 .name = "mvebu-gpio",
1269 .of_match_table = mvebu_gpio_of_match,
1270 },
1271 .probe = mvebu_gpio_probe,
1272 .suspend = mvebu_gpio_suspend,
1273 .resume = mvebu_gpio_resume,
1274 };
1275 builtin_platform_driver(mvebu_gpio_driver);
Linux with added FPC-III support