drivers/iio/adc/ad7124.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AD7124 SPI ADC driver
   4  *
   5  * Copyright 2018 Analog Devices Inc.
   6  */
   7 #include <linux/bitfield.h>
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/err.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/spi/spi.h>
  16
  17 #include <linux/iio/iio.h>
  18 #include <linux/iio/adc/ad_sigma_delta.h>
  19 #include <linux/iio/sysfs.h>
  20
  21 /* AD7124 registers */
  22 #define AD7124_COMMS                    0x00
  23 #define AD7124_STATUS                   0x00
  24 #define AD7124_ADC_CONTROL              0x01
  25 #define AD7124_DATA                     0x02
  26 #define AD7124_IO_CONTROL_1             0x03
  27 #define AD7124_IO_CONTROL_2             0x04
  28 #define AD7124_ID                       0x05
  29 #define AD7124_ERROR                    0x06
  30 #define AD7124_ERROR_EN         0x07
  31 #define AD7124_MCLK_COUNT               0x08
  32 #define AD7124_CHANNEL(x)               (0x09 + (x))
  33 #define AD7124_CONFIG(x)                (0x19 + (x))
  34 #define AD7124_FILTER(x)                (0x21 + (x))
  35 #define AD7124_OFFSET(x)                (0x29 + (x))
  36 #define AD7124_GAIN(x)                  (0x31 + (x))
  37
  38 /* AD7124_STATUS */
  39 #define AD7124_STATUS_POR_FLAG_MSK      BIT(4)
  40
  41 /* AD7124_ADC_CONTROL */
  42 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
  43 #define AD7124_ADC_CTRL_PWR(x)          FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
  44 #define AD7124_ADC_CTRL_MODE_MSK        GENMASK(5, 2)
  45 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
  46
  47 /* AD7124_CHANNEL_X */
  48 #define AD7124_CHANNEL_EN_MSK           BIT(15)
  49 #define AD7124_CHANNEL_EN(x)            FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
  50 #define AD7124_CHANNEL_SETUP_MSK        GENMASK(14, 12)
  51 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
  52 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
  53 #define AD7124_CHANNEL_AINP(x)          FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
  54 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
  55 #define AD7124_CHANNEL_AINM(x)          FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
  56
  57 /* AD7124_CONFIG_X */
  58 #define AD7124_CONFIG_BIPOLAR_MSK       BIT(11)
  59 #define AD7124_CONFIG_BIPOLAR(x)        FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
  60 #define AD7124_CONFIG_REF_SEL_MSK       GENMASK(4, 3)
  61 #define AD7124_CONFIG_REF_SEL(x)        FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
  62 #define AD7124_CONFIG_PGA_MSK           GENMASK(2, 0)
  63 #define AD7124_CONFIG_PGA(x)            FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
  64 #define AD7124_CONFIG_IN_BUFF_MSK       GENMASK(7, 6)
  65 #define AD7124_CONFIG_IN_BUFF(x)        FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
  66
  67 /* AD7124_FILTER_X */
  68 #define AD7124_FILTER_FS_MSK            GENMASK(10, 0)
  69 #define AD7124_FILTER_FS(x)             FIELD_PREP(AD7124_FILTER_FS_MSK, x)
  70
  71 enum ad7124_ids {
  72         ID_AD7124_4,
  73         ID_AD7124_8,
  74 };
  75
  76 enum ad7124_ref_sel {
  77         AD7124_REFIN1,
  78         AD7124_REFIN2,
  79         AD7124_INT_REF,
  80         AD7124_AVDD_REF,
  81 };
  82
  83 enum ad7124_power_mode {
  84         AD7124_LOW_POWER,
  85         AD7124_MID_POWER,
  86         AD7124_FULL_POWER,
  87 };
  88
  89 static const unsigned int ad7124_gain[8] = {
  90         1, 2, 4, 8, 16, 32, 64, 128
  91 };
  92
  93 static const int ad7124_master_clk_freq_hz[3] = {
  94         [AD7124_LOW_POWER] = 76800,
  95         [AD7124_MID_POWER] = 153600,
  96         [AD7124_FULL_POWER] = 614400,
  97 };
  98
  99 static const char * const ad7124_ref_names[] = {
 100         [AD7124_REFIN1] = "refin1",
 101         [AD7124_REFIN2] = "refin2",
 102         [AD7124_INT_REF] = "int",
 103         [AD7124_AVDD_REF] = "avdd",
 104 };
 105
 106 struct ad7124_chip_info {
 107         unsigned int num_inputs;
 108 };
 109
 110 struct ad7124_channel_config {
 111         enum ad7124_ref_sel refsel;
 112         bool bipolar;
 113         bool buf_positive;
 114         bool buf_negative;
 115         unsigned int ain;
 116         unsigned int vref_mv;
 117         unsigned int pga_bits;
 118         unsigned int odr;
 119 };
 120
 121 struct ad7124_state {
 122         const struct ad7124_chip_info *chip_info;
 123         struct ad_sigma_delta sd;
 124         struct ad7124_channel_config *channel_config;
 125         struct regulator *vref[4];
 126         struct clk *mclk;
 127         unsigned int adc_control;
 128         unsigned int num_channels;
 129 };
 130
 131 static const struct iio_chan_spec ad7124_channel_template = {
 132         .type = IIO_VOLTAGE,
 133         .indexed = 1,
 134         .differential = 1,
 135         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 136                 BIT(IIO_CHAN_INFO_SCALE) |
 137                 BIT(IIO_CHAN_INFO_OFFSET) |
 138                 BIT(IIO_CHAN_INFO_SAMP_FREQ),
 139         .scan_type = {
 140                 .sign = 'u',
 141                 .realbits = 24,
 142                 .storagebits = 32,
 143                 .shift = 8,
 144                 .endianness = IIO_BE,
 145         },
 146 };
 147
 148 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
 149         [ID_AD7124_4] = {
 150                 .num_inputs = 8,
 151         },
 152         [ID_AD7124_8] = {
 153                 .num_inputs = 16,
 154         },
 155 };
 156
 157 static int ad7124_find_closest_match(const int *array,
 158                                      unsigned int size, int val)
 159 {
 160         int i, idx;
 161         unsigned int diff_new, diff_old;
 162
 163         diff_old = U32_MAX;
 164         idx = 0;
 165
 166         for (i = 0; i < size; i++) {
 167                 diff_new = abs(val - array[i]);
 168                 if (diff_new < diff_old) {
 169                         diff_old = diff_new;
 170                         idx = i;
 171                 }
 172         }
 173
 174         return idx;
 175 }
 176
 177 static int ad7124_spi_write_mask(struct ad7124_state *st,
 178                                  unsigned int addr,
 179                                  unsigned long mask,
 180                                  unsigned int val,
 181                                  unsigned int bytes)
 182 {
 183         unsigned int readval;
 184         int ret;
 185
 186         ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
 187         if (ret < 0)
 188                 return ret;
 189
 190         readval &= ~mask;
 191         readval |= val;
 192
 193         return ad_sd_write_reg(&st->sd, addr, bytes, readval);
 194 }
 195
 196 static int ad7124_set_mode(struct ad_sigma_delta *sd,
 197                            enum ad_sigma_delta_mode mode)
 198 {
 199         struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
 200
 201         st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
 202         st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
 203
 204         return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
 205 }
 206
 207 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
 208 {
 209         struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
 210         unsigned int val;
 211
 212         val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
 213               AD7124_CHANNEL_SETUP(channel);
 214
 215         return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
 216 }
 217
 218 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
 219         .set_channel = ad7124_set_channel,
 220         .set_mode = ad7124_set_mode,
 221         .has_registers = true,
 222         .addr_shift = 0,
 223         .read_mask = BIT(6),
 224         .data_reg = AD7124_DATA,
 225 };
 226
 227 static int ad7124_set_channel_odr(struct ad7124_state *st,
 228                                   unsigned int channel,
 229                                   unsigned int odr)
 230 {
 231         unsigned int fclk, odr_sel_bits;
 232         int ret;
 233
 234         fclk = clk_get_rate(st->mclk);
 235         /*
 236          * FS[10:0] = fCLK / (fADC x 32) where:
 237          * fADC is the output data rate
 238          * fCLK is the master clock frequency
 239          * FS[10:0] are the bits in the filter register
 240          * FS[10:0] can have a value from 1 to 2047
 241          */
 242         odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
 243         if (odr_sel_bits < 1)
 244                 odr_sel_bits = 1;
 245         else if (odr_sel_bits > 2047)
 246                 odr_sel_bits = 2047;
 247
 248         ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
 249                                     AD7124_FILTER_FS_MSK,
 250                                     AD7124_FILTER_FS(odr_sel_bits), 3);
 251         if (ret < 0)
 252                 return ret;
 253         /* fADC = fCLK / (FS[10:0] x 32) */
 254         st->channel_config[channel].odr =
 255                 DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
 256
 257         return 0;
 258 }
 259
 260 static int ad7124_set_channel_gain(struct ad7124_state *st,
 261                                    unsigned int channel,
 262                                    unsigned int gain)
 263 {
 264         unsigned int res;
 265         int ret;
 266
 267         res = ad7124_find_closest_match(ad7124_gain,
 268                                         ARRAY_SIZE(ad7124_gain), gain);
 269         ret = ad7124_spi_write_mask(st, AD7124_CONFIG(channel),
 270                                     AD7124_CONFIG_PGA_MSK,
 271                                     AD7124_CONFIG_PGA(res), 2);
 272         if (ret < 0)
 273                 return ret;
 274
 275         st->channel_config[channel].pga_bits = res;
 276
 277         return 0;
 278 }
 279
 280 static int ad7124_read_raw(struct iio_dev *indio_dev,
 281                            struct iio_chan_spec const *chan,
 282                            int *val, int *val2, long info)
 283 {
 284         struct ad7124_state *st = iio_priv(indio_dev);
 285         int idx, ret;
 286
 287         switch (info) {
 288         case IIO_CHAN_INFO_RAW:
 289                 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
 290                 if (ret < 0)
 291                         return ret;
 292
 293                 /* After the conversion is performed, disable the channel */
 294                 ret = ad_sd_write_reg(&st->sd,
 295                                       AD7124_CHANNEL(chan->address), 2,
 296                                       st->channel_config[chan->address].ain |
 297                                       AD7124_CHANNEL_EN(0));
 298                 if (ret < 0)
 299                         return ret;
 300
 301                 return IIO_VAL_INT;
 302         case IIO_CHAN_INFO_SCALE:
 303                 idx = st->channel_config[chan->address].pga_bits;
 304                 *val = st->channel_config[chan->address].vref_mv;
 305                 if (st->channel_config[chan->address].bipolar)
 306                         *val2 = chan->scan_type.realbits - 1 + idx;
 307                 else
 308                         *val2 = chan->scan_type.realbits + idx;
 309
 310                 return IIO_VAL_FRACTIONAL_LOG2;
 311         case IIO_CHAN_INFO_OFFSET:
 312                 if (st->channel_config[chan->address].bipolar)
 313                         *val = -(1 << (chan->scan_type.realbits - 1));
 314                 else
 315                         *val = 0;
 316
 317                 return IIO_VAL_INT;
 318         case IIO_CHAN_INFO_SAMP_FREQ:
 319                 *val = st->channel_config[chan->address].odr;
 320
 321                 return IIO_VAL_INT;
 322         default:
 323                 return -EINVAL;
 324         }
 325 }
 326
 327 static int ad7124_write_raw(struct iio_dev *indio_dev,
 328                             struct iio_chan_spec const *chan,
 329                             int val, int val2, long info)
 330 {
 331         struct ad7124_state *st = iio_priv(indio_dev);
 332         unsigned int res, gain, full_scale, vref;
 333
 334         switch (info) {
 335         case IIO_CHAN_INFO_SAMP_FREQ:
 336                 if (val2 != 0)
 337                         return -EINVAL;
 338
 339                 return ad7124_set_channel_odr(st, chan->address, val);
 340         case IIO_CHAN_INFO_SCALE:
 341                 if (val != 0)
 342                         return -EINVAL;
 343
 344                 if (st->channel_config[chan->address].bipolar)
 345                         full_scale = 1 << (chan->scan_type.realbits - 1);
 346                 else
 347                         full_scale = 1 << chan->scan_type.realbits;
 348
 349                 vref = st->channel_config[chan->address].vref_mv * 1000000LL;
 350                 res = DIV_ROUND_CLOSEST(vref, full_scale);
 351                 gain = DIV_ROUND_CLOSEST(res, val2);
 352
 353                 return ad7124_set_channel_gain(st, chan->address, gain);
 354         default:
 355                 return -EINVAL;
 356         }
 357 }
 358
 359 static IIO_CONST_ATTR(in_voltage_scale_available,
 360         "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
 361
 362 static struct attribute *ad7124_attributes[] = {
 363         &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
 364         NULL,
 365 };
 366
 367 static const struct attribute_group ad7124_attrs_group = {
 368         .attrs = ad7124_attributes,
 369 };
 370
 371 static const struct iio_info ad7124_info = {
 372         .read_raw = ad7124_read_raw,
 373         .write_raw = ad7124_write_raw,
 374         .validate_trigger = ad_sd_validate_trigger,
 375         .attrs = &ad7124_attrs_group,
 376 };
 377
 378 static int ad7124_soft_reset(struct ad7124_state *st)
 379 {
 380         unsigned int readval, timeout;
 381         int ret;
 382
 383         ret = ad_sd_reset(&st->sd, 64);
 384         if (ret < 0)
 385                 return ret;
 386
 387         timeout = 100;
 388         do {
 389                 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
 390                 if (ret < 0)
 391                         return ret;
 392
 393                 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
 394                         return 0;
 395
 396                 /* The AD7124 requires typically 2ms to power up and settle */
 397                 usleep_range(100, 2000);
 398         } while (--timeout);
 399
 400         dev_err(&st->sd.spi->dev, "Soft reset failed\n");
 401
 402         return -EIO;
 403 }
 404
 405 static int ad7124_init_channel_vref(struct ad7124_state *st,
 406                                     unsigned int channel_number)
 407 {
 408         unsigned int refsel = st->channel_config[channel_number].refsel;
 409
 410         switch (refsel) {
 411         case AD7124_REFIN1:
 412         case AD7124_REFIN2:
 413         case AD7124_AVDD_REF:
 414                 if (IS_ERR(st->vref[refsel])) {
 415                         dev_err(&st->sd.spi->dev,
 416                                 "Error, trying to use external voltage reference without a %s regulator.\n",
 417                                 ad7124_ref_names[refsel]);
 418                         return PTR_ERR(st->vref[refsel]);
 419                 }
 420                 st->channel_config[channel_number].vref_mv =
 421                         regulator_get_voltage(st->vref[refsel]);
 422                 /* Conversion from uV to mV */
 423                 st->channel_config[channel_number].vref_mv /= 1000;
 424                 break;
 425         case AD7124_INT_REF:
 426                 st->channel_config[channel_number].vref_mv = 2500;
 427                 break;
 428         default:
 429                 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
 430                 return -EINVAL;
 431         }
 432
 433         return 0;
 434 }
 435
 436 static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
 437                                           struct device_node *np)
 438 {
 439         struct ad7124_state *st = iio_priv(indio_dev);
 440         struct device_node *child;
 441         struct iio_chan_spec *chan;
 442         struct ad7124_channel_config *chan_config;
 443         unsigned int ain[2], channel = 0, tmp;
 444         int ret;
 445
 446         st->num_channels = of_get_available_child_count(np);
 447         if (!st->num_channels) {
 448                 dev_err(indio_dev->dev.parent, "no channel children\n");
 449                 return -ENODEV;
 450         }
 451
 452         chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
 453                             sizeof(*chan), GFP_KERNEL);
 454         if (!chan)
 455                 return -ENOMEM;
 456
 457         chan_config = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
 458                                    sizeof(*chan_config), GFP_KERNEL);
 459         if (!chan_config)
 460                 return -ENOMEM;
 461
 462         indio_dev->channels = chan;
 463         indio_dev->num_channels = st->num_channels;
 464         st->channel_config = chan_config;
 465
 466         for_each_available_child_of_node(np, child) {
 467                 ret = of_property_read_u32(child, "reg", &channel);
 468                 if (ret)
 469                         goto err;
 470
 471                 ret = of_property_read_u32_array(child, "diff-channels",
 472                                                  ain, 2);
 473                 if (ret)
 474                         goto err;
 475
 476                 st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
 477                                                   AD7124_CHANNEL_AINM(ain[1]);
 478                 st->channel_config[channel].bipolar =
 479                         of_property_read_bool(child, "bipolar");
 480
 481                 ret = of_property_read_u32(child, "adi,reference-select", &tmp);
 482                 if (ret)
 483                         st->channel_config[channel].refsel = AD7124_INT_REF;
 484                 else
 485                         st->channel_config[channel].refsel = tmp;
 486
 487                 st->channel_config[channel].buf_positive =
 488                         of_property_read_bool(child, "adi,buffered-positive");
 489                 st->channel_config[channel].buf_negative =
 490                         of_property_read_bool(child, "adi,buffered-negative");
 491
 492                 *chan = ad7124_channel_template;
 493                 chan->address = channel;
 494                 chan->scan_index = channel;
 495                 chan->channel = ain[0];
 496                 chan->channel2 = ain[1];
 497
 498                 chan++;
 499         }
 500
 501         return 0;
 502 err:
 503         of_node_put(child);
 504
 505         return ret;
 506 }
 507
 508 static int ad7124_setup(struct ad7124_state *st)
 509 {
 510         unsigned int val, fclk, power_mode;
 511         int i, ret, tmp;
 512
 513         fclk = clk_get_rate(st->mclk);
 514         if (!fclk)
 515                 return -EINVAL;
 516
 517         /* The power mode changes the master clock frequency */
 518         power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
 519                                         ARRAY_SIZE(ad7124_master_clk_freq_hz),
 520                                         fclk);
 521         if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
 522                 ret = clk_set_rate(st->mclk, fclk);
 523                 if (ret)
 524                         return ret;
 525         }
 526
 527         /* Set the power mode */
 528         st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
 529         st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
 530         ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
 531         if (ret < 0)
 532                 return ret;
 533
 534         for (i = 0; i < st->num_channels; i++) {
 535                 val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);
 536                 ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);
 537                 if (ret < 0)
 538                         return ret;
 539
 540                 ret = ad7124_init_channel_vref(st, i);
 541                 if (ret < 0)
 542                         return ret;
 543
 544                 tmp = (st->channel_config[i].buf_positive << 1)  +
 545                         st->channel_config[i].buf_negative;
 546
 547                 val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |
 548                       AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel) |
 549                       AD7124_CONFIG_IN_BUFF(tmp);
 550                 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);
 551                 if (ret < 0)
 552                         return ret;
 553                 /*
 554                  * 9.38 SPS is the minimum output data rate supported
 555                  * regardless of the selected power mode. Round it up to 10 and
 556                  * set all the enabled channels to this default value.
 557                  */
 558                 ret = ad7124_set_channel_odr(st, i, 10);
 559         }
 560
 561         return ret;
 562 }
 563
 564 static int ad7124_probe(struct spi_device *spi)
 565 {
 566         const struct spi_device_id *id;
 567         struct ad7124_state *st;
 568         struct iio_dev *indio_dev;
 569         int i, ret;
 570
 571         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 572         if (!indio_dev)
 573                 return -ENOMEM;
 574
 575         st = iio_priv(indio_dev);
 576
 577         id = spi_get_device_id(spi);
 578         st->chip_info = &ad7124_chip_info_tbl[id->driver_data];
 579
 580         ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
 581
 582         spi_set_drvdata(spi, indio_dev);
 583
 584         indio_dev->dev.parent = &spi->dev;
 585         indio_dev->name = spi_get_device_id(spi)->name;
 586         indio_dev->modes = INDIO_DIRECT_MODE;
 587         indio_dev->info = &ad7124_info;
 588
 589         ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
 590         if (ret < 0)
 591                 return ret;
 592
 593         for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
 594                 if (i == AD7124_INT_REF)
 595                         continue;
 596
 597                 st->vref[i] = devm_regulator_get_optional(&spi->dev,
 598                                                 ad7124_ref_names[i]);
 599                 if (PTR_ERR(st->vref[i]) == -ENODEV)
 600                         continue;
 601                 else if (IS_ERR(st->vref[i]))
 602                         return PTR_ERR(st->vref[i]);
 603
 604                 ret = regulator_enable(st->vref[i]);
 605                 if (ret)
 606                         return ret;
 607         }
 608
 609         st->mclk = devm_clk_get(&spi->dev, "mclk");
 610         if (IS_ERR(st->mclk)) {
 611                 ret = PTR_ERR(st->mclk);
 612                 goto error_regulator_disable;
 613         }
 614
 615         ret = clk_prepare_enable(st->mclk);
 616         if (ret < 0)
 617                 goto error_regulator_disable;
 618
 619         ret = ad7124_soft_reset(st);
 620         if (ret < 0)
 621                 goto error_clk_disable_unprepare;
 622
 623         ret = ad7124_setup(st);
 624         if (ret < 0)
 625                 goto error_clk_disable_unprepare;
 626
 627         ret = ad_sd_setup_buffer_and_trigger(indio_dev);
 628         if (ret < 0)
 629                 goto error_clk_disable_unprepare;
 630
 631         ret = iio_device_register(indio_dev);
 632         if (ret < 0) {
 633                 dev_err(&spi->dev, "Failed to register iio device\n");
 634                 goto error_remove_trigger;
 635         }
 636
 637         return 0;
 638
 639 error_remove_trigger:
 640         ad_sd_cleanup_buffer_and_trigger(indio_dev);
 641 error_clk_disable_unprepare:
 642         clk_disable_unprepare(st->mclk);
 643 error_regulator_disable:
 644         for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
 645                 if (!IS_ERR_OR_NULL(st->vref[i]))
 646                         regulator_disable(st->vref[i]);
 647         }
 648
 649         return ret;
 650 }
 651
 652 static int ad7124_remove(struct spi_device *spi)
 653 {
 654         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 655         struct ad7124_state *st = iio_priv(indio_dev);
 656         int i;
 657
 658         iio_device_unregister(indio_dev);
 659         ad_sd_cleanup_buffer_and_trigger(indio_dev);
 660         clk_disable_unprepare(st->mclk);
 661
 662         for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
 663                 if (!IS_ERR_OR_NULL(st->vref[i]))
 664                         regulator_disable(st->vref[i]);
 665         }
 666
 667         return 0;
 668 }
 669
 670 static const struct spi_device_id ad7124_id_table[] = {
 671         { "ad7124-4", ID_AD7124_4 },
 672         { "ad7124-8", ID_AD7124_8 },
 673         {}
 674 };
 675 MODULE_DEVICE_TABLE(spi, ad7124_id_table);
 676
 677 static const struct of_device_id ad7124_of_match[] = {
 678         { .compatible = "adi,ad7124-4" },
 679         { .compatible = "adi,ad7124-8" },
 680         { },
 681 };
 682 MODULE_DEVICE_TABLE(of, ad7124_of_match);
 683
 684 static struct spi_driver ad71124_driver = {
 685         .driver = {
 686                 .name = "ad7124",
 687                 .of_match_table = ad7124_of_match,
 688         },
 689         .probe = ad7124_probe,
 690         .remove = ad7124_remove,
 691         .id_table = ad7124_id_table,
 692 };
 693 module_spi_driver(ad71124_driver);
 694
 695 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
 696 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
 697 MODULE_LICENSE("GPL");