drivers/spi/spi-dw.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef DW_SPI_HEADER_H
   3 #define DW_SPI_HEADER_H
   4
   5 #include <linux/io.h>
   6 #include <linux/scatterlist.h>
   7
   8 /* Register offsets */
   9 #define DW_SPI_CTRL0                    0x00
  10 #define DW_SPI_CTRL1                    0x04
  11 #define DW_SPI_SSIENR                   0x08
  12 #define DW_SPI_MWCR                     0x0c
  13 #define DW_SPI_SER                      0x10
  14 #define DW_SPI_BAUDR                    0x14
  15 #define DW_SPI_TXFLTR                   0x18
  16 #define DW_SPI_RXFLTR                   0x1c
  17 #define DW_SPI_TXFLR                    0x20
  18 #define DW_SPI_RXFLR                    0x24
  19 #define DW_SPI_SR                       0x28
  20 #define DW_SPI_IMR                      0x2c
  21 #define DW_SPI_ISR                      0x30
  22 #define DW_SPI_RISR                     0x34
  23 #define DW_SPI_TXOICR                   0x38
  24 #define DW_SPI_RXOICR                   0x3c
  25 #define DW_SPI_RXUICR                   0x40
  26 #define DW_SPI_MSTICR                   0x44
  27 #define DW_SPI_ICR                      0x48
  28 #define DW_SPI_DMACR                    0x4c
  29 #define DW_SPI_DMATDLR                  0x50
  30 #define DW_SPI_DMARDLR                  0x54
  31 #define DW_SPI_IDR                      0x58
  32 #define DW_SPI_VERSION                  0x5c
  33 #define DW_SPI_DR                       0x60
  34 #define DW_SPI_CS_OVERRIDE              0xf4
  35
  36 /* Bit fields in CTRLR0 */
  37 #define SPI_DFS_OFFSET                  0
  38
  39 #define SPI_FRF_OFFSET                  4
  40 #define SPI_FRF_SPI                     0x0
  41 #define SPI_FRF_SSP                     0x1
  42 #define SPI_FRF_MICROWIRE               0x2
  43 #define SPI_FRF_RESV                    0x3
  44
  45 #define SPI_MODE_OFFSET                 6
  46 #define SPI_SCPH_OFFSET                 6
  47 #define SPI_SCOL_OFFSET                 7
  48
  49 #define SPI_TMOD_OFFSET                 8
  50 #define SPI_TMOD_MASK                   (0x3 << SPI_TMOD_OFFSET)
  51 #define SPI_TMOD_TR                     0x0             /* xmit & recv */
  52 #define SPI_TMOD_TO                     0x1             /* xmit only */
  53 #define SPI_TMOD_RO                     0x2             /* recv only */
  54 #define SPI_TMOD_EPROMREAD              0x3             /* eeprom read mode */
  55
  56 #define SPI_SLVOE_OFFSET                10
  57 #define SPI_SRL_OFFSET                  11
  58 #define SPI_CFS_OFFSET                  12
  59
  60 /* Bit fields in SR, 7 bits */
  61 #define SR_MASK                         0x7f            /* cover 7 bits */
  62 #define SR_BUSY                         (1 << 0)
  63 #define SR_TF_NOT_FULL                  (1 << 1)
  64 #define SR_TF_EMPT                      (1 << 2)
  65 #define SR_RF_NOT_EMPT                  (1 << 3)
  66 #define SR_RF_FULL                      (1 << 4)
  67 #define SR_TX_ERR                       (1 << 5)
  68 #define SR_DCOL                         (1 << 6)
  69
  70 /* Bit fields in ISR, IMR, RISR, 7 bits */
  71 #define SPI_INT_TXEI                    (1 << 0)
  72 #define SPI_INT_TXOI                    (1 << 1)
  73 #define SPI_INT_RXUI                    (1 << 2)
  74 #define SPI_INT_RXOI                    (1 << 3)
  75 #define SPI_INT_RXFI                    (1 << 4)
  76 #define SPI_INT_MSTI                    (1 << 5)
  77
  78 /* Bit fields in DMACR */
  79 #define SPI_DMA_RDMAE                   (1 << 0)
  80 #define SPI_DMA_TDMAE                   (1 << 1)
  81
  82 /* TX RX interrupt level threshold, max can be 256 */
  83 #define SPI_INT_THRESHOLD               32
  84
  85 enum dw_ssi_type {
  86         SSI_MOTO_SPI = 0,
  87         SSI_TI_SSP,
  88         SSI_NS_MICROWIRE,
  89 };
  90
  91 struct dw_spi;
  92 struct dw_spi_dma_ops {
  93         int (*dma_init)(struct dw_spi *dws);
  94         void (*dma_exit)(struct dw_spi *dws);
  95         int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
  96         bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
  97                         struct spi_transfer *xfer);
  98         int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
  99         void (*dma_stop)(struct dw_spi *dws);
 100 };
 101
 102 struct dw_spi {
 103         struct spi_controller   *master;
 104         enum dw_ssi_type        type;
 105
 106         void __iomem            *regs;
 107         unsigned long           paddr;
 108         int                     irq;
 109         u32                     fifo_len;       /* depth of the FIFO buffer */
 110         u32                     max_freq;       /* max bus freq supported */
 111
 112         int                     cs_override;
 113         u32                     reg_io_width;   /* DR I/O width in bytes */
 114         u16                     bus_num;
 115         u16                     num_cs;         /* supported slave numbers */
 116         void (*set_cs)(struct spi_device *spi, bool enable);
 117
 118         /* Current message transfer state info */
 119         size_t                  len;
 120         void                    *tx;
 121         void                    *tx_end;
 122         void                    *rx;
 123         void                    *rx_end;
 124         int                     dma_mapped;
 125         u8                      n_bytes;        /* current is a 1/2 bytes op */
 126         u32                     dma_width;
 127         irqreturn_t             (*transfer_handler)(struct dw_spi *dws);
 128         u32                     current_freq;   /* frequency in hz */
 129
 130         /* DMA info */
 131         int                     dma_inited;
 132         struct dma_chan         *txchan;
 133         struct dma_chan         *rxchan;
 134         unsigned long           dma_chan_busy;
 135         dma_addr_t              dma_addr; /* phy address of the Data register */
 136         const struct dw_spi_dma_ops *dma_ops;
 137         void                    *dma_tx;
 138         void                    *dma_rx;
 139
 140         /* Bus interface info */
 141         void                    *priv;
 142 #ifdef CONFIG_DEBUG_FS
 143         struct dentry *debugfs;
 144 #endif
 145 };
 146
 147 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
 148 {
 149         return __raw_readl(dws->regs + offset);
 150 }
 151
 152 static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
 153 {
 154         return __raw_readw(dws->regs + offset);
 155 }
 156
 157 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
 158 {
 159         __raw_writel(val, dws->regs + offset);
 160 }
 161
 162 static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
 163 {
 164         __raw_writew(val, dws->regs + offset);
 165 }
 166
 167 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
 168 {
 169         switch (dws->reg_io_width) {
 170         case 2:
 171                 return dw_readw(dws, offset);
 172         case 4:
 173         default:
 174                 return dw_readl(dws, offset);
 175         }
 176 }
 177
 178 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
 179 {
 180         switch (dws->reg_io_width) {
 181         case 2:
 182                 dw_writew(dws, offset, val);
 183                 break;
 184         case 4:
 185         default:
 186                 dw_writel(dws, offset, val);
 187                 break;
 188         }
 189 }
 190
 191 static inline void spi_enable_chip(struct dw_spi *dws, int enable)
 192 {
 193         dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
 194 }
 195
 196 static inline void spi_set_clk(struct dw_spi *dws, u16 div)
 197 {
 198         dw_writel(dws, DW_SPI_BAUDR, div);
 199 }
 200
 201 /* Disable IRQ bits */
 202 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
 203 {
 204         u32 new_mask;
 205
 206         new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
 207         dw_writel(dws, DW_SPI_IMR, new_mask);
 208 }
 209
 210 /* Enable IRQ bits */
 211 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
 212 {
 213         u32 new_mask;
 214
 215         new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
 216         dw_writel(dws, DW_SPI_IMR, new_mask);
 217 }
 218
 219 /*
 220  * This does disable the SPI controller, interrupts, and re-enable the
 221  * controller back. Transmit and receive FIFO buffers are cleared when the
 222  * device is disabled.
 223  */
 224 static inline void spi_reset_chip(struct dw_spi *dws)
 225 {
 226         spi_enable_chip(dws, 0);
 227         spi_mask_intr(dws, 0xff);
 228         spi_enable_chip(dws, 1);
 229 }
 230
 231 static inline void spi_shutdown_chip(struct dw_spi *dws)
 232 {
 233         spi_enable_chip(dws, 0);
 234         spi_set_clk(dws, 0);
 235 }
 236
 237 /*
 238  * Each SPI slave device to work with dw_api controller should
 239  * has such a structure claiming its working mode (poll or PIO/DMA),
 240  * which can be save in the "controller_data" member of the
 241  * struct spi_device.
 242  */
 243 struct dw_spi_chip {
 244         u8 poll_mode;   /* 1 for controller polling mode */
 245         u8 type;        /* SPI/SSP/MicroWire */
 246         void (*cs_control)(u32 command);
 247 };
 248
 249 extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
 250 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
 251 extern void dw_spi_remove_host(struct dw_spi *dws);
 252 extern int dw_spi_suspend_host(struct dw_spi *dws);
 253 extern int dw_spi_resume_host(struct dw_spi *dws);
 254
 255 /* platform related setup */
 256 extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
 257 #endif /* DW_SPI_HEADER_H */