drivers/staging/axis-fifo/axis-fifo.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
   4  *
   5  * Copyright (C) 2018 Jacob Feder
   6  *
   7  * Authors:  Jacob Feder <jacobsfeder@gmail.com>
   8  *
   9  * See Xilinx PG080 document for IP details
  10  */
  11
  12 /* ----------------------------
  13  *           includes
  14  * ----------------------------
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/wait.h>
  19 #include <linux/spinlock_types.h>
  20 #include <linux/device.h>
  21 #include <linux/cdev.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/io.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/param.h>
  29 #include <linux/fs.h>
  30 #include <linux/types.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/jiffies.h>
  33
  34 #include <linux/of_address.h>
  35 #include <linux/of_device.h>
  36 #include <linux/of_platform.h>
  37
  38 /* ----------------------------
  39  *       driver parameters
  40  * ----------------------------
  41  */
  42
  43 #define DRIVER_NAME "axis_fifo"
  44
  45 #define READ_BUF_SIZE 128U /* read buffer length in words */
  46 #define WRITE_BUF_SIZE 128U /* write buffer length in words */
  47
  48 /* ----------------------------
  49  *     IP register offsets
  50  * ----------------------------
  51  */
  52
  53 #define XLLF_ISR_OFFSET  0x00000000  /* Interrupt Status */
  54 #define XLLF_IER_OFFSET  0x00000004  /* Interrupt Enable */
  55
  56 #define XLLF_TDFR_OFFSET 0x00000008  /* Transmit Reset */
  57 #define XLLF_TDFV_OFFSET 0x0000000c  /* Transmit Vacancy */
  58 #define XLLF_TDFD_OFFSET 0x00000010  /* Transmit Data */
  59 #define XLLF_TLR_OFFSET  0x00000014  /* Transmit Length */
  60
  61 #define XLLF_RDFR_OFFSET 0x00000018  /* Receive Reset */
  62 #define XLLF_RDFO_OFFSET 0x0000001c  /* Receive Occupancy */
  63 #define XLLF_RDFD_OFFSET 0x00000020  /* Receive Data */
  64 #define XLLF_RLR_OFFSET  0x00000024  /* Receive Length */
  65 #define XLLF_SRR_OFFSET  0x00000028  /* Local Link Reset */
  66 #define XLLF_TDR_OFFSET  0x0000002C  /* Transmit Destination */
  67 #define XLLF_RDR_OFFSET  0x00000030  /* Receive Destination */
  68
  69 /* ----------------------------
  70  *     reset register masks
  71  * ----------------------------
  72  */
  73
  74 #define XLLF_RDFR_RESET_MASK        0x000000a5 /* receive reset value */
  75 #define XLLF_TDFR_RESET_MASK        0x000000a5 /* Transmit reset value */
  76 #define XLLF_SRR_RESET_MASK         0x000000a5 /* Local Link reset value */
  77
  78 /* ----------------------------
  79  *       interrupt masks
  80  * ----------------------------
  81  */
  82
  83 #define XLLF_INT_RPURE_MASK       0x80000000 /* Receive under-read */
  84 #define XLLF_INT_RPORE_MASK       0x40000000 /* Receive over-read */
  85 #define XLLF_INT_RPUE_MASK        0x20000000 /* Receive underrun (empty) */
  86 #define XLLF_INT_TPOE_MASK        0x10000000 /* Transmit overrun */
  87 #define XLLF_INT_TC_MASK          0x08000000 /* Transmit complete */
  88 #define XLLF_INT_RC_MASK          0x04000000 /* Receive complete */
  89 #define XLLF_INT_TSE_MASK         0x02000000 /* Transmit length mismatch */
  90 #define XLLF_INT_TRC_MASK         0x01000000 /* Transmit reset complete */
  91 #define XLLF_INT_RRC_MASK         0x00800000 /* Receive reset complete */
  92 #define XLLF_INT_TFPF_MASK        0x00400000 /* Tx FIFO Programmable Full */
  93 #define XLLF_INT_TFPE_MASK        0x00200000 /* Tx FIFO Programmable Empty */
  94 #define XLLF_INT_RFPF_MASK        0x00100000 /* Rx FIFO Programmable Full */
  95 #define XLLF_INT_RFPE_MASK        0x00080000 /* Rx FIFO Programmable Empty */
  96 #define XLLF_INT_ALL_MASK         0xfff80000 /* All the ints */
  97 #define XLLF_INT_ERROR_MASK       0xf2000000 /* Error status ints */
  98 #define XLLF_INT_RXERROR_MASK     0xe0000000 /* Receive Error status ints */
  99 #define XLLF_INT_TXERROR_MASK     0x12000000 /* Transmit Error status ints */
 100
 101 /* ----------------------------
 102  *           globals
 103  * ----------------------------
 104  */
 105
 106 static struct class *axis_fifo_driver_class; /* char device class */
 107
 108 static int read_timeout = 1000; /* ms to wait before read() times out */
 109 static int write_timeout = 1000; /* ms to wait before write() times out */
 110
 111 /* ----------------------------
 112  * module command-line arguments
 113  * ----------------------------
 114  */
 115
 116 module_param(read_timeout, int, 0444);
 117 MODULE_PARM_DESC(read_timeout, "ms to wait before blocking read() timing out; set to -1 for no timeout");
 118 module_param(write_timeout, int, 0444);
 119 MODULE_PARM_DESC(write_timeout, "ms to wait before blocking write() timing out; set to -1 for no timeout");
 120
 121 /* ----------------------------
 122  *            types
 123  * ----------------------------
 124  */
 125
 126 struct axis_fifo {
 127         int irq; /* interrupt */
 128         void __iomem *base_addr; /* kernel space memory */
 129
 130         unsigned int rx_fifo_depth; /* max words in the receive fifo */
 131         unsigned int tx_fifo_depth; /* max words in the transmit fifo */
 132         int has_rx_fifo; /* whether the IP has the rx fifo enabled */
 133         int has_tx_fifo; /* whether the IP has the tx fifo enabled */
 134
 135         wait_queue_head_t read_queue; /* wait queue for asynchronos read */
 136         spinlock_t read_queue_lock; /* lock for reading waitqueue */
 137         wait_queue_head_t write_queue; /* wait queue for asynchronos write */
 138         spinlock_t write_queue_lock; /* lock for writing waitqueue */
 139         unsigned int write_flags; /* write file flags */
 140         unsigned int read_flags; /* read file flags */
 141
 142         struct device *dt_device; /* device created from the device tree */
 143         struct device *device; /* device associated with char_device */
 144         dev_t devt; /* our char device number */
 145         struct cdev char_device; /* our char device */
 146 };
 147
 148 /* ----------------------------
 149  *         sysfs entries
 150  * ----------------------------
 151  */
 152
 153 static ssize_t sysfs_write(struct device *dev, const char *buf,
 154                            size_t count, unsigned int addr_offset)
 155 {
 156         struct axis_fifo *fifo = dev_get_drvdata(dev);
 157         unsigned long tmp;
 158         int rc;
 159
 160         rc = kstrtoul(buf, 0, &tmp);
 161         if (rc < 0)
 162                 return rc;
 163
 164         iowrite32(tmp, fifo->base_addr + addr_offset);
 165
 166         return count;
 167 }
 168
 169 static ssize_t sysfs_read(struct device *dev, char *buf,
 170                           unsigned int addr_offset)
 171 {
 172         struct axis_fifo *fifo = dev_get_drvdata(dev);
 173         unsigned int read_val;
 174         unsigned int len;
 175         char tmp[32];
 176
 177         read_val = ioread32(fifo->base_addr + addr_offset);
 178         len =  snprintf(tmp, sizeof(tmp), "0x%x\n", read_val);
 179         memcpy(buf, tmp, len);
 180
 181         return len;
 182 }
 183
 184 static ssize_t isr_store(struct device *dev, struct device_attribute *attr,
 185                          const char *buf, size_t count)
 186 {
 187         return sysfs_write(dev, buf, count, XLLF_ISR_OFFSET);
 188 }
 189
 190 static ssize_t isr_show(struct device *dev,
 191                         struct device_attribute *attr, char *buf)
 192 {
 193         return sysfs_read(dev, buf, XLLF_ISR_OFFSET);
 194 }
 195
 196 static DEVICE_ATTR_RW(isr);
 197
 198 static ssize_t ier_store(struct device *dev, struct device_attribute *attr,
 199                          const char *buf, size_t count)
 200 {
 201         return sysfs_write(dev, buf, count, XLLF_IER_OFFSET);
 202 }
 203
 204 static ssize_t ier_show(struct device *dev,
 205                         struct device_attribute *attr, char *buf)
 206 {
 207         return sysfs_read(dev, buf, XLLF_IER_OFFSET);
 208 }
 209
 210 static DEVICE_ATTR_RW(ier);
 211
 212 static ssize_t tdfr_store(struct device *dev, struct device_attribute *attr,
 213                           const char *buf, size_t count)
 214 {
 215         return sysfs_write(dev, buf, count, XLLF_TDFR_OFFSET);
 216 }
 217
 218 static DEVICE_ATTR_WO(tdfr);
 219
 220 static ssize_t tdfv_show(struct device *dev,
 221                          struct device_attribute *attr, char *buf)
 222 {
 223         return sysfs_read(dev, buf, XLLF_TDFV_OFFSET);
 224 }
 225
 226 static DEVICE_ATTR_RO(tdfv);
 227
 228 static ssize_t tdfd_store(struct device *dev, struct device_attribute *attr,
 229                           const char *buf, size_t count)
 230 {
 231         return sysfs_write(dev, buf, count, XLLF_TDFD_OFFSET);
 232 }
 233
 234 static DEVICE_ATTR_WO(tdfd);
 235
 236 static ssize_t tlr_store(struct device *dev, struct device_attribute *attr,
 237                          const char *buf, size_t count)
 238 {
 239         return sysfs_write(dev, buf, count, XLLF_TLR_OFFSET);
 240 }
 241
 242 static DEVICE_ATTR_WO(tlr);
 243
 244 static ssize_t rdfr_store(struct device *dev, struct device_attribute *attr,
 245                           const char *buf, size_t count)
 246 {
 247         return sysfs_write(dev, buf, count, XLLF_RDFR_OFFSET);
 248 }
 249
 250 static DEVICE_ATTR_WO(rdfr);
 251
 252 static ssize_t rdfo_show(struct device *dev,
 253                          struct device_attribute *attr, char *buf)
 254 {
 255         return sysfs_read(dev, buf, XLLF_RDFO_OFFSET);
 256 }
 257
 258 static DEVICE_ATTR_RO(rdfo);
 259
 260 static ssize_t rdfd_show(struct device *dev,
 261                          struct device_attribute *attr, char *buf)
 262 {
 263         return sysfs_read(dev, buf, XLLF_RDFD_OFFSET);
 264 }
 265
 266 static DEVICE_ATTR_RO(rdfd);
 267
 268 static ssize_t rlr_show(struct device *dev,
 269                         struct device_attribute *attr, char *buf)
 270 {
 271         return sysfs_read(dev, buf, XLLF_RLR_OFFSET);
 272 }
 273
 274 static DEVICE_ATTR_RO(rlr);
 275
 276 static ssize_t srr_store(struct device *dev, struct device_attribute *attr,
 277                          const char *buf, size_t count)
 278 {
 279         return sysfs_write(dev, buf, count, XLLF_SRR_OFFSET);
 280 }
 281
 282 static DEVICE_ATTR_WO(srr);
 283
 284 static ssize_t tdr_store(struct device *dev, struct device_attribute *attr,
 285                          const char *buf, size_t count)
 286 {
 287         return sysfs_write(dev, buf, count, XLLF_TDR_OFFSET);
 288 }
 289
 290 static DEVICE_ATTR_WO(tdr);
 291
 292 static ssize_t rdr_show(struct device *dev,
 293                         struct device_attribute *attr, char *buf)
 294 {
 295         return sysfs_read(dev, buf, XLLF_RDR_OFFSET);
 296 }
 297
 298 static DEVICE_ATTR_RO(rdr);
 299
 300 static struct attribute *axis_fifo_attrs[] = {
 301         &dev_attr_isr.attr,
 302         &dev_attr_ier.attr,
 303         &dev_attr_tdfr.attr,
 304         &dev_attr_tdfv.attr,
 305         &dev_attr_tdfd.attr,
 306         &dev_attr_tlr.attr,
 307         &dev_attr_rdfr.attr,
 308         &dev_attr_rdfo.attr,
 309         &dev_attr_rdfd.attr,
 310         &dev_attr_rlr.attr,
 311         &dev_attr_srr.attr,
 312         &dev_attr_tdr.attr,
 313         &dev_attr_rdr.attr,
 314         NULL,
 315 };
 316
 317 static const struct attribute_group axis_fifo_attrs_group = {
 318         .name = "ip_registers",
 319         .attrs = axis_fifo_attrs,
 320 };
 321
 322 /* ----------------------------
 323  *        implementation
 324  * ----------------------------
 325  */
 326
 327 static void reset_ip_core(struct axis_fifo *fifo)
 328 {
 329         iowrite32(XLLF_SRR_RESET_MASK, fifo->base_addr + XLLF_SRR_OFFSET);
 330         iowrite32(XLLF_TDFR_RESET_MASK, fifo->base_addr + XLLF_TDFR_OFFSET);
 331         iowrite32(XLLF_RDFR_RESET_MASK, fifo->base_addr + XLLF_RDFR_OFFSET);
 332         iowrite32(XLLF_INT_TC_MASK | XLLF_INT_RC_MASK | XLLF_INT_RPURE_MASK |
 333                   XLLF_INT_RPORE_MASK | XLLF_INT_RPUE_MASK |
 334                   XLLF_INT_TPOE_MASK | XLLF_INT_TSE_MASK,
 335                   fifo->base_addr + XLLF_IER_OFFSET);
 336         iowrite32(XLLF_INT_ALL_MASK, fifo->base_addr + XLLF_ISR_OFFSET);
 337 }
 338
 339 /* reads a single packet from the fifo as dictated by the tlast signal */
 340 static ssize_t axis_fifo_read(struct file *f, char __user *buf,
 341                               size_t len, loff_t *off)
 342 {
 343         struct axis_fifo *fifo = (struct axis_fifo *)f->private_data;
 344         size_t bytes_available;
 345         unsigned int words_available;
 346         unsigned int copied;
 347         unsigned int copy;
 348         unsigned int i;
 349         int ret;
 350         u32 tmp_buf[READ_BUF_SIZE];
 351
 352         if (fifo->read_flags & O_NONBLOCK) {
 353                 /* opened in non-blocking mode
 354                  * return if there are no packets available
 355                  */
 356                 if (!ioread32(fifo->base_addr + XLLF_RDFO_OFFSET))
 357                         return -EAGAIN;
 358         } else {
 359                 /* opened in blocking mode
 360                  * wait for a packet available interrupt (or timeout)
 361                  * if nothing is currently available
 362                  */
 363                 spin_lock_irq(&fifo->read_queue_lock);
 364                 ret = wait_event_interruptible_lock_irq_timeout
 365                         (fifo->read_queue,
 366                          ioread32(fifo->base_addr + XLLF_RDFO_OFFSET),
 367                          fifo->read_queue_lock,
 368                          (read_timeout >= 0) ? msecs_to_jiffies(read_timeout) :
 369                                 MAX_SCHEDULE_TIMEOUT);
 370                 spin_unlock_irq(&fifo->read_queue_lock);
 371
 372                 if (ret == 0) {
 373                         /* timeout occurred */
 374                         dev_dbg(fifo->dt_device, "read timeout");
 375                         return -EAGAIN;
 376                 } else if (ret == -ERESTARTSYS) {
 377                         /* signal received */
 378                         return -ERESTARTSYS;
 379                 } else if (ret < 0) {
 380                         dev_err(fifo->dt_device, "wait_event_interruptible_timeout() error in read (ret=%i)\n",
 381                                 ret);
 382                         return ret;
 383                 }
 384         }
 385
 386         bytes_available = ioread32(fifo->base_addr + XLLF_RLR_OFFSET);
 387         if (!bytes_available) {
 388                 dev_err(fifo->dt_device, "received a packet of length 0 - fifo core will be reset\n");
 389                 reset_ip_core(fifo);
 390                 return -EIO;
 391         }
 392
 393         if (bytes_available > len) {
 394                 dev_err(fifo->dt_device, "user read buffer too small (available bytes=%zu user buffer bytes=%zu) - fifo core will be reset\n",
 395                         bytes_available, len);
 396                 reset_ip_core(fifo);
 397                 return -EINVAL;
 398         }
 399
 400         if (bytes_available % sizeof(u32)) {
 401                 /* this probably can't happen unless IP
 402                  * registers were previously mishandled
 403                  */
 404                 dev_err(fifo->dt_device, "received a packet that isn't word-aligned - fifo core will be reset\n");
 405                 reset_ip_core(fifo);
 406                 return -EIO;
 407         }
 408
 409         words_available = bytes_available / sizeof(u32);
 410
 411         /* read data into an intermediate buffer, copying the contents
 412          * to userspace when the buffer is full
 413          */
 414         copied = 0;
 415         while (words_available > 0) {
 416                 copy = min(words_available, READ_BUF_SIZE);
 417
 418                 for (i = 0; i < copy; i++) {
 419                         tmp_buf[i] = ioread32(fifo->base_addr +
 420                                               XLLF_RDFD_OFFSET);
 421                 }
 422
 423                 if (copy_to_user(buf + copied * sizeof(u32), tmp_buf,
 424                                  copy * sizeof(u32))) {
 425                         reset_ip_core(fifo);
 426                         return -EFAULT;
 427                 }
 428
 429                 copied += copy;
 430                 words_available -= copy;
 431         }
 432
 433         return bytes_available;
 434 }
 435
 436 static ssize_t axis_fifo_write(struct file *f, const char __user *buf,
 437                                size_t len, loff_t *off)
 438 {
 439         struct axis_fifo *fifo = (struct axis_fifo *)f->private_data;
 440         unsigned int words_to_write;
 441         unsigned int copied;
 442         unsigned int copy;
 443         unsigned int i;
 444         int ret;
 445         u32 tmp_buf[WRITE_BUF_SIZE];
 446
 447         if (len % sizeof(u32)) {
 448                 dev_err(fifo->dt_device,
 449                         "tried to send a packet that isn't word-aligned\n");
 450                 return -EINVAL;
 451         }
 452
 453         words_to_write = len / sizeof(u32);
 454
 455         if (!words_to_write) {
 456                 dev_err(fifo->dt_device,
 457                         "tried to send a packet of length 0\n");
 458                 return -EINVAL;
 459         }
 460
 461         if (words_to_write > fifo->tx_fifo_depth) {
 462                 dev_err(fifo->dt_device, "tried to write more words [%u] than slots in the fifo buffer [%u]\n",
 463                         words_to_write, fifo->tx_fifo_depth);
 464                 return -EINVAL;
 465         }
 466
 467         if (fifo->write_flags & O_NONBLOCK) {
 468                 /* opened in non-blocking mode
 469                  * return if there is not enough room available in the fifo
 470                  */
 471                 if (words_to_write > ioread32(fifo->base_addr +
 472                                               XLLF_TDFV_OFFSET)) {
 473                         return -EAGAIN;
 474                 }
 475         } else {
 476                 /* opened in blocking mode */
 477
 478                 /* wait for an interrupt (or timeout) if there isn't
 479                  * currently enough room in the fifo
 480                  */
 481                 spin_lock_irq(&fifo->write_queue_lock);
 482                 ret = wait_event_interruptible_lock_irq_timeout
 483                         (fifo->write_queue,
 484                          ioread32(fifo->base_addr + XLLF_TDFV_OFFSET)
 485                                 >= words_to_write,
 486                          fifo->write_queue_lock,
 487                          (write_timeout >= 0) ?
 488                                 msecs_to_jiffies(write_timeout) :
 489                                 MAX_SCHEDULE_TIMEOUT);
 490                 spin_unlock_irq(&fifo->write_queue_lock);
 491
 492                 if (ret == 0) {
 493                         /* timeout occurred */
 494                         dev_dbg(fifo->dt_device, "write timeout\n");
 495                         return -EAGAIN;
 496                 } else if (ret == -ERESTARTSYS) {
 497                         /* signal received */
 498                         return -ERESTARTSYS;
 499                 } else if (ret < 0) {
 500                         /* unknown error */
 501                         dev_err(fifo->dt_device,
 502                                 "wait_event_interruptible_timeout() error in write (ret=%i)\n",
 503                                 ret);
 504                         return ret;
 505                 }
 506         }
 507
 508         /* write data from an intermediate buffer into the fifo IP, refilling
 509          * the buffer with userspace data as needed
 510          */
 511         copied = 0;
 512         while (words_to_write > 0) {
 513                 copy = min(words_to_write, WRITE_BUF_SIZE);
 514
 515                 if (copy_from_user(tmp_buf, buf + copied * sizeof(u32),
 516                                    copy * sizeof(u32))) {
 517                         reset_ip_core(fifo);
 518                         return -EFAULT;
 519                 }
 520
 521                 for (i = 0; i < copy; i++)
 522                         iowrite32(tmp_buf[i], fifo->base_addr +
 523                                   XLLF_TDFD_OFFSET);
 524
 525                 copied += copy;
 526                 words_to_write -= copy;
 527         }
 528
 529         /* write packet size to fifo */
 530         iowrite32(copied * sizeof(u32), fifo->base_addr + XLLF_TLR_OFFSET);
 531
 532         return (ssize_t)copied * sizeof(u32);
 533 }
 534
 535 static irqreturn_t axis_fifo_irq(int irq, void *dw)
 536 {
 537         struct axis_fifo *fifo = (struct axis_fifo *)dw;
 538         unsigned int pending_interrupts;
 539
 540         do {
 541                 pending_interrupts = ioread32(fifo->base_addr +
 542                                               XLLF_IER_OFFSET) &
 543                                               ioread32(fifo->base_addr
 544                                               + XLLF_ISR_OFFSET);
 545                 if (pending_interrupts & XLLF_INT_RC_MASK) {
 546                         /* packet received */
 547
 548                         /* wake the reader process if it is waiting */
 549                         wake_up(&fifo->read_queue);
 550
 551                         /* clear interrupt */
 552                         iowrite32(XLLF_INT_RC_MASK & XLLF_INT_ALL_MASK,
 553                                   fifo->base_addr + XLLF_ISR_OFFSET);
 554                 } else if (pending_interrupts & XLLF_INT_TC_MASK) {
 555                         /* packet sent */
 556
 557                         /* wake the writer process if it is waiting */
 558                         wake_up(&fifo->write_queue);
 559
 560                         iowrite32(XLLF_INT_TC_MASK & XLLF_INT_ALL_MASK,
 561                                   fifo->base_addr + XLLF_ISR_OFFSET);
 562                 } else if (pending_interrupts & XLLF_INT_TFPF_MASK) {
 563                         /* transmit fifo programmable full */
 564
 565                         iowrite32(XLLF_INT_TFPF_MASK & XLLF_INT_ALL_MASK,
 566                                   fifo->base_addr + XLLF_ISR_OFFSET);
 567                 } else if (pending_interrupts & XLLF_INT_TFPE_MASK) {
 568                         /* transmit fifo programmable empty */
 569
 570                         iowrite32(XLLF_INT_TFPE_MASK & XLLF_INT_ALL_MASK,
 571                                   fifo->base_addr + XLLF_ISR_OFFSET);
 572                 } else if (pending_interrupts & XLLF_INT_RFPF_MASK) {
 573                         /* receive fifo programmable full */
 574
 575                         iowrite32(XLLF_INT_RFPF_MASK & XLLF_INT_ALL_MASK,
 576                                   fifo->base_addr + XLLF_ISR_OFFSET);
 577                 } else if (pending_interrupts & XLLF_INT_RFPE_MASK) {
 578                         /* receive fifo programmable empty */
 579
 580                         iowrite32(XLLF_INT_RFPE_MASK & XLLF_INT_ALL_MASK,
 581                                   fifo->base_addr + XLLF_ISR_OFFSET);
 582                 } else if (pending_interrupts & XLLF_INT_TRC_MASK) {
 583                         /* transmit reset complete interrupt */
 584
 585                         iowrite32(XLLF_INT_TRC_MASK & XLLF_INT_ALL_MASK,
 586                                   fifo->base_addr + XLLF_ISR_OFFSET);
 587                 } else if (pending_interrupts & XLLF_INT_RRC_MASK) {
 588                         /* receive reset complete interrupt */
 589
 590                         iowrite32(XLLF_INT_RRC_MASK & XLLF_INT_ALL_MASK,
 591                                   fifo->base_addr + XLLF_ISR_OFFSET);
 592                 } else if (pending_interrupts & XLLF_INT_RPURE_MASK) {
 593                         /* receive fifo under-read error interrupt */
 594                         dev_err(fifo->dt_device,
 595                                 "receive under-read interrupt\n");
 596
 597                         iowrite32(XLLF_INT_RPURE_MASK & XLLF_INT_ALL_MASK,
 598                                   fifo->base_addr + XLLF_ISR_OFFSET);
 599                 } else if (pending_interrupts & XLLF_INT_RPORE_MASK) {
 600                         /* receive over-read error interrupt */
 601                         dev_err(fifo->dt_device,
 602                                 "receive over-read interrupt\n");
 603
 604                         iowrite32(XLLF_INT_RPORE_MASK & XLLF_INT_ALL_MASK,
 605                                   fifo->base_addr + XLLF_ISR_OFFSET);
 606                 } else if (pending_interrupts & XLLF_INT_RPUE_MASK) {
 607                         /* receive underrun error interrupt */
 608                         dev_err(fifo->dt_device,
 609                                 "receive underrun error interrupt\n");
 610
 611                         iowrite32(XLLF_INT_RPUE_MASK & XLLF_INT_ALL_MASK,
 612                                   fifo->base_addr + XLLF_ISR_OFFSET);
 613                 } else if (pending_interrupts & XLLF_INT_TPOE_MASK) {
 614                         /* transmit overrun error interrupt */
 615                         dev_err(fifo->dt_device,
 616                                 "transmit overrun error interrupt\n");
 617
 618                         iowrite32(XLLF_INT_TPOE_MASK & XLLF_INT_ALL_MASK,
 619                                   fifo->base_addr + XLLF_ISR_OFFSET);
 620                 } else if (pending_interrupts & XLLF_INT_TSE_MASK) {
 621                         /* transmit length mismatch error interrupt */
 622                         dev_err(fifo->dt_device,
 623                                 "transmit length mismatch error interrupt\n");
 624
 625                         iowrite32(XLLF_INT_TSE_MASK & XLLF_INT_ALL_MASK,
 626                                   fifo->base_addr + XLLF_ISR_OFFSET);
 627                 } else if (pending_interrupts) {
 628                         /* unknown interrupt type */
 629                         dev_err(fifo->dt_device,
 630                                 "unknown interrupt(s) 0x%x\n",
 631                                 pending_interrupts);
 632
 633                         iowrite32(XLLF_INT_ALL_MASK,
 634                                   fifo->base_addr + XLLF_ISR_OFFSET);
 635                 }
 636         } while (pending_interrupts);
 637
 638         return IRQ_HANDLED;
 639 }
 640
 641 static int axis_fifo_open(struct inode *inod, struct file *f)
 642 {
 643         struct axis_fifo *fifo = (struct axis_fifo *)container_of(inod->i_cdev,
 644                                         struct axis_fifo, char_device);
 645         f->private_data = fifo;
 646
 647         if (((f->f_flags & O_ACCMODE) == O_WRONLY) ||
 648             ((f->f_flags & O_ACCMODE) == O_RDWR)) {
 649                 if (fifo->has_tx_fifo) {
 650                         fifo->write_flags = f->f_flags;
 651                 } else {
 652                         dev_err(fifo->dt_device, "tried to open device for write but the transmit fifo is disabled\n");
 653                         return -EPERM;
 654                 }
 655         }
 656
 657         if (((f->f_flags & O_ACCMODE) == O_RDONLY) ||
 658             ((f->f_flags & O_ACCMODE) == O_RDWR)) {
 659                 if (fifo->has_rx_fifo) {
 660                         fifo->read_flags = f->f_flags;
 661                 } else {
 662                         dev_err(fifo->dt_device, "tried to open device for read but the receive fifo is disabled\n");
 663                         return -EPERM;
 664                 }
 665         }
 666
 667         return 0;
 668 }
 669
 670 static int axis_fifo_close(struct inode *inod, struct file *f)
 671 {
 672         f->private_data = NULL;
 673
 674         return 0;
 675 }
 676
 677 static const struct file_operations fops = {
 678         .owner = THIS_MODULE,
 679         .open = axis_fifo_open,
 680         .release = axis_fifo_close,
 681         .read = axis_fifo_read,
 682         .write = axis_fifo_write
 683 };
 684
 685 /* read named property from the device tree */
 686 static int get_dts_property(struct axis_fifo *fifo,
 687                             char *name, unsigned int *var)
 688 {
 689         int rc;
 690
 691         rc = of_property_read_u32(fifo->dt_device->of_node, name, var);
 692         if (rc) {
 693                 dev_err(fifo->dt_device, "couldn't read IP dts property '%s'",
 694                         name);
 695                 return rc;
 696         }
 697         dev_dbg(fifo->dt_device, "dts property '%s' = %u\n",
 698                 name, *var);
 699
 700         return 0;
 701 }
 702
 703 static int axis_fifo_parse_dt(struct axis_fifo *fifo)
 704 {
 705         int ret;
 706         unsigned int value;
 707
 708         ret = get_dts_property(fifo, "xlnx,axi-str-rxd-tdata-width", &value);
 709         if (ret) {
 710                 dev_err(fifo->dt_device, "missing xlnx,axi-str-rxd-tdata-width property\n");
 711                 goto end;
 712         } else if (value != 32) {
 713                 dev_err(fifo->dt_device, "xlnx,axi-str-rxd-tdata-width only supports 32 bits\n");
 714                 ret = -EIO;
 715                 goto end;
 716         }
 717
 718         ret = get_dts_property(fifo, "xlnx,axi-str-txd-tdata-width", &value);
 719         if (ret) {
 720                 dev_err(fifo->dt_device, "missing xlnx,axi-str-txd-tdata-width property\n");
 721                 goto end;
 722         } else if (value != 32) {
 723                 dev_err(fifo->dt_device, "xlnx,axi-str-txd-tdata-width only supports 32 bits\n");
 724                 ret = -EIO;
 725                 goto end;
 726         }
 727
 728         ret = get_dts_property(fifo, "xlnx,rx-fifo-depth",
 729                                &fifo->rx_fifo_depth);
 730         if (ret) {
 731                 dev_err(fifo->dt_device, "missing xlnx,rx-fifo-depth property\n");
 732                 ret = -EIO;
 733                 goto end;
 734         }
 735
 736         ret = get_dts_property(fifo, "xlnx,tx-fifo-depth",
 737                                &fifo->tx_fifo_depth);
 738         if (ret) {
 739                 dev_err(fifo->dt_device, "missing xlnx,tx-fifo-depth property\n");
 740                 ret = -EIO;
 741                 goto end;
 742         }
 743
 744         /* IP sets TDFV to fifo depth - 4 so we will do the same */
 745         fifo->tx_fifo_depth -= 4;
 746
 747         ret = get_dts_property(fifo, "xlnx,use-rx-data", &fifo->has_rx_fifo);
 748         if (ret) {
 749                 dev_err(fifo->dt_device, "missing xlnx,use-rx-data property\n");
 750                 ret = -EIO;
 751                 goto end;
 752         }
 753
 754         ret = get_dts_property(fifo, "xlnx,use-tx-data", &fifo->has_tx_fifo);
 755         if (ret) {
 756                 dev_err(fifo->dt_device, "missing xlnx,use-tx-data property\n");
 757                 ret = -EIO;
 758                 goto end;
 759         }
 760
 761 end:
 762         return ret;
 763 }
 764
 765 static int axis_fifo_probe(struct platform_device *pdev)
 766 {
 767         struct resource *r_irq; /* interrupt resources */
 768         struct resource *r_mem; /* IO mem resources */
 769         struct device *dev = &pdev->dev; /* OS device (from device tree) */
 770         struct axis_fifo *fifo = NULL;
 771
 772         char device_name[32];
 773
 774         int rc = 0; /* error return value */
 775
 776         /* ----------------------------
 777          *     init wrapper device
 778          * ----------------------------
 779          */
 780
 781         /* allocate device wrapper memory */
 782         fifo = devm_kmalloc(dev, sizeof(*fifo), GFP_KERNEL);
 783         if (!fifo)
 784                 return -ENOMEM;
 785
 786         dev_set_drvdata(dev, fifo);
 787         fifo->dt_device = dev;
 788
 789         init_waitqueue_head(&fifo->read_queue);
 790         init_waitqueue_head(&fifo->write_queue);
 791
 792         spin_lock_init(&fifo->read_queue_lock);
 793         spin_lock_init(&fifo->write_queue_lock);
 794
 795         /* ----------------------------
 796          *   init device memory space
 797          * ----------------------------
 798          */
 799
 800         /* get iospace for the device */
 801         r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 802         if (!r_mem) {
 803                 dev_err(fifo->dt_device, "invalid address\n");
 804                 rc = -ENODEV;
 805                 goto err_initial;
 806         }
 807
 808         /* request physical memory */
 809         fifo->base_addr = devm_ioremap_resource(fifo->dt_device, r_mem);
 810         if (IS_ERR(fifo->base_addr)) {
 811                 rc = PTR_ERR(fifo->base_addr);
 812                 dev_err(fifo->dt_device, "can't remap IO resource (%d)\n", rc);
 813                 goto err_initial;
 814         }
 815
 816         dev_dbg(fifo->dt_device, "remapped memory to 0x%p\n", fifo->base_addr);
 817
 818         /* create unique device name */
 819         snprintf(device_name, sizeof(device_name), "%s_%pa",
 820                  DRIVER_NAME, &r_mem->start);
 821
 822         dev_dbg(fifo->dt_device, "device name [%s]\n", device_name);
 823
 824         /* ----------------------------
 825          *          init IP
 826          * ----------------------------
 827          */
 828
 829         rc = axis_fifo_parse_dt(fifo);
 830         if (rc)
 831                 goto err_initial;
 832
 833         reset_ip_core(fifo);
 834
 835         /* ----------------------------
 836          *    init device interrupts
 837          * ----------------------------
 838          */
 839
 840         /* get IRQ resource */
 841         r_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 842         if (!r_irq) {
 843                 dev_err(fifo->dt_device, "no IRQ found for 0x%pa\n",
 844                         &r_mem->start);
 845                 rc = -EIO;
 846                 goto err_initial;
 847         }
 848
 849         /* request IRQ */
 850         fifo->irq = r_irq->start;
 851         rc = devm_request_irq(fifo->dt_device, fifo->irq, &axis_fifo_irq, 0,
 852                               DRIVER_NAME, fifo);
 853         if (rc) {
 854                 dev_err(fifo->dt_device, "couldn't allocate interrupt %i\n",
 855                         fifo->irq);
 856                 goto err_initial;
 857         }
 858
 859         /* ----------------------------
 860          *      init char device
 861          * ----------------------------
 862          */
 863
 864         /* allocate device number */
 865         rc = alloc_chrdev_region(&fifo->devt, 0, 1, DRIVER_NAME);
 866         if (rc < 0)
 867                 goto err_initial;
 868         dev_dbg(fifo->dt_device, "allocated device number major %i minor %i\n",
 869                 MAJOR(fifo->devt), MINOR(fifo->devt));
 870
 871         /* create driver file */
 872         fifo->device = device_create(axis_fifo_driver_class, NULL, fifo->devt,
 873                                      NULL, device_name);
 874         if (IS_ERR(fifo->device)) {
 875                 dev_err(fifo->dt_device,
 876                         "couldn't create driver file\n");
 877                 rc = PTR_ERR(fifo->device);
 878                 goto err_chrdev_region;
 879         }
 880         dev_set_drvdata(fifo->device, fifo);
 881
 882         /* create character device */
 883         cdev_init(&fifo->char_device, &fops);
 884         rc = cdev_add(&fifo->char_device, fifo->devt, 1);
 885         if (rc < 0) {
 886                 dev_err(fifo->dt_device, "couldn't create character device\n");
 887                 goto err_dev;
 888         }
 889
 890         /* create sysfs entries */
 891         rc = devm_device_add_group(fifo->device, &axis_fifo_attrs_group);
 892         if (rc < 0) {
 893                 dev_err(fifo->dt_device, "couldn't register sysfs group\n");
 894                 goto err_cdev;
 895         }
 896
 897         dev_info(fifo->dt_device, "axis-fifo created at %pa mapped to 0x%pa, irq=%i, major=%i, minor=%i\n",
 898                  &r_mem->start, &fifo->base_addr, fifo->irq,
 899                  MAJOR(fifo->devt), MINOR(fifo->devt));
 900
 901         return 0;
 902
 903 err_cdev:
 904         cdev_del(&fifo->char_device);
 905 err_dev:
 906         device_destroy(axis_fifo_driver_class, fifo->devt);
 907 err_chrdev_region:
 908         unregister_chrdev_region(fifo->devt, 1);
 909 err_initial:
 910         dev_set_drvdata(dev, NULL);
 911         return rc;
 912 }
 913
 914 static int axis_fifo_remove(struct platform_device *pdev)
 915 {
 916         struct device *dev = &pdev->dev;
 917         struct axis_fifo *fifo = dev_get_drvdata(dev);
 918
 919         cdev_del(&fifo->char_device);
 920         dev_set_drvdata(fifo->device, NULL);
 921         device_destroy(axis_fifo_driver_class, fifo->devt);
 922         unregister_chrdev_region(fifo->devt, 1);
 923         dev_set_drvdata(dev, NULL);
 924
 925         return 0;
 926 }
 927
 928 static const struct of_device_id axis_fifo_of_match[] = {
 929         { .compatible = "xlnx,axi-fifo-mm-s-4.1", },
 930         {},
 931 };
 932 MODULE_DEVICE_TABLE(of, axis_fifo_of_match);
 933
 934 static struct platform_driver axis_fifo_driver = {
 935         .driver = {
 936                 .name = DRIVER_NAME,
 937                 .of_match_table = axis_fifo_of_match,
 938         },
 939         .probe          = axis_fifo_probe,
 940         .remove         = axis_fifo_remove,
 941 };
 942
 943 static int __init axis_fifo_init(void)
 944 {
 945         pr_info("axis-fifo driver loaded with parameters read_timeout = %i, write_timeout = %i\n",
 946                 read_timeout, write_timeout);
 947         axis_fifo_driver_class = class_create(THIS_MODULE, DRIVER_NAME);
 948         if (IS_ERR(axis_fifo_driver_class))
 949                 return PTR_ERR(axis_fifo_driver_class);
 950         return platform_driver_register(&axis_fifo_driver);
 951 }
 952
 953 module_init(axis_fifo_init);
 954
 955 static void __exit axis_fifo_exit(void)
 956 {
 957         platform_driver_unregister(&axis_fifo_driver);
 958         class_destroy(axis_fifo_driver_class);
 959 }
 960
 961 module_exit(axis_fifo_exit);
 962
 963 MODULE_LICENSE("GPL");
 964 MODULE_AUTHOR("Jacob Feder <jacobsfeder@gmail.com>");
 965 MODULE_DESCRIPTION("Xilinx AXI-Stream FIFO v4.1 IP core driver");