drivers/staging/wilc1000/spi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
   4  * All rights reserved.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/spi/spi.h>
   9
  10 #include "netdev.h"
  11 #include "cfg80211.h"
  12
  13 struct wilc_spi {
  14         int crc_off;
  15         int nint;
  16         int has_thrpt_enh;
  17 };
  18
  19 static const struct wilc_hif_func wilc_hif_spi;
  20
  21 /********************************************
  22  *
  23  *      Crc7
  24  *
  25  ********************************************/
  26
  27 static const u8 crc7_syndrome_table[256] = {
  28         0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
  29         0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
  30         0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
  31         0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
  32         0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
  33         0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
  34         0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
  35         0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
  36         0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
  37         0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
  38         0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
  39         0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
  40         0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
  41         0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
  42         0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
  43         0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
  44         0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
  45         0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
  46         0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
  47         0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
  48         0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
  49         0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
  50         0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
  51         0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
  52         0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
  53         0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
  54         0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
  55         0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
  56         0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
  57         0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
  58         0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
  59         0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
  60 };
  61
  62 static u8 crc7_byte(u8 crc, u8 data)
  63 {
  64         return crc7_syndrome_table[(crc << 1) ^ data];
  65 }
  66
  67 static u8 crc7(u8 crc, const u8 *buffer, u32 len)
  68 {
  69         while (len--)
  70                 crc = crc7_byte(crc, *buffer++);
  71         return crc;
  72 }
  73
  74 /********************************************
  75  *
  76  *      Spi protocol Function
  77  *
  78  ********************************************/
  79
  80 #define CMD_DMA_WRITE                           0xc1
  81 #define CMD_DMA_READ                            0xc2
  82 #define CMD_INTERNAL_WRITE                      0xc3
  83 #define CMD_INTERNAL_READ                       0xc4
  84 #define CMD_TERMINATE                           0xc5
  85 #define CMD_REPEAT                              0xc6
  86 #define CMD_DMA_EXT_WRITE                       0xc7
  87 #define CMD_DMA_EXT_READ                        0xc8
  88 #define CMD_SINGLE_WRITE                        0xc9
  89 #define CMD_SINGLE_READ                         0xca
  90 #define CMD_RESET                               0xcf
  91
  92 #define N_OK                                    1
  93 #define N_FAIL                                  0
  94 #define N_RESET                                 -1
  95 #define N_RETRY                                 -2
  96
  97 #define DATA_PKT_SZ_256                         256
  98 #define DATA_PKT_SZ_512                         512
  99 #define DATA_PKT_SZ_1K                          1024
 100 #define DATA_PKT_SZ_4K                          (4 * 1024)
 101 #define DATA_PKT_SZ_8K                          (8 * 1024)
 102 #define DATA_PKT_SZ                             DATA_PKT_SZ_8K
 103
 104 #define USE_SPI_DMA                             0
 105
 106 static int wilc_bus_probe(struct spi_device *spi)
 107 {
 108         int ret;
 109         struct wilc *wilc;
 110         struct gpio_desc *gpio;
 111         struct wilc_spi *spi_priv;
 112
 113         spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL);
 114         if (!spi_priv)
 115                 return -ENOMEM;
 116
 117         gpio = gpiod_get(&spi->dev, "irq", GPIOD_IN);
 118         if (IS_ERR(gpio)) {
 119                 /* get the GPIO descriptor from hardcode GPIO number */
 120                 gpio = gpio_to_desc(GPIO_NUM);
 121                 if (!gpio)
 122                         dev_err(&spi->dev, "failed to get the irq gpio\n");
 123         }
 124
 125         ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi);
 126         if (ret) {
 127                 kfree(spi_priv);
 128                 return ret;
 129         }
 130
 131         spi_set_drvdata(spi, wilc);
 132         wilc->dev = &spi->dev;
 133         wilc->bus_data = spi_priv;
 134         wilc->gpio_irq = gpio;
 135
 136         wilc->rtc_clk = devm_clk_get(&spi->dev, "rtc_clk");
 137         if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER)
 138                 return -EPROBE_DEFER;
 139         else if (!IS_ERR(wilc->rtc_clk))
 140                 clk_prepare_enable(wilc->rtc_clk);
 141
 142         return 0;
 143 }
 144
 145 static int wilc_bus_remove(struct spi_device *spi)
 146 {
 147         struct wilc *wilc = spi_get_drvdata(spi);
 148
 149         /* free the GPIO in module remove */
 150         if (wilc->gpio_irq)
 151                 gpiod_put(wilc->gpio_irq);
 152
 153         if (!IS_ERR(wilc->rtc_clk))
 154                 clk_disable_unprepare(wilc->rtc_clk);
 155
 156         wilc_netdev_cleanup(wilc);
 157         return 0;
 158 }
 159
 160 static const struct of_device_id wilc_of_match[] = {
 161         { .compatible = "microchip,wilc1000-spi", },
 162         { /* sentinel */ }
 163 };
 164 MODULE_DEVICE_TABLE(of, wilc_of_match);
 165
 166 static struct spi_driver wilc_spi_driver = {
 167         .driver = {
 168                 .name = MODALIAS,
 169                 .of_match_table = wilc_of_match,
 170         },
 171         .probe =  wilc_bus_probe,
 172         .remove = wilc_bus_remove,
 173 };
 174 module_spi_driver(wilc_spi_driver);
 175 MODULE_LICENSE("GPL");
 176
 177 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
 178 {
 179         struct spi_device *spi = to_spi_device(wilc->dev);
 180         int ret;
 181         struct spi_message msg;
 182
 183         if (len > 0 && b) {
 184                 struct spi_transfer tr = {
 185                         .tx_buf = b,
 186                         .len = len,
 187                         .delay_usecs = 0,
 188                 };
 189                 char *r_buffer = kzalloc(len, GFP_KERNEL);
 190
 191                 if (!r_buffer)
 192                         return -ENOMEM;
 193
 194                 tr.rx_buf = r_buffer;
 195                 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
 196
 197                 memset(&msg, 0, sizeof(msg));
 198                 spi_message_init(&msg);
 199                 msg.spi = spi;
 200                 msg.is_dma_mapped = USE_SPI_DMA;
 201                 spi_message_add_tail(&tr, &msg);
 202
 203                 ret = spi_sync(spi, &msg);
 204                 if (ret < 0)
 205                         dev_err(&spi->dev, "SPI transaction failed\n");
 206
 207                 kfree(r_buffer);
 208         } else {
 209                 dev_err(&spi->dev,
 210                         "can't write data with the following length: %d\n",
 211                         len);
 212                 ret = -EINVAL;
 213         }
 214
 215         return ret;
 216 }
 217
 218 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
 219 {
 220         struct spi_device *spi = to_spi_device(wilc->dev);
 221         int ret;
 222
 223         if (rlen > 0) {
 224                 struct spi_message msg;
 225                 struct spi_transfer tr = {
 226                         .rx_buf = rb,
 227                         .len = rlen,
 228                         .delay_usecs = 0,
 229
 230                 };
 231                 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
 232
 233                 if (!t_buffer)
 234                         return -ENOMEM;
 235
 236                 tr.tx_buf = t_buffer;
 237
 238                 memset(&msg, 0, sizeof(msg));
 239                 spi_message_init(&msg);
 240                 msg.spi = spi;
 241                 msg.is_dma_mapped = USE_SPI_DMA;
 242                 spi_message_add_tail(&tr, &msg);
 243
 244                 ret = spi_sync(spi, &msg);
 245                 if (ret < 0)
 246                         dev_err(&spi->dev, "SPI transaction failed\n");
 247                 kfree(t_buffer);
 248         } else {
 249                 dev_err(&spi->dev,
 250                         "can't read data with the following length: %u\n",
 251                         rlen);
 252                 ret = -EINVAL;
 253         }
 254
 255         return ret;
 256 }
 257
 258 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
 259 {
 260         struct spi_device *spi = to_spi_device(wilc->dev);
 261         int ret;
 262
 263         if (rlen > 0) {
 264                 struct spi_message msg;
 265                 struct spi_transfer tr = {
 266                         .rx_buf = rb,
 267                         .tx_buf = wb,
 268                         .len = rlen,
 269                         .bits_per_word = 8,
 270                         .delay_usecs = 0,
 271
 272                 };
 273
 274                 memset(&msg, 0, sizeof(msg));
 275                 spi_message_init(&msg);
 276                 msg.spi = spi;
 277                 msg.is_dma_mapped = USE_SPI_DMA;
 278
 279                 spi_message_add_tail(&tr, &msg);
 280                 ret = spi_sync(spi, &msg);
 281                 if (ret < 0)
 282                         dev_err(&spi->dev, "SPI transaction failed\n");
 283         } else {
 284                 dev_err(&spi->dev,
 285                         "can't read data with the following length: %u\n",
 286                         rlen);
 287                 ret = -EINVAL;
 288         }
 289
 290         return ret;
 291 }
 292
 293 static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
 294                             u8 clockless)
 295 {
 296         struct spi_device *spi = to_spi_device(wilc->dev);
 297         struct wilc_spi *spi_priv = wilc->bus_data;
 298         u8 wb[32], rb[32];
 299         u8 wix, rix;
 300         u32 len2;
 301         u8 rsp;
 302         int len = 0;
 303         int result = N_OK;
 304         int retry;
 305         u8 crc[2];
 306
 307         wb[0] = cmd;
 308         switch (cmd) {
 309         case CMD_SINGLE_READ: /* single word (4 bytes) read */
 310                 wb[1] = (u8)(adr >> 16);
 311                 wb[2] = (u8)(adr >> 8);
 312                 wb[3] = (u8)adr;
 313                 len = 5;
 314                 break;
 315
 316         case CMD_INTERNAL_READ: /* internal register read */
 317                 wb[1] = (u8)(adr >> 8);
 318                 if (clockless == 1)
 319                         wb[1] |= BIT(7);
 320                 wb[2] = (u8)adr;
 321                 wb[3] = 0x00;
 322                 len = 5;
 323                 break;
 324
 325         case CMD_TERMINATE:
 326                 wb[1] = 0x00;
 327                 wb[2] = 0x00;
 328                 wb[3] = 0x00;
 329                 len = 5;
 330                 break;
 331
 332         case CMD_REPEAT:
 333                 wb[1] = 0x00;
 334                 wb[2] = 0x00;
 335                 wb[3] = 0x00;
 336                 len = 5;
 337                 break;
 338
 339         case CMD_RESET:
 340                 wb[1] = 0xff;
 341                 wb[2] = 0xff;
 342                 wb[3] = 0xff;
 343                 len = 5;
 344                 break;
 345
 346         case CMD_DMA_WRITE: /* dma write */
 347         case CMD_DMA_READ:  /* dma read */
 348                 wb[1] = (u8)(adr >> 16);
 349                 wb[2] = (u8)(adr >> 8);
 350                 wb[3] = (u8)adr;
 351                 wb[4] = (u8)(sz >> 8);
 352                 wb[5] = (u8)(sz);
 353                 len = 7;
 354                 break;
 355
 356         case CMD_DMA_EXT_WRITE: /* dma extended write */
 357         case CMD_DMA_EXT_READ:  /* dma extended read */
 358                 wb[1] = (u8)(adr >> 16);
 359                 wb[2] = (u8)(adr >> 8);
 360                 wb[3] = (u8)adr;
 361                 wb[4] = (u8)(sz >> 16);
 362                 wb[5] = (u8)(sz >> 8);
 363                 wb[6] = (u8)(sz);
 364                 len = 8;
 365                 break;
 366
 367         case CMD_INTERNAL_WRITE: /* internal register write */
 368                 wb[1] = (u8)(adr >> 8);
 369                 if (clockless == 1)
 370                         wb[1] |= BIT(7);
 371                 wb[2] = (u8)(adr);
 372                 wb[3] = b[3];
 373                 wb[4] = b[2];
 374                 wb[5] = b[1];
 375                 wb[6] = b[0];
 376                 len = 8;
 377                 break;
 378
 379         case CMD_SINGLE_WRITE: /* single word write */
 380                 wb[1] = (u8)(adr >> 16);
 381                 wb[2] = (u8)(adr >> 8);
 382                 wb[3] = (u8)(adr);
 383                 wb[4] = b[3];
 384                 wb[5] = b[2];
 385                 wb[6] = b[1];
 386                 wb[7] = b[0];
 387                 len = 9;
 388                 break;
 389
 390         default:
 391                 result = N_FAIL;
 392                 break;
 393         }
 394
 395         if (result != N_OK)
 396                 return result;
 397
 398         if (!spi_priv->crc_off)
 399                 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
 400         else
 401                 len -= 1;
 402
 403 #define NUM_SKIP_BYTES (1)
 404 #define NUM_RSP_BYTES (2)
 405 #define NUM_DATA_HDR_BYTES (1)
 406 #define NUM_DATA_BYTES (4)
 407 #define NUM_CRC_BYTES (2)
 408 #define NUM_DUMMY_BYTES (3)
 409         if (cmd == CMD_RESET ||
 410             cmd == CMD_TERMINATE ||
 411             cmd == CMD_REPEAT) {
 412                 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 413         } else if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
 414                 int tmp = NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 415                         + NUM_DUMMY_BYTES;
 416                 if (!spi_priv->crc_off)
 417                         len2 = len + tmp + NUM_CRC_BYTES;
 418                 else
 419                         len2 = len + tmp;
 420         } else {
 421                 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 422         }
 423 #undef NUM_DUMMY_BYTES
 424
 425         if (len2 > ARRAY_SIZE(wb)) {
 426                 dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
 427                         len2, ARRAY_SIZE(wb));
 428                 return N_FAIL;
 429         }
 430         /* zero spi write buffers. */
 431         for (wix = len; wix < len2; wix++)
 432                 wb[wix] = 0;
 433         rix = len;
 434
 435         if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
 436                 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
 437                 return N_FAIL;
 438         }
 439
 440         /*
 441          * Command/Control response
 442          */
 443         if (cmd == CMD_RESET || cmd == CMD_TERMINATE || cmd == CMD_REPEAT)
 444                 rix++; /* skip 1 byte */
 445
 446         rsp = rb[rix++];
 447
 448         if (rsp != cmd) {
 449                 dev_err(&spi->dev,
 450                         "Failed cmd response, cmd (%02x), resp (%02x)\n",
 451                         cmd, rsp);
 452                 return N_FAIL;
 453         }
 454
 455         /*
 456          * State response
 457          */
 458         rsp = rb[rix++];
 459         if (rsp != 0x00) {
 460                 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
 461                         rsp);
 462                 return N_FAIL;
 463         }
 464
 465         if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ ||
 466             cmd == CMD_DMA_READ || cmd == CMD_DMA_EXT_READ) {
 467                 /*
 468                  * Data Respnose header
 469                  */
 470                 retry = 100;
 471                 do {
 472                         /*
 473                          * ensure there is room in buffer later
 474                          * to read data and crc
 475                          */
 476                         if (rix < len2) {
 477                                 rsp = rb[rix++];
 478                         } else {
 479                                 retry = 0;
 480                                 break;
 481                         }
 482                         if (((rsp >> 4) & 0xf) == 0xf)
 483                                 break;
 484                 } while (retry--);
 485
 486                 if (retry <= 0) {
 487                         dev_err(&spi->dev,
 488                                 "Error, data read response (%02x)\n", rsp);
 489                         return N_RESET;
 490                 }
 491         }
 492
 493         if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
 494                 /*
 495                  * Read bytes
 496                  */
 497                 if ((rix + 3) < len2) {
 498                         b[0] = rb[rix++];
 499                         b[1] = rb[rix++];
 500                         b[2] = rb[rix++];
 501                         b[3] = rb[rix++];
 502                 } else {
 503                         dev_err(&spi->dev,
 504                                 "buffer overrun when reading data.\n");
 505                         return N_FAIL;
 506                 }
 507
 508                 if (!spi_priv->crc_off) {
 509                         /*
 510                          * Read Crc
 511                          */
 512                         if ((rix + 1) < len2) {
 513                                 crc[0] = rb[rix++];
 514                                 crc[1] = rb[rix++];
 515                         } else {
 516                                 dev_err(&spi->dev,
 517                                         "buffer overrun when reading crc.\n");
 518                                 return N_FAIL;
 519                         }
 520                 }
 521         } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 522                 int ix;
 523
 524                 /* some data may be read in response to dummy bytes. */
 525                 for (ix = 0; (rix < len2) && (ix < sz); )
 526                         b[ix++] = rb[rix++];
 527
 528                 sz -= ix;
 529
 530                 if (sz > 0) {
 531                         int nbytes;
 532
 533                         if (sz <= (DATA_PKT_SZ - ix))
 534                                 nbytes = sz;
 535                         else
 536                                 nbytes = DATA_PKT_SZ - ix;
 537
 538                         /*
 539                          * Read bytes
 540                          */
 541                         if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 542                                 dev_err(&spi->dev,
 543                                         "Failed block read, bus err\n");
 544                                 return N_FAIL;
 545                         }
 546
 547                         /*
 548                          * Read Crc
 549                          */
 550                         if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
 551                                 dev_err(&spi->dev,
 552                                         "Failed block crc read, bus err\n");
 553                                 return N_FAIL;
 554                         }
 555
 556                         ix += nbytes;
 557                         sz -= nbytes;
 558                 }
 559
 560                 /*
 561                  * if any data in left unread,
 562                  * then read the rest using normal DMA code.
 563                  */
 564                 while (sz > 0) {
 565                         int nbytes;
 566
 567                         if (sz <= DATA_PKT_SZ)
 568                                 nbytes = sz;
 569                         else
 570                                 nbytes = DATA_PKT_SZ;
 571
 572                         /*
 573                          * read data response only on the next DMA cycles not
 574                          * the first DMA since data response header is already
 575                          * handled above for the first DMA.
 576                          */
 577                         /*
 578                          * Data Respnose header
 579                          */
 580                         retry = 10;
 581                         do {
 582                                 if (wilc_spi_rx(wilc, &rsp, 1)) {
 583                                         dev_err(&spi->dev,
 584                                                 "Failed resp read, bus err\n");
 585                                         result = N_FAIL;
 586                                         break;
 587                                 }
 588                                 if (((rsp >> 4) & 0xf) == 0xf)
 589                                         break;
 590                         } while (retry--);
 591
 592                         if (result == N_FAIL)
 593                                 break;
 594
 595                         /*
 596                          * Read bytes
 597                          */
 598                         if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 599                                 dev_err(&spi->dev,
 600                                         "Failed block read, bus err\n");
 601                                 result = N_FAIL;
 602                                 break;
 603                         }
 604
 605                         /*
 606                          * Read Crc
 607                          */
 608                         if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
 609                                 dev_err(&spi->dev,
 610                                         "Failed block crc read, bus err\n");
 611                                 result = N_FAIL;
 612                                 break;
 613                         }
 614
 615                         ix += nbytes;
 616                         sz -= nbytes;
 617                 }
 618         }
 619         return result;
 620 }
 621
 622 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
 623 {
 624         struct spi_device *spi = to_spi_device(wilc->dev);
 625         struct wilc_spi *spi_priv = wilc->bus_data;
 626         int ix, nbytes;
 627         int result = 1;
 628         u8 cmd, order, crc[2] = {0};
 629
 630         /*
 631          * Data
 632          */
 633         ix = 0;
 634         do {
 635                 if (sz <= DATA_PKT_SZ) {
 636                         nbytes = sz;
 637                         order = 0x3;
 638                 } else {
 639                         nbytes = DATA_PKT_SZ;
 640                         if (ix == 0)
 641                                 order = 0x1;
 642                         else
 643                                 order = 0x02;
 644                 }
 645
 646                 /*
 647                  * Write command
 648                  */
 649                 cmd = 0xf0;
 650                 cmd |= order;
 651
 652                 if (wilc_spi_tx(wilc, &cmd, 1)) {
 653                         dev_err(&spi->dev,
 654                                 "Failed data block cmd write, bus error...\n");
 655                         result = N_FAIL;
 656                         break;
 657                 }
 658
 659                 /*
 660                  * Write data
 661                  */
 662                 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
 663                         dev_err(&spi->dev,
 664                                 "Failed data block write, bus error...\n");
 665                         result = N_FAIL;
 666                         break;
 667                 }
 668
 669                 /*
 670                  * Write Crc
 671                  */
 672                 if (!spi_priv->crc_off) {
 673                         if (wilc_spi_tx(wilc, crc, 2)) {
 674                                 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
 675                                 result = N_FAIL;
 676                                 break;
 677                         }
 678                 }
 679
 680                 /*
 681                  * No need to wait for response
 682                  */
 683                 ix += nbytes;
 684                 sz -= nbytes;
 685         } while (sz);
 686
 687         return result;
 688 }
 689
 690 /********************************************
 691  *
 692  *      Spi Internal Read/Write Function
 693  *
 694  ********************************************/
 695
 696 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
 697 {
 698         struct spi_device *spi = to_spi_device(wilc->dev);
 699         int result;
 700
 701         cpu_to_le32s(&dat);
 702         result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
 703                                   0);
 704         if (result != N_OK)
 705                 dev_err(&spi->dev, "Failed internal write cmd...\n");
 706
 707         return result;
 708 }
 709
 710 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
 711 {
 712         struct spi_device *spi = to_spi_device(wilc->dev);
 713         int result;
 714
 715         result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
 716                                   0);
 717         if (result != N_OK) {
 718                 dev_err(&spi->dev, "Failed internal read cmd...\n");
 719                 return 0;
 720         }
 721
 722         le32_to_cpus(data);
 723
 724         return 1;
 725 }
 726
 727 /********************************************
 728  *
 729  *      Spi interfaces
 730  *
 731  ********************************************/
 732
 733 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
 734 {
 735         struct spi_device *spi = to_spi_device(wilc->dev);
 736         int result = N_OK;
 737         u8 cmd = CMD_SINGLE_WRITE;
 738         u8 clockless = 0;
 739
 740         cpu_to_le32s(&data);
 741         if (addr < 0x30) {
 742                 /* Clockless register */
 743                 cmd = CMD_INTERNAL_WRITE;
 744                 clockless = 1;
 745         }
 746
 747         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
 748         if (result != N_OK)
 749                 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
 750
 751         return result;
 752 }
 753
 754 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 755 {
 756         struct spi_device *spi = to_spi_device(wilc->dev);
 757         int result;
 758
 759         /*
 760          * has to be greated than 4
 761          */
 762         if (size <= 4)
 763                 return 0;
 764
 765         result = spi_cmd_complete(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size, 0);
 766         if (result != N_OK) {
 767                 dev_err(&spi->dev,
 768                         "Failed cmd, write block (%08x)...\n", addr);
 769                 return 0;
 770         }
 771
 772         /*
 773          * Data
 774          */
 775         result = spi_data_write(wilc, buf, size);
 776         if (result != N_OK)
 777                 dev_err(&spi->dev, "Failed block data write...\n");
 778
 779         return 1;
 780 }
 781
 782 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
 783 {
 784         struct spi_device *spi = to_spi_device(wilc->dev);
 785         int result = N_OK;
 786         u8 cmd = CMD_SINGLE_READ;
 787         u8 clockless = 0;
 788
 789         if (addr < 0x30) {
 790                 /* Clockless register */
 791                 cmd = CMD_INTERNAL_READ;
 792                 clockless = 1;
 793         }
 794
 795         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
 796         if (result != N_OK) {
 797                 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
 798                 return 0;
 799         }
 800
 801         le32_to_cpus(data);
 802
 803         return 1;
 804 }
 805
 806 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 807 {
 808         struct spi_device *spi = to_spi_device(wilc->dev);
 809         int result;
 810
 811         if (size <= 4)
 812                 return 0;
 813
 814         result = spi_cmd_complete(wilc, CMD_DMA_EXT_READ, addr, buf, size, 0);
 815         if (result != N_OK) {
 816                 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
 817                 return 0;
 818         }
 819
 820         return 1;
 821 }
 822
 823 /********************************************
 824  *
 825  *      Bus interfaces
 826  *
 827  ********************************************/
 828
 829 static int wilc_spi_deinit(struct wilc *wilc)
 830 {
 831         /*
 832          * TODO:
 833          */
 834         return 1;
 835 }
 836
 837 static int wilc_spi_init(struct wilc *wilc, bool resume)
 838 {
 839         struct spi_device *spi = to_spi_device(wilc->dev);
 840         struct wilc_spi *spi_priv = wilc->bus_data;
 841         u32 reg;
 842         u32 chipid;
 843         static int isinit;
 844
 845         if (isinit) {
 846                 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
 847                         dev_err(&spi->dev, "Fail cmd read chip id...\n");
 848                         return 0;
 849                 }
 850                 return 1;
 851         }
 852
 853         /*
 854          * configure protocol
 855          */
 856
 857         /*
 858          * TODO: We can remove the CRC trials if there is a definite
 859          * way to reset
 860          */
 861         /* the SPI to it's initial value. */
 862         if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 863                 /*
 864                  * Read failed. Try with CRC off. This might happen when module
 865                  * is removed but chip isn't reset
 866                  */
 867                 spi_priv->crc_off = 1;
 868                 dev_err(&spi->dev,
 869                         "Failed read with CRC on, retrying with CRC off\n");
 870                 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 871                         /*
 872                          * Read failed with both CRC on and off,
 873                          * something went bad
 874                          */
 875                         dev_err(&spi->dev, "Failed internal read protocol\n");
 876                         return 0;
 877                 }
 878         }
 879         if (spi_priv->crc_off == 0) {
 880                 reg &= ~0xc; /* disable crc checking */
 881                 reg &= ~0x70;
 882                 reg |= (0x5 << 4);
 883                 if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) {
 884                         dev_err(&spi->dev,
 885                                 "[wilc spi %d]: Failed internal write reg\n",
 886                                 __LINE__);
 887                         return 0;
 888                 }
 889                 spi_priv->crc_off = 1;
 890         }
 891
 892         /*
 893          * make sure can read back chip id correctly
 894          */
 895         if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
 896                 dev_err(&spi->dev, "Fail cmd read chip id...\n");
 897                 return 0;
 898         }
 899
 900         spi_priv->has_thrpt_enh = 1;
 901
 902         isinit = 1;
 903
 904         return 1;
 905 }
 906
 907 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
 908 {
 909         struct spi_device *spi = to_spi_device(wilc->dev);
 910         struct wilc_spi *spi_priv = wilc->bus_data;
 911         int ret;
 912
 913         if (spi_priv->has_thrpt_enh) {
 914                 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
 915                                         size);
 916                 *size = *size  & IRQ_DMA_WD_CNT_MASK;
 917         } else {
 918                 u32 tmp;
 919                 u32 byte_cnt;
 920
 921                 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
 922                                         &byte_cnt);
 923                 if (!ret) {
 924                         dev_err(&spi->dev,
 925                                 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
 926                         return ret;
 927                 }
 928                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
 929                 *size = tmp;
 930         }
 931
 932         return ret;
 933 }
 934
 935 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
 936 {
 937         struct spi_device *spi = to_spi_device(wilc->dev);
 938         struct wilc_spi *spi_priv = wilc->bus_data;
 939         int ret;
 940         u32 tmp;
 941         u32 byte_cnt;
 942         bool unexpected_irq;
 943         int j;
 944         u32 unknown_mask;
 945         u32 irq_flags;
 946         int k = IRG_FLAGS_OFFSET + 5;
 947
 948         if (spi_priv->has_thrpt_enh)
 949                 return spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
 950                                          int_status);
 951         ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE, &byte_cnt);
 952         if (!ret) {
 953                 dev_err(&spi->dev,
 954                         "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
 955                 return ret;
 956         }
 957         tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
 958
 959         j = 0;
 960         do {
 961                 wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
 962                 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
 963
 964                 if (spi_priv->nint > 5) {
 965                         wilc_spi_read_reg(wilc, 0x1a94, &irq_flags);
 966                         tmp |= (((irq_flags >> 0) & 0x7) << k);
 967                 }
 968
 969                 unknown_mask = ~((1ul << spi_priv->nint) - 1);
 970
 971                 unexpected_irq = (tmp >> IRG_FLAGS_OFFSET) & unknown_mask;
 972                 if (unexpected_irq) {
 973                         dev_err(&spi->dev,
 974                                 "Unexpected interrupt(2):j=%d,tmp=%x,mask=%x\n",
 975                                 j, tmp, unknown_mask);
 976                 }
 977
 978                 j++;
 979         } while (unexpected_irq);
 980
 981         *int_status = tmp;
 982
 983         return ret;
 984 }
 985
 986 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
 987 {
 988         struct spi_device *spi = to_spi_device(wilc->dev);
 989         struct wilc_spi *spi_priv = wilc->bus_data;
 990         int ret;
 991         u32 flags;
 992         u32 tbl_ctl;
 993
 994         if (spi_priv->has_thrpt_enh) {
 995                 return spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE,
 996                                           val);
 997         }
 998
 999         flags = val & (BIT(MAX_NUM_INT) - 1);
1000         if (flags) {
1001                 int i;
1002
1003                 ret = 1;
1004                 for (i = 0; i < spi_priv->nint; i++) {
1005                         /*
1006                          * No matter what you write 1 or 0,
1007                          * it will clear interrupt.
1008                          */
1009                         if (flags & 1)
1010                                 ret = wilc_spi_write_reg(wilc,
1011                                                          0x10c8 + i * 4, 1);
1012                         if (!ret)
1013                                 break;
1014                         flags >>= 1;
1015                 }
1016                 if (!ret) {
1017                         dev_err(&spi->dev,
1018                                 "Failed wilc_spi_write_reg, set reg %x ...\n",
1019                                 0x10c8 + i * 4);
1020                         return ret;
1021                 }
1022                 for (i = spi_priv->nint; i < MAX_NUM_INT; i++) {
1023                         if (flags & 1)
1024                                 dev_err(&spi->dev,
1025                                         "Unexpected interrupt cleared %d...\n",
1026                                         i);
1027                         flags >>= 1;
1028                 }
1029         }
1030
1031         tbl_ctl = 0;
1032         /* select VMM table 0 */
1033         if (val & SEL_VMM_TBL0)
1034                 tbl_ctl |= BIT(0);
1035         /* select VMM table 1 */
1036         if (val & SEL_VMM_TBL1)
1037                 tbl_ctl |= BIT(1);
1038
1039         ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL, tbl_ctl);
1040         if (!ret) {
1041                 dev_err(&spi->dev, "fail write reg vmm_tbl_ctl...\n");
1042                 return ret;
1043         }
1044
1045         if (val & EN_VMM) {
1046                 /*
1047                  * enable vmm transfer.
1048                  */
1049                 ret = wilc_spi_write_reg(wilc, WILC_VMM_CORE_CTL, 1);
1050                 if (!ret) {
1051                         dev_err(&spi->dev, "fail write reg vmm_core_ctl...\n");
1052                         return ret;
1053                 }
1054         }
1055
1056         return ret;
1057 }
1058
1059 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1060 {
1061         struct spi_device *spi = to_spi_device(wilc->dev);
1062         struct wilc_spi *spi_priv = wilc->bus_data;
1063         u32 reg;
1064         int ret, i;
1065
1066         if (nint > MAX_NUM_INT) {
1067                 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1068                 return 0;
1069         }
1070
1071         spi_priv->nint = nint;
1072
1073         /*
1074          * interrupt pin mux select
1075          */
1076         ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, &reg);
1077         if (!ret) {
1078                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1079                         WILC_PIN_MUX_0);
1080                 return 0;
1081         }
1082         reg |= BIT(8);
1083         ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1084         if (!ret) {
1085                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1086                         WILC_PIN_MUX_0);
1087                 return 0;
1088         }
1089
1090         /*
1091          * interrupt enable
1092          */
1093         ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, &reg);
1094         if (!ret) {
1095                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1096                         WILC_INTR_ENABLE);
1097                 return 0;
1098         }
1099
1100         for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1101                 reg |= (BIT((27 + i)));
1102
1103         ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1104         if (!ret) {
1105                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1106                         WILC_INTR_ENABLE);
1107                 return 0;
1108         }
1109         if (nint) {
1110                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1111                 if (!ret) {
1112                         dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1113                                 WILC_INTR2_ENABLE);
1114                         return 0;
1115                 }
1116
1117                 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1118                         reg |= BIT(i);
1119
1120                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1121                 if (!ret) {
1122                         dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1123                                 WILC_INTR2_ENABLE);
1124                         return 0;
1125                 }
1126         }
1127
1128         return 1;
1129 }
1130
1131 /* Global spi HIF function table */
1132 static const struct wilc_hif_func wilc_hif_spi = {
1133         .hif_init = wilc_spi_init,
1134         .hif_deinit = wilc_spi_deinit,
1135         .hif_read_reg = wilc_spi_read_reg,
1136         .hif_write_reg = wilc_spi_write_reg,
1137         .hif_block_rx = wilc_spi_read,
1138         .hif_block_tx = wilc_spi_write,
1139         .hif_read_int = wilc_spi_read_int,
1140         .hif_clear_int_ext = wilc_spi_clear_int_ext,
1141         .hif_read_size = wilc_spi_read_size,
1142         .hif_block_tx_ext = wilc_spi_write,
1143         .hif_block_rx_ext = wilc_spi_read,
1144         .hif_sync_ext = wilc_spi_sync_ext,
1145 };