drivers/usb/chipidea/ci.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ci.h - common structures, functions, and macros of the ChipIdea driver
   4  *
   5  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   6  *
   7  * Author: David Lopo
   8  */
   9
  10 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
  11 #define __DRIVERS_USB_CHIPIDEA_CI_H
  12
  13 #include <linux/list.h>
  14 #include <linux/irqreturn.h>
  15 #include <linux/usb.h>
  16 #include <linux/usb/gadget.h>
  17 #include <linux/usb/otg-fsm.h>
  18 #include <linux/usb/otg.h>
  19 #include <linux/usb/role.h>
  20 #include <linux/ulpi/interface.h>
  21
  22 /******************************************************************************
  23  * DEFINE
  24  *****************************************************************************/
  25 #define TD_PAGE_COUNT      5
  26 #define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
  27 #define ENDPT_MAX          32
  28
  29 /******************************************************************************
  30  * REGISTERS
  31  *****************************************************************************/
  32 /* Identification Registers */
  33 #define ID_ID                           0x0
  34 #define ID_HWGENERAL                    0x4
  35 #define ID_HWHOST                       0x8
  36 #define ID_HWDEVICE                     0xc
  37 #define ID_HWTXBUF                      0x10
  38 #define ID_HWRXBUF                      0x14
  39 #define ID_SBUSCFG                      0x90
  40
  41 /* register indices */
  42 enum ci_hw_regs {
  43         CAP_CAPLENGTH,
  44         CAP_HCCPARAMS,
  45         CAP_DCCPARAMS,
  46         CAP_TESTMODE,
  47         CAP_LAST = CAP_TESTMODE,
  48         OP_USBCMD,
  49         OP_USBSTS,
  50         OP_USBINTR,
  51         OP_DEVICEADDR,
  52         OP_ENDPTLISTADDR,
  53         OP_TTCTRL,
  54         OP_BURSTSIZE,
  55         OP_ULPI_VIEWPORT,
  56         OP_PORTSC,
  57         OP_DEVLC,
  58         OP_OTGSC,
  59         OP_USBMODE,
  60         OP_ENDPTSETUPSTAT,
  61         OP_ENDPTPRIME,
  62         OP_ENDPTFLUSH,
  63         OP_ENDPTSTAT,
  64         OP_ENDPTCOMPLETE,
  65         OP_ENDPTCTRL,
  66         /* endptctrl1..15 follow */
  67         OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
  68 };
  69
  70 /******************************************************************************
  71  * STRUCTURES
  72  *****************************************************************************/
  73 /**
  74  * struct ci_hw_ep - endpoint representation
  75  * @ep: endpoint structure for gadget drivers
  76  * @dir: endpoint direction (TX/RX)
  77  * @num: endpoint number
  78  * @type: endpoint type
  79  * @name: string description of the endpoint
  80  * @qh: queue head for this endpoint
  81  * @wedge: is the endpoint wedged
  82  * @ci: pointer to the controller
  83  * @lock: pointer to controller's spinlock
  84  * @td_pool: pointer to controller's TD pool
  85  */
  86 struct ci_hw_ep {
  87         struct usb_ep                           ep;
  88         u8                                      dir;
  89         u8                                      num;
  90         u8                                      type;
  91         char                                    name[16];
  92         struct {
  93                 struct list_head        queue;
  94                 struct ci_hw_qh         *ptr;
  95                 dma_addr_t              dma;
  96         }                                       qh;
  97         int                                     wedge;
  98
  99         /* global resources */
 100         struct ci_hdrc                          *ci;
 101         spinlock_t                              *lock;
 102         struct dma_pool                         *td_pool;
 103         struct td_node                          *pending_td;
 104 };
 105
 106 enum ci_role {
 107         CI_ROLE_HOST = 0,
 108         CI_ROLE_GADGET,
 109         CI_ROLE_END,
 110 };
 111
 112 enum ci_revision {
 113         CI_REVISION_1X = 10,    /* Revision 1.x */
 114         CI_REVISION_20 = 20, /* Revision 2.0 */
 115         CI_REVISION_21, /* Revision 2.1 */
 116         CI_REVISION_22, /* Revision 2.2 */
 117         CI_REVISION_23, /* Revision 2.3 */
 118         CI_REVISION_24, /* Revision 2.4 */
 119         CI_REVISION_25, /* Revision 2.5 */
 120         CI_REVISION_25_PLUS, /* Revision above than 2.5 */
 121         CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
 122 };
 123
 124 /**
 125  * struct ci_role_driver - host/gadget role driver
 126  * @start: start this role
 127  * @stop: stop this role
 128  * @irq: irq handler for this role
 129  * @name: role name string (host/gadget)
 130  */
 131 struct ci_role_driver {
 132         int             (*start)(struct ci_hdrc *);
 133         void            (*stop)(struct ci_hdrc *);
 134         irqreturn_t     (*irq)(struct ci_hdrc *);
 135         const char      *name;
 136 };
 137
 138 /**
 139  * struct hw_bank - hardware register mapping representation
 140  * @lpm: set if the device is LPM capable
 141  * @phys: physical address of the controller's registers
 142  * @abs: absolute address of the beginning of register window
 143  * @cap: capability registers
 144  * @op: operational registers
 145  * @size: size of the register window
 146  * @regmap: register lookup table
 147  */
 148 struct hw_bank {
 149         unsigned        lpm;
 150         resource_size_t phys;
 151         void __iomem    *abs;
 152         void __iomem    *cap;
 153         void __iomem    *op;
 154         size_t          size;
 155         void __iomem    *regmap[OP_LAST + 1];
 156 };
 157
 158 /**
 159  * struct ci_hdrc - chipidea device representation
 160  * @dev: pointer to parent device
 161  * @lock: access synchronization
 162  * @hw_bank: hardware register mapping
 163  * @irq: IRQ number
 164  * @roles: array of supported roles for this controller
 165  * @role: current role
 166  * @is_otg: if the device is otg-capable
 167  * @fsm: otg finite state machine
 168  * @otg_fsm_hrtimer: hrtimer for otg fsm timers
 169  * @hr_timeouts: time out list for active otg fsm timers
 170  * @enabled_otg_timer_bits: bits of enabled otg timers
 171  * @next_otg_timer: next nearest enabled timer to be expired
 172  * @work: work for role changing
 173  * @wq: workqueue thread
 174  * @qh_pool: allocation pool for queue heads
 175  * @td_pool: allocation pool for transfer descriptors
 176  * @gadget: device side representation for peripheral controller
 177  * @driver: gadget driver
 178  * @resume_state: save the state of gadget suspend from
 179  * @hw_ep_max: total number of endpoints supported by hardware
 180  * @ci_hw_ep: array of endpoints
 181  * @ep0_dir: ep0 direction
 182  * @ep0out: pointer to ep0 OUT endpoint
 183  * @ep0in: pointer to ep0 IN endpoint
 184  * @status: ep0 status request
 185  * @setaddr: if we should set the address on status completion
 186  * @address: usb address received from the host
 187  * @remote_wakeup: host-enabled remote wakeup
 188  * @suspended: suspended by host
 189  * @test_mode: the selected test mode
 190  * @platdata: platform specific information supplied by parent device
 191  * @vbus_active: is VBUS active
 192  * @ulpi: pointer to ULPI device, if any
 193  * @ulpi_ops: ULPI read/write ops for this device
 194  * @phy: pointer to PHY, if any
 195  * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
 196  * @hcd: pointer to usb_hcd for ehci host driver
 197  * @debugfs: root dentry for this controller in debugfs
 198  * @id_event: indicates there is an id event, and handled at ci_otg_work
 199  * @b_sess_valid_event: indicates there is a vbus event, and handled
 200  * at ci_otg_work
 201  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
 202  * @supports_runtime_pm: if runtime pm is supported
 203  * @in_lpm: if the core in low power mode
 204  * @wakeup_int: if wakeup interrupt occur
 205  * @rev: The revision number for controller
 206  */
 207 struct ci_hdrc {
 208         struct device                   *dev;
 209         spinlock_t                      lock;
 210         struct hw_bank                  hw_bank;
 211         int                             irq;
 212         struct ci_role_driver           *roles[CI_ROLE_END];
 213         enum ci_role                    role;
 214         bool                            is_otg;
 215         struct usb_otg                  otg;
 216         struct otg_fsm                  fsm;
 217         struct hrtimer                  otg_fsm_hrtimer;
 218         ktime_t                         hr_timeouts[NUM_OTG_FSM_TIMERS];
 219         unsigned                        enabled_otg_timer_bits;
 220         enum otg_fsm_timer              next_otg_timer;
 221         struct usb_role_switch          *role_switch;
 222         struct work_struct              work;
 223         struct workqueue_struct         *wq;
 224
 225         struct dma_pool                 *qh_pool;
 226         struct dma_pool                 *td_pool;
 227
 228         struct usb_gadget               gadget;
 229         struct usb_gadget_driver        *driver;
 230         enum usb_device_state           resume_state;
 231         unsigned                        hw_ep_max;
 232         struct ci_hw_ep                 ci_hw_ep[ENDPT_MAX];
 233         u32                             ep0_dir;
 234         struct ci_hw_ep                 *ep0out, *ep0in;
 235
 236         struct usb_request              *status;
 237         bool                            setaddr;
 238         u8                              address;
 239         u8                              remote_wakeup;
 240         u8                              suspended;
 241         u8                              test_mode;
 242
 243         struct ci_hdrc_platform_data    *platdata;
 244         int                             vbus_active;
 245         struct ulpi                     *ulpi;
 246         struct ulpi_ops                 ulpi_ops;
 247         struct phy                      *phy;
 248         /* old usb_phy interface */
 249         struct usb_phy                  *usb_phy;
 250         struct usb_hcd                  *hcd;
 251         struct dentry                   *debugfs;
 252         bool                            id_event;
 253         bool                            b_sess_valid_event;
 254         bool                            imx28_write_fix;
 255         bool                            supports_runtime_pm;
 256         bool                            in_lpm;
 257         bool                            wakeup_int;
 258         enum ci_revision                rev;
 259 };
 260
 261 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
 262 {
 263         BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
 264         return ci->roles[ci->role];
 265 }
 266
 267 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
 268 {
 269         int ret;
 270
 271         if (role >= CI_ROLE_END)
 272                 return -EINVAL;
 273
 274         if (!ci->roles[role])
 275                 return -ENXIO;
 276
 277         ret = ci->roles[role]->start(ci);
 278         if (!ret)
 279                 ci->role = role;
 280         return ret;
 281 }
 282
 283 static inline void ci_role_stop(struct ci_hdrc *ci)
 284 {
 285         enum ci_role role = ci->role;
 286
 287         if (role == CI_ROLE_END)
 288                 return;
 289
 290         ci->role = CI_ROLE_END;
 291
 292         ci->roles[role]->stop(ci);
 293 }
 294
 295 static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci)
 296 {
 297         if (ci->role == CI_ROLE_HOST)
 298                 return USB_ROLE_HOST;
 299         else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)
 300                 return USB_ROLE_DEVICE;
 301         else
 302                 return USB_ROLE_NONE;
 303 }
 304
 305 /**
 306  * hw_read_id_reg: reads from a identification register
 307  * @ci: the controller
 308  * @offset: offset from the beginning of identification registers region
 309  * @mask: bitfield mask
 310  *
 311  * This function returns register contents
 312  */
 313 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
 314 {
 315         return ioread32(ci->hw_bank.abs + offset) & mask;
 316 }
 317
 318 /**
 319  * hw_write_id_reg: writes to a identification register
 320  * @ci: the controller
 321  * @offset: offset from the beginning of identification registers region
 322  * @mask: bitfield mask
 323  * @data: new value
 324  */
 325 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
 326                             u32 mask, u32 data)
 327 {
 328         if (~mask)
 329                 data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
 330                         | (data & mask);
 331
 332         iowrite32(data, ci->hw_bank.abs + offset);
 333 }
 334
 335 /**
 336  * hw_read: reads from a hw register
 337  * @ci: the controller
 338  * @reg:  register index
 339  * @mask: bitfield mask
 340  *
 341  * This function returns register contents
 342  */
 343 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
 344 {
 345         return ioread32(ci->hw_bank.regmap[reg]) & mask;
 346 }
 347
 348 #ifdef CONFIG_SOC_IMX28
 349 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
 350 {
 351         __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
 352 }
 353 #else
 354 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
 355 {
 356 }
 357 #endif
 358
 359 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
 360                 void __iomem *addr)
 361 {
 362         if (ci->imx28_write_fix)
 363                 imx28_ci_writel(val, addr);
 364         else
 365                 iowrite32(val, addr);
 366 }
 367
 368 /**
 369  * hw_write: writes to a hw register
 370  * @ci: the controller
 371  * @reg:  register index
 372  * @mask: bitfield mask
 373  * @data: new value
 374  */
 375 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
 376                             u32 mask, u32 data)
 377 {
 378         if (~mask)
 379                 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
 380                         | (data & mask);
 381
 382         __hw_write(ci, data, ci->hw_bank.regmap[reg]);
 383 }
 384
 385 /**
 386  * hw_test_and_clear: tests & clears a hw register
 387  * @ci: the controller
 388  * @reg:  register index
 389  * @mask: bitfield mask
 390  *
 391  * This function returns register contents
 392  */
 393 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
 394                                     u32 mask)
 395 {
 396         u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
 397
 398         __hw_write(ci, val, ci->hw_bank.regmap[reg]);
 399         return val;
 400 }
 401
 402 /**
 403  * hw_test_and_write: tests & writes a hw register
 404  * @ci: the controller
 405  * @reg:  register index
 406  * @mask: bitfield mask
 407  * @data: new value
 408  *
 409  * This function returns register contents
 410  */
 411 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
 412                                     u32 mask, u32 data)
 413 {
 414         u32 val = hw_read(ci, reg, ~0);
 415
 416         hw_write(ci, reg, mask, data);
 417         return (val & mask) >> __ffs(mask);
 418 }
 419
 420 /**
 421  * ci_otg_is_fsm_mode: runtime check if otg controller
 422  * is in otg fsm mode.
 423  *
 424  * @ci: chipidea device
 425  */
 426 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
 427 {
 428 #ifdef CONFIG_USB_OTG_FSM
 429         struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
 430
 431         return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
 432                 ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
 433                 otg_caps->hnp_support || otg_caps->adp_support);
 434 #else
 435         return false;
 436 #endif
 437 }
 438
 439 int ci_ulpi_init(struct ci_hdrc *ci);
 440 void ci_ulpi_exit(struct ci_hdrc *ci);
 441 int ci_ulpi_resume(struct ci_hdrc *ci);
 442
 443 u32 hw_read_intr_enable(struct ci_hdrc *ci);
 444
 445 u32 hw_read_intr_status(struct ci_hdrc *ci);
 446
 447 int hw_device_reset(struct ci_hdrc *ci);
 448
 449 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
 450
 451 u8 hw_port_test_get(struct ci_hdrc *ci);
 452
 453 void hw_phymode_configure(struct ci_hdrc *ci);
 454
 455 void ci_platform_configure(struct ci_hdrc *ci);
 456
 457 void dbg_create_files(struct ci_hdrc *ci);
 458
 459 void dbg_remove_files(struct ci_hdrc *ci);
 460 #endif  /* __DRIVERS_USB_CHIPIDEA_CI_H */