arch/s390/include/asm/processor.h

   1 /*
   2  *  S390 version
   3  *    Copyright IBM Corp. 1999
   4  *    Author(s): Hartmut Penner (hp@de.ibm.com),
   5  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   6  *
   7  *  Derived from "include/asm-i386/processor.h"
   8  *    Copyright (C) 1994, Linus Torvalds
   9  */
  10
  11 #ifndef __ASM_S390_PROCESSOR_H
  12 #define __ASM_S390_PROCESSOR_H
  13
  14 #define CIF_MCCK_PENDING        0       /* machine check handling is pending */
  15 #define CIF_ASCE                1       /* user asce needs fixup / uaccess */
  16 #define CIF_NOHZ_DELAY          2       /* delay HZ disable for a tick */
  17
  18 #define _CIF_MCCK_PENDING       (1<<CIF_MCCK_PENDING)
  19 #define _CIF_ASCE               (1<<CIF_ASCE)
  20 #define _CIF_NOHZ_DELAY         (1<<CIF_NOHZ_DELAY)
  21
  22
  23 #ifndef __ASSEMBLY__
  24
  25 #include <linux/linkage.h>
  26 #include <linux/irqflags.h>
  27 #include <asm/cpu.h>
  28 #include <asm/page.h>
  29 #include <asm/ptrace.h>
  30 #include <asm/setup.h>
  31 #include <asm/runtime_instr.h>
  32
  33 static inline void set_cpu_flag(int flag)
  34 {
  35         S390_lowcore.cpu_flags |= (1U << flag);
  36 }
  37
  38 static inline void clear_cpu_flag(int flag)
  39 {
  40         S390_lowcore.cpu_flags &= ~(1U << flag);
  41 }
  42
  43 static inline int test_cpu_flag(int flag)
  44 {
  45         return !!(S390_lowcore.cpu_flags & (1U << flag));
  46 }
  47
  48 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
  49
  50 /*
  51  * Default implementation of macro that returns current
  52  * instruction pointer ("program counter").
  53  */
  54 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
  55
  56 static inline void get_cpu_id(struct cpuid *ptr)
  57 {
  58         asm volatile("stidp %0" : "=Q" (*ptr));
  59 }
  60
  61 extern void s390_adjust_jiffies(void);
  62 extern const struct seq_operations cpuinfo_op;
  63 extern int sysctl_ieee_emulation_warnings;
  64 extern void execve_tail(void);
  65
  66 /*
  67  * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
  68  */
  69 #ifndef CONFIG_64BIT
  70
  71 #define TASK_SIZE               (1UL << 31)
  72 #define TASK_MAX_SIZE           (1UL << 31)
  73 #define TASK_UNMAPPED_BASE      (1UL << 30)
  74
  75 #else /* CONFIG_64BIT */
  76
  77 #define TASK_SIZE_OF(tsk)       ((tsk)->mm->context.asce_limit)
  78 #define TASK_UNMAPPED_BASE      (test_thread_flag(TIF_31BIT) ? \
  79                                         (1UL << 30) : (1UL << 41))
  80 #define TASK_SIZE               TASK_SIZE_OF(current)
  81 #define TASK_MAX_SIZE           (1UL << 53)
  82
  83 #endif /* CONFIG_64BIT */
  84
  85 #ifndef CONFIG_64BIT
  86 #define STACK_TOP               (1UL << 31)
  87 #define STACK_TOP_MAX           (1UL << 31)
  88 #else /* CONFIG_64BIT */
  89 #define STACK_TOP               (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
  90 #define STACK_TOP_MAX           (1UL << 42)
  91 #endif /* CONFIG_64BIT */
  92
  93 #define HAVE_ARCH_PICK_MMAP_LAYOUT
  94
  95 typedef struct {
  96         __u32 ar4;
  97 } mm_segment_t;
  98
  99 /*
 100  * Thread structure
 101  */
 102 struct thread_struct {
 103         s390_fp_regs fp_regs;
 104         unsigned int  acrs[NUM_ACRS];
 105         unsigned long ksp;              /* kernel stack pointer             */
 106         mm_segment_t mm_segment;
 107         unsigned long gmap_addr;        /* address of last gmap fault. */
 108         unsigned int gmap_pfault;       /* signal of a pending guest pfault */
 109         struct per_regs per_user;       /* User specified PER registers */
 110         struct per_event per_event;     /* Cause of the last PER trap */
 111         unsigned long per_flags;        /* Flags to control debug behavior */
 112         /* pfault_wait is used to block the process on a pfault event */
 113         unsigned long pfault_wait;
 114         struct list_head list;
 115         /* cpu runtime instrumentation */
 116         struct runtime_instr_cb *ri_cb;
 117         int ri_signum;
 118 #ifdef CONFIG_64BIT
 119         unsigned char trap_tdb[256];    /* Transaction abort diagnose block */
 120         __vector128 *vxrs;              /* Vector register save area */
 121 #endif
 122 };
 123
 124 /* Flag to disable transactions. */
 125 #define PER_FLAG_NO_TE                  1UL
 126 /* Flag to enable random transaction aborts. */
 127 #define PER_FLAG_TE_ABORT_RAND          2UL
 128 /* Flag to specify random transaction abort mode:
 129  * - abort each transaction at a random instruction before TEND if set.
 130  * - abort random transactions at a random instruction if cleared.
 131  */
 132 #define PER_FLAG_TE_ABORT_RAND_TEND     4UL
 133
 134 typedef struct thread_struct thread_struct;
 135
 136 /*
 137  * Stack layout of a C stack frame.
 138  */
 139 #ifndef __PACK_STACK
 140 struct stack_frame {
 141         unsigned long back_chain;
 142         unsigned long empty1[5];
 143         unsigned long gprs[10];
 144         unsigned int  empty2[8];
 145 };
 146 #else
 147 struct stack_frame {
 148         unsigned long empty1[5];
 149         unsigned int  empty2[8];
 150         unsigned long gprs[10];
 151         unsigned long back_chain;
 152 };
 153 #endif
 154
 155 #define ARCH_MIN_TASKALIGN      8
 156
 157 #define INIT_THREAD {                                                   \
 158         .ksp = sizeof(init_stack) + (unsigned long) &init_stack,        \
 159 }
 160
 161 /*
 162  * Do necessary setup to start up a new thread.
 163  */
 164 #define start_thread(regs, new_psw, new_stackp) do {                    \
 165         regs->psw.mask  = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;    \
 166         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 167         regs->gprs[15]  = new_stackp;                                   \
 168         execve_tail();                                                  \
 169 } while (0)
 170
 171 #define start_thread31(regs, new_psw, new_stackp) do {                  \
 172         regs->psw.mask  = PSW_USER_BITS | PSW_MASK_BA;                  \
 173         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 174         regs->gprs[15]  = new_stackp;                                   \
 175         crst_table_downgrade(current->mm, 1UL << 31);                   \
 176         execve_tail();                                                  \
 177 } while (0)
 178
 179 /* Forward declaration, a strange C thing */
 180 struct task_struct;
 181 struct mm_struct;
 182 struct seq_file;
 183
 184 #ifdef CONFIG_64BIT
 185 extern void show_cacheinfo(struct seq_file *m);
 186 #else
 187 static inline void show_cacheinfo(struct seq_file *m) { }
 188 #endif
 189
 190 /* Free all resources held by a thread. */
 191 extern void release_thread(struct task_struct *);
 192
 193 /*
 194  * Return saved PC of a blocked thread.
 195  */
 196 extern unsigned long thread_saved_pc(struct task_struct *t);
 197
 198 unsigned long get_wchan(struct task_struct *p);
 199 #define task_pt_regs(tsk) ((struct pt_regs *) \
 200         (task_stack_page(tsk) + THREAD_SIZE) - 1)
 201 #define KSTK_EIP(tsk)   (task_pt_regs(tsk)->psw.addr)
 202 #define KSTK_ESP(tsk)   (task_pt_regs(tsk)->gprs[15])
 203
 204 /* Has task runtime instrumentation enabled ? */
 205 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
 206
 207 static inline unsigned short stap(void)
 208 {
 209         unsigned short cpu_address;
 210
 211         asm volatile("stap %0" : "=m" (cpu_address));
 212         return cpu_address;
 213 }
 214
 215 /*
 216  * Give up the time slice of the virtual PU.
 217  */
 218 static inline void cpu_relax(void)
 219 {
 220         if (MACHINE_HAS_DIAG44)
 221                 asm volatile("diag 0,0,68");
 222         barrier();
 223 }
 224
 225 #define cpu_relax_lowlatency()  barrier()
 226
 227 static inline void psw_set_key(unsigned int key)
 228 {
 229         asm volatile("spka 0(%0)" : : "d" (key));
 230 }
 231
 232 /*
 233  * Set PSW to specified value.
 234  */
 235 static inline void __load_psw(psw_t psw)
 236 {
 237 #ifndef CONFIG_64BIT
 238         asm volatile("lpsw  %0" : : "Q" (psw) : "cc");
 239 #else
 240         asm volatile("lpswe %0" : : "Q" (psw) : "cc");
 241 #endif
 242 }
 243
 244 /*
 245  * Set PSW mask to specified value, while leaving the
 246  * PSW addr pointing to the next instruction.
 247  */
 248 static inline void __load_psw_mask (unsigned long mask)
 249 {
 250         unsigned long addr;
 251         psw_t psw;
 252
 253         psw.mask = mask;
 254
 255 #ifndef CONFIG_64BIT
 256         asm volatile(
 257                 "       basr    %0,0\n"
 258                 "0:     ahi     %0,1f-0b\n"
 259                 "       st      %0,%O1+4(%R1)\n"
 260                 "       lpsw    %1\n"
 261                 "1:"
 262                 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 263 #else /* CONFIG_64BIT */
 264         asm volatile(
 265                 "       larl    %0,1f\n"
 266                 "       stg     %0,%O1+8(%R1)\n"
 267                 "       lpswe   %1\n"
 268                 "1:"
 269                 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 270 #endif /* CONFIG_64BIT */
 271 }
 272
 273 /*
 274  * Rewind PSW instruction address by specified number of bytes.
 275  */
 276 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
 277 {
 278 #ifndef CONFIG_64BIT
 279         if (psw.addr & PSW_ADDR_AMODE)
 280                 /* 31 bit mode */
 281                 return (psw.addr - ilc) | PSW_ADDR_AMODE;
 282         /* 24 bit mode */
 283         return (psw.addr - ilc) & ((1UL << 24) - 1);
 284 #else
 285         unsigned long mask;
 286
 287         mask = (psw.mask & PSW_MASK_EA) ? -1UL :
 288                (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
 289                                           (1UL << 24) - 1;
 290         return (psw.addr - ilc) & mask;
 291 #endif
 292 }
 293
 294 /*
 295  * Function to stop a processor until the next interrupt occurs
 296  */
 297 void enabled_wait(void);
 298
 299 /*
 300  * Function to drop a processor into disabled wait state
 301  */
 302 static inline void __noreturn disabled_wait(unsigned long code)
 303 {
 304         unsigned long ctl_buf;
 305         psw_t dw_psw;
 306
 307         dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
 308         dw_psw.addr = code;
 309         /*
 310          * Store status and then load disabled wait psw,
 311          * the processor is dead afterwards
 312          */
 313 #ifndef CONFIG_64BIT
 314         asm volatile(
 315                 "       stctl   0,0,0(%2)\n"
 316                 "       ni      0(%2),0xef\n"   /* switch off protection */
 317                 "       lctl    0,0,0(%2)\n"
 318                 "       stpt    0xd8\n"         /* store timer */
 319                 "       stckc   0xe0\n"         /* store clock comparator */
 320                 "       stpx    0x108\n"        /* store prefix register */
 321                 "       stam    0,15,0x120\n"   /* store access registers */
 322                 "       std     0,0x160\n"      /* store f0 */
 323                 "       std     2,0x168\n"      /* store f2 */
 324                 "       std     4,0x170\n"      /* store f4 */
 325                 "       std     6,0x178\n"      /* store f6 */
 326                 "       stm     0,15,0x180\n"   /* store general registers */
 327                 "       stctl   0,15,0x1c0\n"   /* store control registers */
 328                 "       oi      0x1c0,0x10\n"   /* fake protection bit */
 329                 "       lpsw    0(%1)"
 330                 : "=m" (ctl_buf)
 331                 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
 332 #else /* CONFIG_64BIT */
 333         asm volatile(
 334                 "       stctg   0,0,0(%2)\n"
 335                 "       ni      4(%2),0xef\n"   /* switch off protection */
 336                 "       lctlg   0,0,0(%2)\n"
 337                 "       lghi    1,0x1000\n"
 338                 "       stpt    0x328(1)\n"     /* store timer */
 339                 "       stckc   0x330(1)\n"     /* store clock comparator */
 340                 "       stpx    0x318(1)\n"     /* store prefix register */
 341                 "       stam    0,15,0x340(1)\n"/* store access registers */
 342                 "       stfpc   0x31c(1)\n"     /* store fpu control */
 343                 "       std     0,0x200(1)\n"   /* store f0 */
 344                 "       std     1,0x208(1)\n"   /* store f1 */
 345                 "       std     2,0x210(1)\n"   /* store f2 */
 346                 "       std     3,0x218(1)\n"   /* store f3 */
 347                 "       std     4,0x220(1)\n"   /* store f4 */
 348                 "       std     5,0x228(1)\n"   /* store f5 */
 349                 "       std     6,0x230(1)\n"   /* store f6 */
 350                 "       std     7,0x238(1)\n"   /* store f7 */
 351                 "       std     8,0x240(1)\n"   /* store f8 */
 352                 "       std     9,0x248(1)\n"   /* store f9 */
 353                 "       std     10,0x250(1)\n"  /* store f10 */
 354                 "       std     11,0x258(1)\n"  /* store f11 */
 355                 "       std     12,0x260(1)\n"  /* store f12 */
 356                 "       std     13,0x268(1)\n"  /* store f13 */
 357                 "       std     14,0x270(1)\n"  /* store f14 */
 358                 "       std     15,0x278(1)\n"  /* store f15 */
 359                 "       stmg    0,15,0x280(1)\n"/* store general registers */
 360                 "       stctg   0,15,0x380(1)\n"/* store control registers */
 361                 "       oi      0x384(1),0x10\n"/* fake protection bit */
 362                 "       lpswe   0(%1)"
 363                 : "=m" (ctl_buf)
 364                 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
 365 #endif /* CONFIG_64BIT */
 366         while (1);
 367 }
 368
 369 /*
 370  * Use to set psw mask except for the first byte which
 371  * won't be changed by this function.
 372  */
 373 static inline void
 374 __set_psw_mask(unsigned long mask)
 375 {
 376         __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
 377 }
 378
 379 #define local_mcck_enable() \
 380         __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK)
 381 #define local_mcck_disable() \
 382         __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT)
 383
 384 /*
 385  * Basic Machine Check/Program Check Handler.
 386  */
 387
 388 extern void s390_base_mcck_handler(void);
 389 extern void s390_base_pgm_handler(void);
 390 extern void s390_base_ext_handler(void);
 391
 392 extern void (*s390_base_mcck_handler_fn)(void);
 393 extern void (*s390_base_pgm_handler_fn)(void);
 394 extern void (*s390_base_ext_handler_fn)(void);
 395
 396 #define ARCH_LOW_ADDRESS_LIMIT  0x7fffffffUL
 397
 398 extern int memcpy_real(void *, void *, size_t);
 399 extern void memcpy_absolute(void *, void *, size_t);
 400
 401 #define mem_assign_absolute(dest, val) {                        \
 402         __typeof__(dest) __tmp = (val);                         \
 403                                                                 \
 404         BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));             \
 405         memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));        \
 406 }
 407
 408 /*
 409  * Helper macro for exception table entries
 410  */
 411 #define EX_TABLE(_fault, _target)       \
 412         ".section __ex_table,\"a\"\n"   \
 413         ".align 4\n"                    \
 414         ".long  (" #_fault ") - .\n"    \
 415         ".long  (" #_target ") - .\n"   \
 416         ".previous\n"
 417
 418 #else /* __ASSEMBLY__ */
 419
 420 #define EX_TABLE(_fault, _target)       \
 421         .section __ex_table,"a" ;       \
 422         .align  4 ;                     \
 423         .long   (_fault) - . ;          \
 424         .long   (_target) - . ;         \
 425         .previous
 426
 427 #endif /* __ASSEMBLY__ */
 428
 429 #endif /* __ASM_S390_PROCESSOR_H */