Merge branch 'for-3.18-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj...
[linux/fpc-iii.git] / arch / unicore32 / include / mach / regs-spi.h
blobde16895e2dc0da3b66f3ef474fa9ed678c0b8e9c
1 /*
2 * PKUnity Serial Peripheral Interface (SPI) Registers
3 */
4 /*
5 * Control reg. 0 SPI_CR0
6 */
7 #define SPI_CR0 (PKUNITY_SPI_BASE + 0x0000)
8 /*
9 * Control reg. 1 SPI_CR1
11 #define SPI_CR1 (PKUNITY_SPI_BASE + 0x0004)
13 * Enable reg SPI_SSIENR
15 #define SPI_SSIENR (PKUNITY_SPI_BASE + 0x0008)
17 * Status reg SPI_SR
19 #define SPI_SR (PKUNITY_SPI_BASE + 0x0028)
21 * Interrupt Mask reg SPI_IMR
23 #define SPI_IMR (PKUNITY_SPI_BASE + 0x002C)
25 * Interrupt Status reg SPI_ISR
27 #define SPI_ISR (PKUNITY_SPI_BASE + 0x0030)
30 * Enable SPI Controller SPI_SSIENR_EN
32 #define SPI_SSIENR_EN FIELD(1, 1, 0)
35 * SPI Busy SPI_SR_BUSY
37 #define SPI_SR_BUSY FIELD(1, 1, 0)
39 * Transmit FIFO Not Full SPI_SR_TFNF
41 #define SPI_SR_TFNF FIELD(1, 1, 1)
43 * Transmit FIFO Empty SPI_SR_TFE
45 #define SPI_SR_TFE FIELD(1, 1, 2)
47 * Receive FIFO Not Empty SPI_SR_RFNE
49 #define SPI_SR_RFNE FIELD(1, 1, 3)
51 * Receive FIFO Full SPI_SR_RFF
53 #define SPI_SR_RFF FIELD(1, 1, 4)
56 * Trans. FIFO Empty Interrupt Status SPI_ISR_TXEIS
58 #define SPI_ISR_TXEIS FIELD(1, 1, 0)
60 * Trans. FIFO Overflow Interrupt Status SPI_ISR_TXOIS
62 #define SPI_ISR_TXOIS FIELD(1, 1, 1)
64 * Receiv. FIFO Underflow Interrupt Status SPI_ISR_RXUIS
66 #define SPI_ISR_RXUIS FIELD(1, 1, 2)
68 * Receiv. FIFO Overflow Interrupt Status SPI_ISR_RXOIS
70 #define SPI_ISR_RXOIS FIELD(1, 1, 3)
72 * Receiv. FIFO Full Interrupt Status SPI_ISR_RXFIS
74 #define SPI_ISR_RXFIS FIELD(1, 1, 4)
75 #define SPI_ISR_MSTIS FIELD(1, 1, 5)
78 * Trans. FIFO Empty Interrupt Mask SPI_IMR_TXEIM
80 #define SPI_IMR_TXEIM FIELD(1, 1, 0)
82 * Trans. FIFO Overflow Interrupt Mask SPI_IMR_TXOIM
84 #define SPI_IMR_TXOIM FIELD(1, 1, 1)
86 * Receiv. FIFO Underflow Interrupt Mask SPI_IMR_RXUIM
88 #define SPI_IMR_RXUIM FIELD(1, 1, 2)
90 * Receiv. FIFO Overflow Interrupt Mask SPI_IMR_RXOIM
92 #define SPI_IMR_RXOIM FIELD(1, 1, 3)
94 * Receiv. FIFO Full Interrupt Mask SPI_IMR_RXFIM
96 #define SPI_IMR_RXFIM FIELD(1, 1, 4)
97 #define SPI_IMR_MSTIM FIELD(1, 1, 5)