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Staging: netwave: delete the driver
[linux/fpc-iii.git] / drivers / net / arm / ep93xx_eth.c
blob6995169d285ab10b71ede945c68451d6dc972f21
1 /*
2 * EP93xx ethernet network device driver
3 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
4 * Dedicated to Marija Kulikova.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
13
14 #include <linux/dma-mapping.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/netdevice.h>
18 #include <linux/mii.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/init.h>
22 #include <linux/moduleparam.h>
23 #include <linux/platform_device.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/slab.h>
27
28 #include <mach/hardware.h>
29
30 #define DRV_MODULE_NAME "ep93xx-eth"
31 #define DRV_MODULE_VERSION "0.1"
32
33 #define RX_QUEUE_ENTRIES 64
34 #define TX_QUEUE_ENTRIES 8
35
36 #define MAX_PKT_SIZE 2044
37 #define PKT_BUF_SIZE 2048
38
39 #define REG_RXCTL 0x0000
40 #define REG_RXCTL_DEFAULT 0x00073800
41 #define REG_TXCTL 0x0004
42 #define REG_TXCTL_ENABLE 0x00000001
43 #define REG_MIICMD 0x0010
44 #define REG_MIICMD_READ 0x00008000
45 #define REG_MIICMD_WRITE 0x00004000
46 #define REG_MIIDATA 0x0014
47 #define REG_MIISTS 0x0018
48 #define REG_MIISTS_BUSY 0x00000001
49 #define REG_SELFCTL 0x0020
50 #define REG_SELFCTL_RESET 0x00000001
51 #define REG_INTEN 0x0024
52 #define REG_INTEN_TX 0x00000008
53 #define REG_INTEN_RX 0x00000007
54 #define REG_INTSTSP 0x0028
55 #define REG_INTSTS_TX 0x00000008
56 #define REG_INTSTS_RX 0x00000004
57 #define REG_INTSTSC 0x002c
58 #define REG_AFP 0x004c
59 #define REG_INDAD0 0x0050
60 #define REG_INDAD1 0x0051
61 #define REG_INDAD2 0x0052
62 #define REG_INDAD3 0x0053
63 #define REG_INDAD4 0x0054
64 #define REG_INDAD5 0x0055
65 #define REG_GIINTMSK 0x0064
66 #define REG_GIINTMSK_ENABLE 0x00008000
67 #define REG_BMCTL 0x0080
68 #define REG_BMCTL_ENABLE_TX 0x00000100
69 #define REG_BMCTL_ENABLE_RX 0x00000001
70 #define REG_BMSTS 0x0084
71 #define REG_BMSTS_RX_ACTIVE 0x00000008
72 #define REG_RXDQBADD 0x0090
73 #define REG_RXDQBLEN 0x0094
74 #define REG_RXDCURADD 0x0098
75 #define REG_RXDENQ 0x009c
76 #define REG_RXSTSQBADD 0x00a0
77 #define REG_RXSTSQBLEN 0x00a4
78 #define REG_RXSTSQCURADD 0x00a8
79 #define REG_RXSTSENQ 0x00ac
80 #define REG_TXDQBADD 0x00b0
81 #define REG_TXDQBLEN 0x00b4
82 #define REG_TXDQCURADD 0x00b8
83 #define REG_TXDENQ 0x00bc
84 #define REG_TXSTSQBADD 0x00c0
85 #define REG_TXSTSQBLEN 0x00c4
86 #define REG_TXSTSQCURADD 0x00c8
87 #define REG_MAXFRMLEN 0x00e8
88
89 struct ep93xx_rdesc
90 {
91 u32 buf_addr;
92 u32 rdesc1;
93 };
94
95 #define RDESC1_NSOF 0x80000000
96 #define RDESC1_BUFFER_INDEX 0x7fff0000
97 #define RDESC1_BUFFER_LENGTH 0x0000ffff
98
99 struct ep93xx_rstat
100 {
101 u32 rstat0;
102 u32 rstat1;
103 };
104
105 #define RSTAT0_RFP 0x80000000
106 #define RSTAT0_RWE 0x40000000
107 #define RSTAT0_EOF 0x20000000
108 #define RSTAT0_EOB 0x10000000
109 #define RSTAT0_AM 0x00c00000
110 #define RSTAT0_RX_ERR 0x00200000
111 #define RSTAT0_OE 0x00100000
112 #define RSTAT0_FE 0x00080000
113 #define RSTAT0_RUNT 0x00040000
114 #define RSTAT0_EDATA 0x00020000
115 #define RSTAT0_CRCE 0x00010000
116 #define RSTAT0_CRCI 0x00008000
117 #define RSTAT0_HTI 0x00003f00
118 #define RSTAT1_RFP 0x80000000
119 #define RSTAT1_BUFFER_INDEX 0x7fff0000
120 #define RSTAT1_FRAME_LENGTH 0x0000ffff
121
122 struct ep93xx_tdesc
123 {
124 u32 buf_addr;
125 u32 tdesc1;
126 };
127
128 #define TDESC1_EOF 0x80000000
129 #define TDESC1_BUFFER_INDEX 0x7fff0000
130 #define TDESC1_BUFFER_ABORT 0x00008000
131 #define TDESC1_BUFFER_LENGTH 0x00000fff
132
133 struct ep93xx_tstat
134 {
135 u32 tstat0;
136 };
137
138 #define TSTAT0_TXFP 0x80000000
139 #define TSTAT0_TXWE 0x40000000
140 #define TSTAT0_FA 0x20000000
141 #define TSTAT0_LCRS 0x10000000
142 #define TSTAT0_OW 0x04000000
143 #define TSTAT0_TXU 0x02000000
144 #define TSTAT0_ECOLL 0x01000000
145 #define TSTAT0_NCOLL 0x001f0000
146 #define TSTAT0_BUFFER_INDEX 0x00007fff
147
148 struct ep93xx_descs
149 {
150 struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES];
151 struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES];
152 struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES];
153 struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES];
154 };
155
156 struct ep93xx_priv
157 {
158 struct resource *res;
159 void __iomem *base_addr;
160 int irq;
161
162 struct ep93xx_descs *descs;
163 dma_addr_t descs_dma_addr;
164
165 void *rx_buf[RX_QUEUE_ENTRIES];
166 void *tx_buf[TX_QUEUE_ENTRIES];
167
168 spinlock_t rx_lock;
169 unsigned int rx_pointer;
170 unsigned int tx_clean_pointer;
171 unsigned int tx_pointer;
172 spinlock_t tx_pending_lock;
173 unsigned int tx_pending;
174
175 struct net_device *dev;
176 struct napi_struct napi;
177
178 struct net_device_stats stats;
179
180 struct mii_if_info mii;
181 u8 mdc_divisor;
182 };
183
184 #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
185 #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
186 #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
187 #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
188 #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
189 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
190
191 static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
192 {
193 struct ep93xx_priv *ep = netdev_priv(dev);
194 int data;
195 int i;
196
197 wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
198
199 for (i = 0; i < 10; i++) {
200 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
201 break;
202 msleep(1);
203 }
204
205 if (i == 10) {
206 pr_info("mdio read timed out\n");
207 data = 0xffff;
208 } else {
209 data = rdl(ep, REG_MIIDATA);
210 }
211
212 return data;
213 }
214
215 static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
216 {
217 struct ep93xx_priv *ep = netdev_priv(dev);
218 int i;
219
220 wrl(ep, REG_MIIDATA, data);
221 wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
222
223 for (i = 0; i < 10; i++) {
224 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
225 break;
226 msleep(1);
227 }
228
229 if (i == 10)
230 pr_info("mdio write timed out\n");
231 }
232
233 static struct net_device_stats *ep93xx_get_stats(struct net_device *dev)
234 {
235 struct ep93xx_priv *ep = netdev_priv(dev);
236 return &(ep->stats);
237 }
238
239 static int ep93xx_rx(struct net_device *dev, int processed, int budget)
240 {
241 struct ep93xx_priv *ep = netdev_priv(dev);
242
243 while (processed < budget) {
244 int entry;
245 struct ep93xx_rstat *rstat;
246 u32 rstat0;
247 u32 rstat1;
248 int length;
249 struct sk_buff *skb;
250
251 entry = ep->rx_pointer;
252 rstat = ep->descs->rstat + entry;
253
254 rstat0 = rstat->rstat0;
255 rstat1 = rstat->rstat1;
256 if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
257 break;
258
259 rstat->rstat0 = 0;
260 rstat->rstat1 = 0;
261
262 if (!(rstat0 & RSTAT0_EOF))
263 pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1);
264 if (!(rstat0 & RSTAT0_EOB))
265 pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1);
266 if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
267 pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1);
268
269 if (!(rstat0 & RSTAT0_RWE)) {
270 ep->stats.rx_errors++;
271 if (rstat0 & RSTAT0_OE)
272 ep->stats.rx_fifo_errors++;
273 if (rstat0 & RSTAT0_FE)
274 ep->stats.rx_frame_errors++;
275 if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
276 ep->stats.rx_length_errors++;
277 if (rstat0 & RSTAT0_CRCE)
278 ep->stats.rx_crc_errors++;
279 goto err;
280 }
281
282 length = rstat1 & RSTAT1_FRAME_LENGTH;
283 if (length > MAX_PKT_SIZE) {
284 pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1);
285 goto err;
286 }
287
288 /* Strip FCS. */
289 if (rstat0 & RSTAT0_CRCI)
290 length -= 4;
291
292 skb = dev_alloc_skb(length + 2);
293 if (likely(skb != NULL)) {
294 skb_reserve(skb, 2);
295 dma_sync_single_for_cpu(NULL, ep->descs->rdesc[entry].buf_addr,
296 length, DMA_FROM_DEVICE);
297 skb_copy_to_linear_data(skb, ep->rx_buf[entry], length);
298 skb_put(skb, length);
299 skb->protocol = eth_type_trans(skb, dev);
300
301 netif_receive_skb(skb);
302
303 ep->stats.rx_packets++;
304 ep->stats.rx_bytes += length;
305 } else {
306 ep->stats.rx_dropped++;
307 }
308
309 err:
310 ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
311 processed++;
312 }
313
314 if (processed) {
315 wrw(ep, REG_RXDENQ, processed);
316 wrw(ep, REG_RXSTSENQ, processed);
317 }
318
319 return processed;
320 }
321
322 static int ep93xx_have_more_rx(struct ep93xx_priv *ep)
323 {
324 struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer;
325 return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP));
326 }
327
328 static int ep93xx_poll(struct napi_struct *napi, int budget)
329 {
330 struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi);
331 struct net_device *dev = ep->dev;
332 int rx = 0;
333
334 poll_some_more:
335 rx = ep93xx_rx(dev, rx, budget);
336 if (rx < budget) {
337 int more = 0;
338
339 spin_lock_irq(&ep->rx_lock);
340 __napi_complete(napi);
341 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
342 if (ep93xx_have_more_rx(ep)) {
343 wrl(ep, REG_INTEN, REG_INTEN_TX);
344 wrl(ep, REG_INTSTSP, REG_INTSTS_RX);
345 more = 1;
346 }
347 spin_unlock_irq(&ep->rx_lock);
348
349 if (more && napi_reschedule(napi))
350 goto poll_some_more;
351 }
352
353 return rx;
354 }
355
356 static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
357 {
358 struct ep93xx_priv *ep = netdev_priv(dev);
359 int entry;
360
361 if (unlikely(skb->len > MAX_PKT_SIZE)) {
362 ep->stats.tx_dropped++;
363 dev_kfree_skb(skb);
364 return NETDEV_TX_OK;
365 }
366
367 entry = ep->tx_pointer;
368 ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
369
370 ep->descs->tdesc[entry].tdesc1 =
371 TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
372 skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
373 dma_sync_single_for_cpu(NULL, ep->descs->tdesc[entry].buf_addr,
374 skb->len, DMA_TO_DEVICE);
375 dev_kfree_skb(skb);
376
377 dev->trans_start = jiffies;
378
379 spin_lock_irq(&ep->tx_pending_lock);
380 ep->tx_pending++;
381 if (ep->tx_pending == TX_QUEUE_ENTRIES)
382 netif_stop_queue(dev);
383 spin_unlock_irq(&ep->tx_pending_lock);
384
385 wrl(ep, REG_TXDENQ, 1);
386
387 return NETDEV_TX_OK;
388 }
389
390 static void ep93xx_tx_complete(struct net_device *dev)
391 {
392 struct ep93xx_priv *ep = netdev_priv(dev);
393 int wake;
394
395 wake = 0;
396
397 spin_lock(&ep->tx_pending_lock);
398 while (1) {
399 int entry;
400 struct ep93xx_tstat *tstat;
401 u32 tstat0;
402
403 entry = ep->tx_clean_pointer;
404 tstat = ep->descs->tstat + entry;
405
406 tstat0 = tstat->tstat0;
407 if (!(tstat0 & TSTAT0_TXFP))
408 break;
409
410 tstat->tstat0 = 0;
411
412 if (tstat0 & TSTAT0_FA)
413 pr_crit("frame aborted %.8x\n", tstat0);
414 if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
415 pr_crit("entry mismatch %.8x\n", tstat0);
416
417 if (tstat0 & TSTAT0_TXWE) {
418 int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
419
420 ep->stats.tx_packets++;
421 ep->stats.tx_bytes += length;
422 } else {
423 ep->stats.tx_errors++;
424 }
425
426 if (tstat0 & TSTAT0_OW)
427 ep->stats.tx_window_errors++;
428 if (tstat0 & TSTAT0_TXU)
429 ep->stats.tx_fifo_errors++;
430 ep->stats.collisions += (tstat0 >> 16) & 0x1f;
431
432 ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
433 if (ep->tx_pending == TX_QUEUE_ENTRIES)
434 wake = 1;
435 ep->tx_pending--;
436 }
437 spin_unlock(&ep->tx_pending_lock);
438
439 if (wake)
440 netif_wake_queue(dev);
441 }
442
443 static irqreturn_t ep93xx_irq(int irq, void *dev_id)
444 {
445 struct net_device *dev = dev_id;
446 struct ep93xx_priv *ep = netdev_priv(dev);
447 u32 status;
448
449 status = rdl(ep, REG_INTSTSC);
450 if (status == 0)
451 return IRQ_NONE;
452
453 if (status & REG_INTSTS_RX) {
454 spin_lock(&ep->rx_lock);
455 if (likely(napi_schedule_prep(&ep->napi))) {
456 wrl(ep, REG_INTEN, REG_INTEN_TX);
457 __napi_schedule(&ep->napi);
458 }
459 spin_unlock(&ep->rx_lock);
460 }
461
462 if (status & REG_INTSTS_TX)
463 ep93xx_tx_complete(dev);
464
465 return IRQ_HANDLED;
466 }
467
468 static void ep93xx_free_buffers(struct ep93xx_priv *ep)
469 {
470 int i;
471
472 for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) {
473 dma_addr_t d;
474
475 d = ep->descs->rdesc[i].buf_addr;
476 if (d)
477 dma_unmap_single(NULL, d, PAGE_SIZE, DMA_FROM_DEVICE);
478
479 if (ep->rx_buf[i] != NULL)
480 free_page((unsigned long)ep->rx_buf[i]);
481 }
482
483 for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) {
484 dma_addr_t d;
485
486 d = ep->descs->tdesc[i].buf_addr;
487 if (d)
488 dma_unmap_single(NULL, d, PAGE_SIZE, DMA_TO_DEVICE);
489
490 if (ep->tx_buf[i] != NULL)
491 free_page((unsigned long)ep->tx_buf[i]);
492 }
493
494 dma_free_coherent(NULL, sizeof(struct ep93xx_descs), ep->descs,
495 ep->descs_dma_addr);
496 }
497
498 /*
499 * The hardware enforces a sub-2K maximum packet size, so we put
500 * two buffers on every hardware page.
501 */
502 static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
503 {
504 int i;
505
506 ep->descs = dma_alloc_coherent(NULL, sizeof(struct ep93xx_descs),
507 &ep->descs_dma_addr, GFP_KERNEL | GFP_DMA);
508 if (ep->descs == NULL)
509 return 1;
510
511 for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) {
512 void *page;
513 dma_addr_t d;
514
515 page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
516 if (page == NULL)
517 goto err;
518
519 d = dma_map_single(NULL, page, PAGE_SIZE, DMA_FROM_DEVICE);
520 if (dma_mapping_error(NULL, d)) {
521 free_page((unsigned long)page);
522 goto err;
523 }
524
525 ep->rx_buf[i] = page;
526 ep->descs->rdesc[i].buf_addr = d;
527 ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
528
529 ep->rx_buf[i + 1] = page + PKT_BUF_SIZE;
530 ep->descs->rdesc[i + 1].buf_addr = d + PKT_BUF_SIZE;
531 ep->descs->rdesc[i + 1].rdesc1 = ((i + 1) << 16) | PKT_BUF_SIZE;
532 }
533
534 for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) {
535 void *page;
536 dma_addr_t d;
537
538 page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
539 if (page == NULL)
540 goto err;
541
542 d = dma_map_single(NULL, page, PAGE_SIZE, DMA_TO_DEVICE);
543 if (dma_mapping_error(NULL, d)) {
544 free_page((unsigned long)page);
545 goto err;
546 }
547
548 ep->tx_buf[i] = page;
549 ep->descs->tdesc[i].buf_addr = d;
550
551 ep->tx_buf[i + 1] = page + PKT_BUF_SIZE;
552 ep->descs->tdesc[i + 1].buf_addr = d + PKT_BUF_SIZE;
553 }
554
555 return 0;
556
557 err:
558 ep93xx_free_buffers(ep);
559 return 1;
560 }
561
562 static int ep93xx_start_hw(struct net_device *dev)
563 {
564 struct ep93xx_priv *ep = netdev_priv(dev);
565 unsigned long addr;
566 int i;
567
568 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
569 for (i = 0; i < 10; i++) {
570 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
571 break;
572 msleep(1);
573 }
574
575 if (i == 10) {
576 pr_crit("hw failed to reset\n");
577 return 1;
578 }
579
580 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
581
582 /* Does the PHY support preamble suppress? */
583 if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
584 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
585
586 /* Receive descriptor ring. */
587 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
588 wrl(ep, REG_RXDQBADD, addr);
589 wrl(ep, REG_RXDCURADD, addr);
590 wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
591
592 /* Receive status ring. */
593 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
594 wrl(ep, REG_RXSTSQBADD, addr);
595 wrl(ep, REG_RXSTSQCURADD, addr);
596 wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
597
598 /* Transmit descriptor ring. */
599 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
600 wrl(ep, REG_TXDQBADD, addr);
601 wrl(ep, REG_TXDQCURADD, addr);
602 wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
603
604 /* Transmit status ring. */
605 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
606 wrl(ep, REG_TXSTSQBADD, addr);
607 wrl(ep, REG_TXSTSQCURADD, addr);
608 wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
609
610 wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
611 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
612 wrl(ep, REG_GIINTMSK, 0);
613
614 for (i = 0; i < 10; i++) {
615 if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
616 break;
617 msleep(1);
618 }
619
620 if (i == 10) {
621 pr_crit("hw failed to start\n");
622 return 1;
623 }
624
625 wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
626 wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
627
628 wrb(ep, REG_INDAD0, dev->dev_addr[0]);
629 wrb(ep, REG_INDAD1, dev->dev_addr[1]);
630 wrb(ep, REG_INDAD2, dev->dev_addr[2]);
631 wrb(ep, REG_INDAD3, dev->dev_addr[3]);
632 wrb(ep, REG_INDAD4, dev->dev_addr[4]);
633 wrb(ep, REG_INDAD5, dev->dev_addr[5]);
634 wrl(ep, REG_AFP, 0);
635
636 wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
637
638 wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
639 wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
640
641 return 0;
642 }
643
644 static void ep93xx_stop_hw(struct net_device *dev)
645 {
646 struct ep93xx_priv *ep = netdev_priv(dev);
647 int i;
648
649 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
650 for (i = 0; i < 10; i++) {
651 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
652 break;
653 msleep(1);
654 }
655
656 if (i == 10)
657 pr_crit("hw failed to reset\n");
658 }
659
660 static int ep93xx_open(struct net_device *dev)
661 {
662 struct ep93xx_priv *ep = netdev_priv(dev);
663 int err;
664
665 if (ep93xx_alloc_buffers(ep))
666 return -ENOMEM;
667
668 napi_enable(&ep->napi);
669
670 if (ep93xx_start_hw(dev)) {
671 napi_disable(&ep->napi);
672 ep93xx_free_buffers(ep);
673 return -EIO;
674 }
675
676 spin_lock_init(&ep->rx_lock);
677 ep->rx_pointer = 0;
678 ep->tx_clean_pointer = 0;
679 ep->tx_pointer = 0;
680 spin_lock_init(&ep->tx_pending_lock);
681 ep->tx_pending = 0;
682
683 err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
684 if (err) {
685 napi_disable(&ep->napi);
686 ep93xx_stop_hw(dev);
687 ep93xx_free_buffers(ep);
688 return err;
689 }
690
691 wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
692
693 netif_start_queue(dev);
694
695 return 0;
696 }
697
698 static int ep93xx_close(struct net_device *dev)
699 {
700 struct ep93xx_priv *ep = netdev_priv(dev);
701
702 napi_disable(&ep->napi);
703 netif_stop_queue(dev);
704
705 wrl(ep, REG_GIINTMSK, 0);
706 free_irq(ep->irq, dev);
707 ep93xx_stop_hw(dev);
708 ep93xx_free_buffers(ep);
709
710 return 0;
711 }
712
713 static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
714 {
715 struct ep93xx_priv *ep = netdev_priv(dev);
716 struct mii_ioctl_data *data = if_mii(ifr);
717
718 return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
719 }
720
721 static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
722 {
723 strcpy(info->driver, DRV_MODULE_NAME);
724 strcpy(info->version, DRV_MODULE_VERSION);
725 }
726
727 static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
728 {
729 struct ep93xx_priv *ep = netdev_priv(dev);
730 return mii_ethtool_gset(&ep->mii, cmd);
731 }
732
733 static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
734 {
735 struct ep93xx_priv *ep = netdev_priv(dev);
736 return mii_ethtool_sset(&ep->mii, cmd);
737 }
738
739 static int ep93xx_nway_reset(struct net_device *dev)
740 {
741 struct ep93xx_priv *ep = netdev_priv(dev);
742 return mii_nway_restart(&ep->mii);
743 }
744
745 static u32 ep93xx_get_link(struct net_device *dev)
746 {
747 struct ep93xx_priv *ep = netdev_priv(dev);
748 return mii_link_ok(&ep->mii);
749 }
750
751 static const struct ethtool_ops ep93xx_ethtool_ops = {
752 .get_drvinfo = ep93xx_get_drvinfo,
753 .get_settings = ep93xx_get_settings,
754 .set_settings = ep93xx_set_settings,
755 .nway_reset = ep93xx_nway_reset,
756 .get_link = ep93xx_get_link,
757 };
758
759 static const struct net_device_ops ep93xx_netdev_ops = {
760 .ndo_open = ep93xx_open,
761 .ndo_stop = ep93xx_close,
762 .ndo_start_xmit = ep93xx_xmit,
763 .ndo_get_stats = ep93xx_get_stats,
764 .ndo_do_ioctl = ep93xx_ioctl,
765 .ndo_validate_addr = eth_validate_addr,
766 .ndo_change_mtu = eth_change_mtu,
767 .ndo_set_mac_address = eth_mac_addr,
768 };
769
770 static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
771 {
772 struct net_device *dev;
773
774 dev = alloc_etherdev(sizeof(struct ep93xx_priv));
775 if (dev == NULL)
776 return NULL;
777
778 memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
779
780 dev->ethtool_ops = &ep93xx_ethtool_ops;
781 dev->netdev_ops = &ep93xx_netdev_ops;
782
783 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
784
785 return dev;
786 }
787
788
789 static int ep93xx_eth_remove(struct platform_device *pdev)
790 {
791 struct net_device *dev;
792 struct ep93xx_priv *ep;
793
794 dev = platform_get_drvdata(pdev);
795 if (dev == NULL)
796 return 0;
797 platform_set_drvdata(pdev, NULL);
798
799 ep = netdev_priv(dev);
800
801 /* @@@ Force down. */
802 unregister_netdev(dev);
803 ep93xx_free_buffers(ep);
804
805 if (ep->base_addr != NULL)
806 iounmap(ep->base_addr);
807
808 if (ep->res != NULL) {
809 release_resource(ep->res);
810 kfree(ep->res);
811 }
812
813 free_netdev(dev);
814
815 return 0;
816 }
817
818 static int ep93xx_eth_probe(struct platform_device *pdev)
819 {
820 struct ep93xx_eth_data *data;
821 struct net_device *dev;
822 struct ep93xx_priv *ep;
823 struct resource *mem;
824 int irq;
825 int err;
826
827 if (pdev == NULL)
828 return -ENODEV;
829 data = pdev->dev.platform_data;
830
831 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
832 irq = platform_get_irq(pdev, 0);
833 if (!mem || irq < 0)
834 return -ENXIO;
835
836 dev = ep93xx_dev_alloc(data);
837 if (dev == NULL) {
838 err = -ENOMEM;
839 goto err_out;
840 }
841 ep = netdev_priv(dev);
842 ep->dev = dev;
843 netif_napi_add(dev, &ep->napi, ep93xx_poll, 64);
844
845 platform_set_drvdata(pdev, dev);
846
847 ep->res = request_mem_region(mem->start, resource_size(mem),
848 dev_name(&pdev->dev));
849 if (ep->res == NULL) {
850 dev_err(&pdev->dev, "Could not reserve memory region\n");
851 err = -ENOMEM;
852 goto err_out;
853 }
854
855 ep->base_addr = ioremap(mem->start, resource_size(mem));
856 if (ep->base_addr == NULL) {
857 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
858 err = -EIO;
859 goto err_out;
860 }
861 ep->irq = irq;
862
863 ep->mii.phy_id = data->phy_id;
864 ep->mii.phy_id_mask = 0x1f;
865 ep->mii.reg_num_mask = 0x1f;
866 ep->mii.dev = dev;
867 ep->mii.mdio_read = ep93xx_mdio_read;
868 ep->mii.mdio_write = ep93xx_mdio_write;
869 ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
870
871 if (is_zero_ether_addr(dev->dev_addr))
872 random_ether_addr(dev->dev_addr);
873
874 err = register_netdev(dev);
875 if (err) {
876 dev_err(&pdev->dev, "Failed to register netdev\n");
877 goto err_out;
878 }
879
880 printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
881 dev->name, ep->irq, dev->dev_addr);
882
883 return 0;
884
885 err_out:
886 ep93xx_eth_remove(pdev);
887 return err;
888 }
889
890
891 static struct platform_driver ep93xx_eth_driver = {
892 .probe = ep93xx_eth_probe,
893 .remove = ep93xx_eth_remove,
894 .driver = {
895 .name = "ep93xx-eth",
896 .owner = THIS_MODULE,
897 },
898 };
899
900 static int __init ep93xx_eth_init_module(void)
901 {
902 printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n");
903 return platform_driver_register(&ep93xx_eth_driver);
904 }
905
906 static void __exit ep93xx_eth_cleanup_module(void)
907 {
908 platform_driver_unregister(&ep93xx_eth_driver);
909 }
910
911 module_init(ep93xx_eth_init_module);
912 module_exit(ep93xx_eth_cleanup_module);
913 MODULE_LICENSE("GPL");
914 MODULE_ALIAS("platform:ep93xx-eth");
Linux with added FPC-III support