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Staging: netwave: delete the driver
[linux/fpc-iii.git] / drivers / net / e1000e / lib.c
bloba8b2c0de27c4084f138f510bf51a274fdd78bf80
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include "e1000.h"
30
31 enum e1000_mng_mode {
32 e1000_mng_mode_none = 0,
33 e1000_mng_mode_asf,
34 e1000_mng_mode_pt,
35 e1000_mng_mode_ipmi,
36 e1000_mng_mode_host_if_only
37 };
38
39 #define E1000_FACTPS_MNGCG 0x20000000
40
41 /* Intel(R) Active Management Technology signature */
42 #define E1000_IAMT_SIGNATURE 0x544D4149
43
44 /**
45 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure
47 *
48 * Determines and stores the system bus information for a particular
49 * network interface. The following bus information is determined and stored:
50 * bus speed, bus width, type (PCIe), and PCIe function.
51 **/
52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
53 {
54 struct e1000_mac_info *mac = &hw->mac;
55 struct e1000_bus_info *bus = &hw->bus;
56 struct e1000_adapter *adapter = hw->adapter;
57 u16 pcie_link_status, cap_offset;
58
59 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
60 if (!cap_offset) {
61 bus->width = e1000_bus_width_unknown;
62 } else {
63 pci_read_config_word(adapter->pdev,
64 cap_offset + PCIE_LINK_STATUS,
65 &pcie_link_status);
66 bus->width = (enum e1000_bus_width)((pcie_link_status &
67 PCIE_LINK_WIDTH_MASK) >>
68 PCIE_LINK_WIDTH_SHIFT);
69 }
70
71 mac->ops.set_lan_id(hw);
72
73 return 0;
74 }
75
76 /**
77 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
78 *
79 * @hw: pointer to the HW structure
80 *
81 * Determines the LAN function id by reading memory-mapped registers
82 * and swaps the port value if requested.
83 **/
84 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
85 {
86 struct e1000_bus_info *bus = &hw->bus;
87 u32 reg;
88
89 /*
90 * The status register reports the correct function number
91 * for the device regardless of function swap state.
92 */
93 reg = er32(STATUS);
94 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
95 }
96
97 /**
98 * e1000_set_lan_id_single_port - Set LAN id for a single port device
99 * @hw: pointer to the HW structure
100 *
101 * Sets the LAN function id to zero for a single port device.
102 **/
103 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
104 {
105 struct e1000_bus_info *bus = &hw->bus;
106
107 bus->func = 0;
108 }
109
110 /**
111 * e1000_clear_vfta_generic - Clear VLAN filter table
112 * @hw: pointer to the HW structure
113 *
114 * Clears the register array which contains the VLAN filter table by
115 * setting all the values to 0.
116 **/
117 void e1000_clear_vfta_generic(struct e1000_hw *hw)
118 {
119 u32 offset;
120
121 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
122 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
123 e1e_flush();
124 }
125 }
126
127 /**
128 * e1000_write_vfta_generic - Write value to VLAN filter table
129 * @hw: pointer to the HW structure
130 * @offset: register offset in VLAN filter table
131 * @value: register value written to VLAN filter table
132 *
133 * Writes value at the given offset in the register array which stores
134 * the VLAN filter table.
135 **/
136 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
137 {
138 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
139 e1e_flush();
140 }
141
142 /**
143 * e1000e_init_rx_addrs - Initialize receive address's
144 * @hw: pointer to the HW structure
145 * @rar_count: receive address registers
146 *
147 * Setups the receive address registers by setting the base receive address
148 * register to the devices MAC address and clearing all the other receive
149 * address registers to 0.
150 **/
151 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
152 {
153 u32 i;
154 u8 mac_addr[ETH_ALEN] = {0};
155
156 /* Setup the receive address */
157 e_dbg("Programming MAC Address into RAR[0]\n");
158
159 e1000e_rar_set(hw, hw->mac.addr, 0);
160
161 /* Zero out the other (rar_entry_count - 1) receive addresses */
162 e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
163 for (i = 1; i < rar_count; i++)
164 e1000e_rar_set(hw, mac_addr, i);
165 }
166
167 /**
168 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
169 * @hw: pointer to the HW structure
170 *
171 * Checks the nvm for an alternate MAC address. An alternate MAC address
172 * can be setup by pre-boot software and must be treated like a permanent
173 * address and must override the actual permanent MAC address. If an
174 * alternate MAC address is found it is programmed into RAR0, replacing
175 * the permanent address that was installed into RAR0 by the Si on reset.
176 * This function will return SUCCESS unless it encounters an error while
177 * reading the EEPROM.
178 **/
179 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
180 {
181 u32 i;
182 s32 ret_val = 0;
183 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
184 u8 alt_mac_addr[ETH_ALEN];
185
186 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
187 &nvm_alt_mac_addr_offset);
188 if (ret_val) {
189 e_dbg("NVM Read Error\n");
190 goto out;
191 }
192
193 if (nvm_alt_mac_addr_offset == 0xFFFF) {
194 /* There is no Alternate MAC Address */
195 goto out;
196 }
197
198 if (hw->bus.func == E1000_FUNC_1)
199 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
200 for (i = 0; i < ETH_ALEN; i += 2) {
201 offset = nvm_alt_mac_addr_offset + (i >> 1);
202 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
203 if (ret_val) {
204 e_dbg("NVM Read Error\n");
205 goto out;
206 }
207
208 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
209 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
210 }
211
212 /* if multicast bit is set, the alternate address will not be used */
213 if (alt_mac_addr[0] & 0x01) {
214 e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
215 goto out;
216 }
217
218 /*
219 * We have a valid alternate MAC address, and we want to treat it the
220 * same as the normal permanent MAC address stored by the HW into the
221 * RAR. Do this by mapping this address into RAR0.
222 */
223 e1000e_rar_set(hw, alt_mac_addr, 0);
224
225 out:
226 return ret_val;
227 }
228
229 /**
230 * e1000e_rar_set - Set receive address register
231 * @hw: pointer to the HW structure
232 * @addr: pointer to the receive address
233 * @index: receive address array register
234 *
235 * Sets the receive address array register at index to the address passed
236 * in by addr.
237 **/
238 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
239 {
240 u32 rar_low, rar_high;
241
242 /*
243 * HW expects these in little endian so we reverse the byte order
244 * from network order (big endian) to little endian
245 */
246 rar_low = ((u32) addr[0] |
247 ((u32) addr[1] << 8) |
248 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
249
250 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
251
252 /* If MAC address zero, no need to set the AV bit */
253 if (rar_low || rar_high)
254 rar_high |= E1000_RAH_AV;
255
256 /*
257 * Some bridges will combine consecutive 32-bit writes into
258 * a single burst write, which will malfunction on some parts.
259 * The flushes avoid this.
260 */
261 ew32(RAL(index), rar_low);
262 e1e_flush();
263 ew32(RAH(index), rar_high);
264 e1e_flush();
265 }
266
267 /**
268 * e1000_hash_mc_addr - Generate a multicast hash value
269 * @hw: pointer to the HW structure
270 * @mc_addr: pointer to a multicast address
271 *
272 * Generates a multicast address hash value which is used to determine
273 * the multicast filter table array address and new table value. See
274 * e1000_mta_set_generic()
275 **/
276 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
277 {
278 u32 hash_value, hash_mask;
279 u8 bit_shift = 0;
280
281 /* Register count multiplied by bits per register */
282 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
283
284 /*
285 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
286 * where 0xFF would still fall within the hash mask.
287 */
288 while (hash_mask >> bit_shift != 0xFF)
289 bit_shift++;
290
291 /*
292 * The portion of the address that is used for the hash table
293 * is determined by the mc_filter_type setting.
294 * The algorithm is such that there is a total of 8 bits of shifting.
295 * The bit_shift for a mc_filter_type of 0 represents the number of
296 * left-shifts where the MSB of mc_addr[5] would still fall within
297 * the hash_mask. Case 0 does this exactly. Since there are a total
298 * of 8 bits of shifting, then mc_addr[4] will shift right the
299 * remaining number of bits. Thus 8 - bit_shift. The rest of the
300 * cases are a variation of this algorithm...essentially raising the
301 * number of bits to shift mc_addr[5] left, while still keeping the
302 * 8-bit shifting total.
303 *
304 * For example, given the following Destination MAC Address and an
305 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
306 * we can see that the bit_shift for case 0 is 4. These are the hash
307 * values resulting from each mc_filter_type...
308 * [0] [1] [2] [3] [4] [5]
309 * 01 AA 00 12 34 56
310 * LSB MSB
311 *
312 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
313 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
314 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
315 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
316 */
317 switch (hw->mac.mc_filter_type) {
318 default:
319 case 0:
320 break;
321 case 1:
322 bit_shift += 1;
323 break;
324 case 2:
325 bit_shift += 2;
326 break;
327 case 3:
328 bit_shift += 4;
329 break;
330 }
331
332 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
333 (((u16) mc_addr[5]) << bit_shift)));
334
335 return hash_value;
336 }
337
338 /**
339 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
340 * @hw: pointer to the HW structure
341 * @mc_addr_list: array of multicast addresses to program
342 * @mc_addr_count: number of multicast addresses to program
343 *
344 * Updates entire Multicast Table Array.
345 * The caller must have a packed mc_addr_list of multicast addresses.
346 **/
347 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
348 u8 *mc_addr_list, u32 mc_addr_count)
349 {
350 u32 hash_value, hash_bit, hash_reg;
351 int i;
352
353 /* clear mta_shadow */
354 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
355
356 /* update mta_shadow from mc_addr_list */
357 for (i = 0; (u32) i < mc_addr_count; i++) {
358 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
359
360 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
361 hash_bit = hash_value & 0x1F;
362
363 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
364 mc_addr_list += (ETH_ALEN);
365 }
366
367 /* replace the entire MTA table */
368 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
369 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
370 e1e_flush();
371 }
372
373 /**
374 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
375 * @hw: pointer to the HW structure
376 *
377 * Clears the base hardware counters by reading the counter registers.
378 **/
379 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
380 {
381 er32(CRCERRS);
382 er32(SYMERRS);
383 er32(MPC);
384 er32(SCC);
385 er32(ECOL);
386 er32(MCC);
387 er32(LATECOL);
388 er32(COLC);
389 er32(DC);
390 er32(SEC);
391 er32(RLEC);
392 er32(XONRXC);
393 er32(XONTXC);
394 er32(XOFFRXC);
395 er32(XOFFTXC);
396 er32(FCRUC);
397 er32(GPRC);
398 er32(BPRC);
399 er32(MPRC);
400 er32(GPTC);
401 er32(GORCL);
402 er32(GORCH);
403 er32(GOTCL);
404 er32(GOTCH);
405 er32(RNBC);
406 er32(RUC);
407 er32(RFC);
408 er32(ROC);
409 er32(RJC);
410 er32(TORL);
411 er32(TORH);
412 er32(TOTL);
413 er32(TOTH);
414 er32(TPR);
415 er32(TPT);
416 er32(MPTC);
417 er32(BPTC);
418 }
419
420 /**
421 * e1000e_check_for_copper_link - Check for link (Copper)
422 * @hw: pointer to the HW structure
423 *
424 * Checks to see of the link status of the hardware has changed. If a
425 * change in link status has been detected, then we read the PHY registers
426 * to get the current speed/duplex if link exists.
427 **/
428 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
429 {
430 struct e1000_mac_info *mac = &hw->mac;
431 s32 ret_val;
432 bool link;
433
434 /*
435 * We only want to go out to the PHY registers to see if Auto-Neg
436 * has completed and/or if our link status has changed. The
437 * get_link_status flag is set upon receiving a Link Status
438 * Change or Rx Sequence Error interrupt.
439 */
440 if (!mac->get_link_status)
441 return 0;
442
443 /*
444 * First we want to see if the MII Status Register reports
445 * link. If so, then we want to get the current speed/duplex
446 * of the PHY.
447 */
448 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
449 if (ret_val)
450 return ret_val;
451
452 if (!link)
453 return ret_val; /* No link detected */
454
455 mac->get_link_status = false;
456
457 /*
458 * Check if there was DownShift, must be checked
459 * immediately after link-up
460 */
461 e1000e_check_downshift(hw);
462
463 /*
464 * If we are forcing speed/duplex, then we simply return since
465 * we have already determined whether we have link or not.
466 */
467 if (!mac->autoneg) {
468 ret_val = -E1000_ERR_CONFIG;
469 return ret_val;
470 }
471
472 /*
473 * Auto-Neg is enabled. Auto Speed Detection takes care
474 * of MAC speed/duplex configuration. So we only need to
475 * configure Collision Distance in the MAC.
476 */
477 e1000e_config_collision_dist(hw);
478
479 /*
480 * Configure Flow Control now that Auto-Neg has completed.
481 * First, we need to restore the desired flow control
482 * settings because we may have had to re-autoneg with a
483 * different link partner.
484 */
485 ret_val = e1000e_config_fc_after_link_up(hw);
486 if (ret_val) {
487 e_dbg("Error configuring flow control\n");
488 }
489
490 return ret_val;
491 }
492
493 /**
494 * e1000e_check_for_fiber_link - Check for link (Fiber)
495 * @hw: pointer to the HW structure
496 *
497 * Checks for link up on the hardware. If link is not up and we have
498 * a signal, then we need to force link up.
499 **/
500 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
501 {
502 struct e1000_mac_info *mac = &hw->mac;
503 u32 rxcw;
504 u32 ctrl;
505 u32 status;
506 s32 ret_val;
507
508 ctrl = er32(CTRL);
509 status = er32(STATUS);
510 rxcw = er32(RXCW);
511
512 /*
513 * If we don't have link (auto-negotiation failed or link partner
514 * cannot auto-negotiate), the cable is plugged in (we have signal),
515 * and our link partner is not trying to auto-negotiate with us (we
516 * are receiving idles or data), we need to force link up. We also
517 * need to give auto-negotiation time to complete, in case the cable
518 * was just plugged in. The autoneg_failed flag does this.
519 */
520 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
521 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
522 (!(rxcw & E1000_RXCW_C))) {
523 if (mac->autoneg_failed == 0) {
524 mac->autoneg_failed = 1;
525 return 0;
526 }
527 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
528
529 /* Disable auto-negotiation in the TXCW register */
530 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
531
532 /* Force link-up and also force full-duplex. */
533 ctrl = er32(CTRL);
534 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
535 ew32(CTRL, ctrl);
536
537 /* Configure Flow Control after forcing link up. */
538 ret_val = e1000e_config_fc_after_link_up(hw);
539 if (ret_val) {
540 e_dbg("Error configuring flow control\n");
541 return ret_val;
542 }
543 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
544 /*
545 * If we are forcing link and we are receiving /C/ ordered
546 * sets, re-enable auto-negotiation in the TXCW register
547 * and disable forced link in the Device Control register
548 * in an attempt to auto-negotiate with our link partner.
549 */
550 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
551 ew32(TXCW, mac->txcw);
552 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
553
554 mac->serdes_has_link = true;
555 }
556
557 return 0;
558 }
559
560 /**
561 * e1000e_check_for_serdes_link - Check for link (Serdes)
562 * @hw: pointer to the HW structure
563 *
564 * Checks for link up on the hardware. If link is not up and we have
565 * a signal, then we need to force link up.
566 **/
567 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
568 {
569 struct e1000_mac_info *mac = &hw->mac;
570 u32 rxcw;
571 u32 ctrl;
572 u32 status;
573 s32 ret_val;
574
575 ctrl = er32(CTRL);
576 status = er32(STATUS);
577 rxcw = er32(RXCW);
578
579 /*
580 * If we don't have link (auto-negotiation failed or link partner
581 * cannot auto-negotiate), and our link partner is not trying to
582 * auto-negotiate with us (we are receiving idles or data),
583 * we need to force link up. We also need to give auto-negotiation
584 * time to complete.
585 */
586 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
587 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
588 if (mac->autoneg_failed == 0) {
589 mac->autoneg_failed = 1;
590 return 0;
591 }
592 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
593
594 /* Disable auto-negotiation in the TXCW register */
595 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
596
597 /* Force link-up and also force full-duplex. */
598 ctrl = er32(CTRL);
599 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
600 ew32(CTRL, ctrl);
601
602 /* Configure Flow Control after forcing link up. */
603 ret_val = e1000e_config_fc_after_link_up(hw);
604 if (ret_val) {
605 e_dbg("Error configuring flow control\n");
606 return ret_val;
607 }
608 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
609 /*
610 * If we are forcing link and we are receiving /C/ ordered
611 * sets, re-enable auto-negotiation in the TXCW register
612 * and disable forced link in the Device Control register
613 * in an attempt to auto-negotiate with our link partner.
614 */
615 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
616 ew32(TXCW, mac->txcw);
617 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
618
619 mac->serdes_has_link = true;
620 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
621 /*
622 * If we force link for non-auto-negotiation switch, check
623 * link status based on MAC synchronization for internal
624 * serdes media type.
625 */
626 /* SYNCH bit and IV bit are sticky. */
627 udelay(10);
628 rxcw = er32(RXCW);
629 if (rxcw & E1000_RXCW_SYNCH) {
630 if (!(rxcw & E1000_RXCW_IV)) {
631 mac->serdes_has_link = true;
632 e_dbg("SERDES: Link up - forced.\n");
633 }
634 } else {
635 mac->serdes_has_link = false;
636 e_dbg("SERDES: Link down - force failed.\n");
637 }
638 }
639
640 if (E1000_TXCW_ANE & er32(TXCW)) {
641 status = er32(STATUS);
642 if (status & E1000_STATUS_LU) {
643 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
644 udelay(10);
645 rxcw = er32(RXCW);
646 if (rxcw & E1000_RXCW_SYNCH) {
647 if (!(rxcw & E1000_RXCW_IV)) {
648 mac->serdes_has_link = true;
649 e_dbg("SERDES: Link up - autoneg "
650 "completed successfully.\n");
651 } else {
652 mac->serdes_has_link = false;
653 e_dbg("SERDES: Link down - invalid"
654 "codewords detected in autoneg.\n");
655 }
656 } else {
657 mac->serdes_has_link = false;
658 e_dbg("SERDES: Link down - no sync.\n");
659 }
660 } else {
661 mac->serdes_has_link = false;
662 e_dbg("SERDES: Link down - autoneg failed\n");
663 }
664 }
665
666 return 0;
667 }
668
669 /**
670 * e1000_set_default_fc_generic - Set flow control default values
671 * @hw: pointer to the HW structure
672 *
673 * Read the EEPROM for the default values for flow control and store the
674 * values.
675 **/
676 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
677 {
678 s32 ret_val;
679 u16 nvm_data;
680
681 /*
682 * Read and store word 0x0F of the EEPROM. This word contains bits
683 * that determine the hardware's default PAUSE (flow control) mode,
684 * a bit that determines whether the HW defaults to enabling or
685 * disabling auto-negotiation, and the direction of the
686 * SW defined pins. If there is no SW over-ride of the flow
687 * control setting, then the variable hw->fc will
688 * be initialized based on a value in the EEPROM.
689 */
690 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
691
692 if (ret_val) {
693 e_dbg("NVM Read Error\n");
694 return ret_val;
695 }
696
697 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
698 hw->fc.requested_mode = e1000_fc_none;
699 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
700 NVM_WORD0F_ASM_DIR)
701 hw->fc.requested_mode = e1000_fc_tx_pause;
702 else
703 hw->fc.requested_mode = e1000_fc_full;
704
705 return 0;
706 }
707
708 /**
709 * e1000e_setup_link - Setup flow control and link settings
710 * @hw: pointer to the HW structure
711 *
712 * Determines which flow control settings to use, then configures flow
713 * control. Calls the appropriate media-specific link configuration
714 * function. Assuming the adapter has a valid link partner, a valid link
715 * should be established. Assumes the hardware has previously been reset
716 * and the transmitter and receiver are not enabled.
717 **/
718 s32 e1000e_setup_link(struct e1000_hw *hw)
719 {
720 struct e1000_mac_info *mac = &hw->mac;
721 s32 ret_val;
722
723 /*
724 * In the case of the phy reset being blocked, we already have a link.
725 * We do not need to set it up again.
726 */
727 if (e1000_check_reset_block(hw))
728 return 0;
729
730 /*
731 * If requested flow control is set to default, set flow control
732 * based on the EEPROM flow control settings.
733 */
734 if (hw->fc.requested_mode == e1000_fc_default) {
735 ret_val = e1000_set_default_fc_generic(hw);
736 if (ret_val)
737 return ret_val;
738 }
739
740 /*
741 * Save off the requested flow control mode for use later. Depending
742 * on the link partner's capabilities, we may or may not use this mode.
743 */
744 hw->fc.current_mode = hw->fc.requested_mode;
745
746 e_dbg("After fix-ups FlowControl is now = %x\n",
747 hw->fc.current_mode);
748
749 /* Call the necessary media_type subroutine to configure the link. */
750 ret_val = mac->ops.setup_physical_interface(hw);
751 if (ret_val)
752 return ret_val;
753
754 /*
755 * Initialize the flow control address, type, and PAUSE timer
756 * registers to their default values. This is done even if flow
757 * control is disabled, because it does not hurt anything to
758 * initialize these registers.
759 */
760 e_dbg("Initializing the Flow Control address, type and timer regs\n");
761 ew32(FCT, FLOW_CONTROL_TYPE);
762 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
763 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
764
765 ew32(FCTTV, hw->fc.pause_time);
766
767 return e1000e_set_fc_watermarks(hw);
768 }
769
770 /**
771 * e1000_commit_fc_settings_generic - Configure flow control
772 * @hw: pointer to the HW structure
773 *
774 * Write the flow control settings to the Transmit Config Word Register (TXCW)
775 * base on the flow control settings in e1000_mac_info.
776 **/
777 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
778 {
779 struct e1000_mac_info *mac = &hw->mac;
780 u32 txcw;
781
782 /*
783 * Check for a software override of the flow control settings, and
784 * setup the device accordingly. If auto-negotiation is enabled, then
785 * software will have to set the "PAUSE" bits to the correct value in
786 * the Transmit Config Word Register (TXCW) and re-start auto-
787 * negotiation. However, if auto-negotiation is disabled, then
788 * software will have to manually configure the two flow control enable
789 * bits in the CTRL register.
790 *
791 * The possible values of the "fc" parameter are:
792 * 0: Flow control is completely disabled
793 * 1: Rx flow control is enabled (we can receive pause frames,
794 * but not send pause frames).
795 * 2: Tx flow control is enabled (we can send pause frames but we
796 * do not support receiving pause frames).
797 * 3: Both Rx and Tx flow control (symmetric) are enabled.
798 */
799 switch (hw->fc.current_mode) {
800 case e1000_fc_none:
801 /* Flow control completely disabled by a software over-ride. */
802 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
803 break;
804 case e1000_fc_rx_pause:
805 /*
806 * Rx Flow control is enabled and Tx Flow control is disabled
807 * by a software over-ride. Since there really isn't a way to
808 * advertise that we are capable of Rx Pause ONLY, we will
809 * advertise that we support both symmetric and asymmetric Rx
810 * PAUSE. Later, we will disable the adapter's ability to send
811 * PAUSE frames.
812 */
813 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
814 break;
815 case e1000_fc_tx_pause:
816 /*
817 * Tx Flow control is enabled, and Rx Flow control is disabled,
818 * by a software over-ride.
819 */
820 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
821 break;
822 case e1000_fc_full:
823 /*
824 * Flow control (both Rx and Tx) is enabled by a software
825 * over-ride.
826 */
827 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
828 break;
829 default:
830 e_dbg("Flow control param set incorrectly\n");
831 return -E1000_ERR_CONFIG;
832 break;
833 }
834
835 ew32(TXCW, txcw);
836 mac->txcw = txcw;
837
838 return 0;
839 }
840
841 /**
842 * e1000_poll_fiber_serdes_link_generic - Poll for link up
843 * @hw: pointer to the HW structure
844 *
845 * Polls for link up by reading the status register, if link fails to come
846 * up with auto-negotiation, then the link is forced if a signal is detected.
847 **/
848 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
849 {
850 struct e1000_mac_info *mac = &hw->mac;
851 u32 i, status;
852 s32 ret_val;
853
854 /*
855 * If we have a signal (the cable is plugged in, or assumed true for
856 * serdes media) then poll for a "Link-Up" indication in the Device
857 * Status Register. Time-out if a link isn't seen in 500 milliseconds
858 * seconds (Auto-negotiation should complete in less than 500
859 * milliseconds even if the other end is doing it in SW).
860 */
861 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
862 msleep(10);
863 status = er32(STATUS);
864 if (status & E1000_STATUS_LU)
865 break;
866 }
867 if (i == FIBER_LINK_UP_LIMIT) {
868 e_dbg("Never got a valid link from auto-neg!!!\n");
869 mac->autoneg_failed = 1;
870 /*
871 * AutoNeg failed to achieve a link, so we'll call
872 * mac->check_for_link. This routine will force the
873 * link up if we detect a signal. This will allow us to
874 * communicate with non-autonegotiating link partners.
875 */
876 ret_val = mac->ops.check_for_link(hw);
877 if (ret_val) {
878 e_dbg("Error while checking for link\n");
879 return ret_val;
880 }
881 mac->autoneg_failed = 0;
882 } else {
883 mac->autoneg_failed = 0;
884 e_dbg("Valid Link Found\n");
885 }
886
887 return 0;
888 }
889
890 /**
891 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
892 * @hw: pointer to the HW structure
893 *
894 * Configures collision distance and flow control for fiber and serdes
895 * links. Upon successful setup, poll for link.
896 **/
897 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
898 {
899 u32 ctrl;
900 s32 ret_val;
901
902 ctrl = er32(CTRL);
903
904 /* Take the link out of reset */
905 ctrl &= ~E1000_CTRL_LRST;
906
907 e1000e_config_collision_dist(hw);
908
909 ret_val = e1000_commit_fc_settings_generic(hw);
910 if (ret_val)
911 return ret_val;
912
913 /*
914 * Since auto-negotiation is enabled, take the link out of reset (the
915 * link will be in reset, because we previously reset the chip). This
916 * will restart auto-negotiation. If auto-negotiation is successful
917 * then the link-up status bit will be set and the flow control enable
918 * bits (RFCE and TFCE) will be set according to their negotiated value.
919 */
920 e_dbg("Auto-negotiation enabled\n");
921
922 ew32(CTRL, ctrl);
923 e1e_flush();
924 msleep(1);
925
926 /*
927 * For these adapters, the SW definable pin 1 is set when the optics
928 * detect a signal. If we have a signal, then poll for a "Link-Up"
929 * indication.
930 */
931 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
932 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
933 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
934 } else {
935 e_dbg("No signal detected\n");
936 }
937
938 return 0;
939 }
940
941 /**
942 * e1000e_config_collision_dist - Configure collision distance
943 * @hw: pointer to the HW structure
944 *
945 * Configures the collision distance to the default value and is used
946 * during link setup. Currently no func pointer exists and all
947 * implementations are handled in the generic version of this function.
948 **/
949 void e1000e_config_collision_dist(struct e1000_hw *hw)
950 {
951 u32 tctl;
952
953 tctl = er32(TCTL);
954
955 tctl &= ~E1000_TCTL_COLD;
956 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
957
958 ew32(TCTL, tctl);
959 e1e_flush();
960 }
961
962 /**
963 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
964 * @hw: pointer to the HW structure
965 *
966 * Sets the flow control high/low threshold (watermark) registers. If
967 * flow control XON frame transmission is enabled, then set XON frame
968 * transmission as well.
969 **/
970 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
971 {
972 u32 fcrtl = 0, fcrth = 0;
973
974 /*
975 * Set the flow control receive threshold registers. Normally,
976 * these registers will be set to a default threshold that may be
977 * adjusted later by the driver's runtime code. However, if the
978 * ability to transmit pause frames is not enabled, then these
979 * registers will be set to 0.
980 */
981 if (hw->fc.current_mode & e1000_fc_tx_pause) {
982 /*
983 * We need to set up the Receive Threshold high and low water
984 * marks as well as (optionally) enabling the transmission of
985 * XON frames.
986 */
987 fcrtl = hw->fc.low_water;
988 fcrtl |= E1000_FCRTL_XONE;
989 fcrth = hw->fc.high_water;
990 }
991 ew32(FCRTL, fcrtl);
992 ew32(FCRTH, fcrth);
993
994 return 0;
995 }
996
997 /**
998 * e1000e_force_mac_fc - Force the MAC's flow control settings
999 * @hw: pointer to the HW structure
1000 *
1001 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1002 * device control register to reflect the adapter settings. TFCE and RFCE
1003 * need to be explicitly set by software when a copper PHY is used because
1004 * autonegotiation is managed by the PHY rather than the MAC. Software must
1005 * also configure these bits when link is forced on a fiber connection.
1006 **/
1007 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
1008 {
1009 u32 ctrl;
1010
1011 ctrl = er32(CTRL);
1012
1013 /*
1014 * Because we didn't get link via the internal auto-negotiation
1015 * mechanism (we either forced link or we got link via PHY
1016 * auto-neg), we have to manually enable/disable transmit an
1017 * receive flow control.
1018 *
1019 * The "Case" statement below enables/disable flow control
1020 * according to the "hw->fc.current_mode" parameter.
1021 *
1022 * The possible values of the "fc" parameter are:
1023 * 0: Flow control is completely disabled
1024 * 1: Rx flow control is enabled (we can receive pause
1025 * frames but not send pause frames).
1026 * 2: Tx flow control is enabled (we can send pause frames
1027 * frames but we do not receive pause frames).
1028 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1029 * other: No other values should be possible at this point.
1030 */
1031 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1032
1033 switch (hw->fc.current_mode) {
1034 case e1000_fc_none:
1035 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1036 break;
1037 case e1000_fc_rx_pause:
1038 ctrl &= (~E1000_CTRL_TFCE);
1039 ctrl |= E1000_CTRL_RFCE;
1040 break;
1041 case e1000_fc_tx_pause:
1042 ctrl &= (~E1000_CTRL_RFCE);
1043 ctrl |= E1000_CTRL_TFCE;
1044 break;
1045 case e1000_fc_full:
1046 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1047 break;
1048 default:
1049 e_dbg("Flow control param set incorrectly\n");
1050 return -E1000_ERR_CONFIG;
1051 }
1052
1053 ew32(CTRL, ctrl);
1054
1055 return 0;
1056 }
1057
1058 /**
1059 * e1000e_config_fc_after_link_up - Configures flow control after link
1060 * @hw: pointer to the HW structure
1061 *
1062 * Checks the status of auto-negotiation after link up to ensure that the
1063 * speed and duplex were not forced. If the link needed to be forced, then
1064 * flow control needs to be forced also. If auto-negotiation is enabled
1065 * and did not fail, then we configure flow control based on our link
1066 * partner.
1067 **/
1068 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1069 {
1070 struct e1000_mac_info *mac = &hw->mac;
1071 s32 ret_val = 0;
1072 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1073 u16 speed, duplex;
1074
1075 /*
1076 * Check for the case where we have fiber media and auto-neg failed
1077 * so we had to force link. In this case, we need to force the
1078 * configuration of the MAC to match the "fc" parameter.
1079 */
1080 if (mac->autoneg_failed) {
1081 if (hw->phy.media_type == e1000_media_type_fiber ||
1082 hw->phy.media_type == e1000_media_type_internal_serdes)
1083 ret_val = e1000e_force_mac_fc(hw);
1084 } else {
1085 if (hw->phy.media_type == e1000_media_type_copper)
1086 ret_val = e1000e_force_mac_fc(hw);
1087 }
1088
1089 if (ret_val) {
1090 e_dbg("Error forcing flow control settings\n");
1091 return ret_val;
1092 }
1093
1094 /*
1095 * Check for the case where we have copper media and auto-neg is
1096 * enabled. In this case, we need to check and see if Auto-Neg
1097 * has completed, and if so, how the PHY and link partner has
1098 * flow control configured.
1099 */
1100 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1101 /*
1102 * Read the MII Status Register and check to see if AutoNeg
1103 * has completed. We read this twice because this reg has
1104 * some "sticky" (latched) bits.
1105 */
1106 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1107 if (ret_val)
1108 return ret_val;
1109 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1110 if (ret_val)
1111 return ret_val;
1112
1113 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1114 e_dbg("Copper PHY and Auto Neg "
1115 "has not completed.\n");
1116 return ret_val;
1117 }
1118
1119 /*
1120 * The AutoNeg process has completed, so we now need to
1121 * read both the Auto Negotiation Advertisement
1122 * Register (Address 4) and the Auto_Negotiation Base
1123 * Page Ability Register (Address 5) to determine how
1124 * flow control was negotiated.
1125 */
1126 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1127 if (ret_val)
1128 return ret_val;
1129 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1130 if (ret_val)
1131 return ret_val;
1132
1133 /*
1134 * Two bits in the Auto Negotiation Advertisement Register
1135 * (Address 4) and two bits in the Auto Negotiation Base
1136 * Page Ability Register (Address 5) determine flow control
1137 * for both the PHY and the link partner. The following
1138 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1139 * 1999, describes these PAUSE resolution bits and how flow
1140 * control is determined based upon these settings.
1141 * NOTE: DC = Don't Care
1142 *
1143 * LOCAL DEVICE | LINK PARTNER
1144 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1145 *-------|---------|-------|---------|--------------------
1146 * 0 | 0 | DC | DC | e1000_fc_none
1147 * 0 | 1 | 0 | DC | e1000_fc_none
1148 * 0 | 1 | 1 | 0 | e1000_fc_none
1149 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1150 * 1 | 0 | 0 | DC | e1000_fc_none
1151 * 1 | DC | 1 | DC | e1000_fc_full
1152 * 1 | 1 | 0 | 0 | e1000_fc_none
1153 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1154 *
1155 * Are both PAUSE bits set to 1? If so, this implies
1156 * Symmetric Flow Control is enabled at both ends. The
1157 * ASM_DIR bits are irrelevant per the spec.
1158 *
1159 * For Symmetric Flow Control:
1160 *
1161 * LOCAL DEVICE | LINK PARTNER
1162 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1163 *-------|---------|-------|---------|--------------------
1164 * 1 | DC | 1 | DC | E1000_fc_full
1165 *
1166 */
1167 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1168 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1169 /*
1170 * Now we need to check if the user selected Rx ONLY
1171 * of pause frames. In this case, we had to advertise
1172 * FULL flow control because we could not advertise Rx
1173 * ONLY. Hence, we must now check to see if we need to
1174 * turn OFF the TRANSMISSION of PAUSE frames.
1175 */
1176 if (hw->fc.requested_mode == e1000_fc_full) {
1177 hw->fc.current_mode = e1000_fc_full;
1178 e_dbg("Flow Control = FULL.\r\n");
1179 } else {
1180 hw->fc.current_mode = e1000_fc_rx_pause;
1181 e_dbg("Flow Control = "
1182 "RX PAUSE frames only.\r\n");
1183 }
1184 }
1185 /*
1186 * For receiving PAUSE frames ONLY.
1187 *
1188 * LOCAL DEVICE | LINK PARTNER
1189 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1190 *-------|---------|-------|---------|--------------------
1191 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1192 */
1193 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1194 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1195 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1196 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1197 hw->fc.current_mode = e1000_fc_tx_pause;
1198 e_dbg("Flow Control = Tx PAUSE frames only.\r\n");
1199 }
1200 /*
1201 * For transmitting PAUSE frames ONLY.
1202 *
1203 * LOCAL DEVICE | LINK PARTNER
1204 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1205 *-------|---------|-------|---------|--------------------
1206 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1207 */
1208 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1209 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1210 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1211 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1212 hw->fc.current_mode = e1000_fc_rx_pause;
1213 e_dbg("Flow Control = Rx PAUSE frames only.\r\n");
1214 } else {
1215 /*
1216 * Per the IEEE spec, at this point flow control
1217 * should be disabled.
1218 */
1219 hw->fc.current_mode = e1000_fc_none;
1220 e_dbg("Flow Control = NONE.\r\n");
1221 }
1222
1223 /*
1224 * Now we need to do one last check... If we auto-
1225 * negotiated to HALF DUPLEX, flow control should not be
1226 * enabled per IEEE 802.3 spec.
1227 */
1228 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1229 if (ret_val) {
1230 e_dbg("Error getting link speed and duplex\n");
1231 return ret_val;
1232 }
1233
1234 if (duplex == HALF_DUPLEX)
1235 hw->fc.current_mode = e1000_fc_none;
1236
1237 /*
1238 * Now we call a subroutine to actually force the MAC
1239 * controller to use the correct flow control settings.
1240 */
1241 ret_val = e1000e_force_mac_fc(hw);
1242 if (ret_val) {
1243 e_dbg("Error forcing flow control settings\n");
1244 return ret_val;
1245 }
1246 }
1247
1248 return 0;
1249 }
1250
1251 /**
1252 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1253 * @hw: pointer to the HW structure
1254 * @speed: stores the current speed
1255 * @duplex: stores the current duplex
1256 *
1257 * Read the status register for the current speed/duplex and store the current
1258 * speed and duplex for copper connections.
1259 **/
1260 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1261 {
1262 u32 status;
1263
1264 status = er32(STATUS);
1265 if (status & E1000_STATUS_SPEED_1000) {
1266 *speed = SPEED_1000;
1267 e_dbg("1000 Mbs, ");
1268 } else if (status & E1000_STATUS_SPEED_100) {
1269 *speed = SPEED_100;
1270 e_dbg("100 Mbs, ");
1271 } else {
1272 *speed = SPEED_10;
1273 e_dbg("10 Mbs, ");
1274 }
1275
1276 if (status & E1000_STATUS_FD) {
1277 *duplex = FULL_DUPLEX;
1278 e_dbg("Full Duplex\n");
1279 } else {
1280 *duplex = HALF_DUPLEX;
1281 e_dbg("Half Duplex\n");
1282 }
1283
1284 return 0;
1285 }
1286
1287 /**
1288 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1289 * @hw: pointer to the HW structure
1290 * @speed: stores the current speed
1291 * @duplex: stores the current duplex
1292 *
1293 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1294 * for fiber/serdes links.
1295 **/
1296 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1297 {
1298 *speed = SPEED_1000;
1299 *duplex = FULL_DUPLEX;
1300
1301 return 0;
1302 }
1303
1304 /**
1305 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1306 * @hw: pointer to the HW structure
1307 *
1308 * Acquire the HW semaphore to access the PHY or NVM
1309 **/
1310 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1311 {
1312 u32 swsm;
1313 s32 timeout = hw->nvm.word_size + 1;
1314 s32 i = 0;
1315
1316 /* Get the SW semaphore */
1317 while (i < timeout) {
1318 swsm = er32(SWSM);
1319 if (!(swsm & E1000_SWSM_SMBI))
1320 break;
1321
1322 udelay(50);
1323 i++;
1324 }
1325
1326 if (i == timeout) {
1327 e_dbg("Driver can't access device - SMBI bit is set.\n");
1328 return -E1000_ERR_NVM;
1329 }
1330
1331 /* Get the FW semaphore. */
1332 for (i = 0; i < timeout; i++) {
1333 swsm = er32(SWSM);
1334 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1335
1336 /* Semaphore acquired if bit latched */
1337 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1338 break;
1339
1340 udelay(50);
1341 }
1342
1343 if (i == timeout) {
1344 /* Release semaphores */
1345 e1000e_put_hw_semaphore(hw);
1346 e_dbg("Driver can't access the NVM\n");
1347 return -E1000_ERR_NVM;
1348 }
1349
1350 return 0;
1351 }
1352
1353 /**
1354 * e1000e_put_hw_semaphore - Release hardware semaphore
1355 * @hw: pointer to the HW structure
1356 *
1357 * Release hardware semaphore used to access the PHY or NVM
1358 **/
1359 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1360 {
1361 u32 swsm;
1362
1363 swsm = er32(SWSM);
1364 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1365 ew32(SWSM, swsm);
1366 }
1367
1368 /**
1369 * e1000e_get_auto_rd_done - Check for auto read completion
1370 * @hw: pointer to the HW structure
1371 *
1372 * Check EEPROM for Auto Read done bit.
1373 **/
1374 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1375 {
1376 s32 i = 0;
1377
1378 while (i < AUTO_READ_DONE_TIMEOUT) {
1379 if (er32(EECD) & E1000_EECD_AUTO_RD)
1380 break;
1381 msleep(1);
1382 i++;
1383 }
1384
1385 if (i == AUTO_READ_DONE_TIMEOUT) {
1386 e_dbg("Auto read by HW from NVM has not completed.\n");
1387 return -E1000_ERR_RESET;
1388 }
1389
1390 return 0;
1391 }
1392
1393 /**
1394 * e1000e_valid_led_default - Verify a valid default LED config
1395 * @hw: pointer to the HW structure
1396 * @data: pointer to the NVM (EEPROM)
1397 *
1398 * Read the EEPROM for the current default LED configuration. If the
1399 * LED configuration is not valid, set to a valid LED configuration.
1400 **/
1401 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1402 {
1403 s32 ret_val;
1404
1405 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1406 if (ret_val) {
1407 e_dbg("NVM Read Error\n");
1408 return ret_val;
1409 }
1410
1411 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1412 *data = ID_LED_DEFAULT;
1413
1414 return 0;
1415 }
1416
1417 /**
1418 * e1000e_id_led_init -
1419 * @hw: pointer to the HW structure
1420 *
1421 **/
1422 s32 e1000e_id_led_init(struct e1000_hw *hw)
1423 {
1424 struct e1000_mac_info *mac = &hw->mac;
1425 s32 ret_val;
1426 const u32 ledctl_mask = 0x000000FF;
1427 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1428 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1429 u16 data, i, temp;
1430 const u16 led_mask = 0x0F;
1431
1432 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1433 if (ret_val)
1434 return ret_val;
1435
1436 mac->ledctl_default = er32(LEDCTL);
1437 mac->ledctl_mode1 = mac->ledctl_default;
1438 mac->ledctl_mode2 = mac->ledctl_default;
1439
1440 for (i = 0; i < 4; i++) {
1441 temp = (data >> (i << 2)) & led_mask;
1442 switch (temp) {
1443 case ID_LED_ON1_DEF2:
1444 case ID_LED_ON1_ON2:
1445 case ID_LED_ON1_OFF2:
1446 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1447 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1448 break;
1449 case ID_LED_OFF1_DEF2:
1450 case ID_LED_OFF1_ON2:
1451 case ID_LED_OFF1_OFF2:
1452 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1453 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1454 break;
1455 default:
1456 /* Do nothing */
1457 break;
1458 }
1459 switch (temp) {
1460 case ID_LED_DEF1_ON2:
1461 case ID_LED_ON1_ON2:
1462 case ID_LED_OFF1_ON2:
1463 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1464 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1465 break;
1466 case ID_LED_DEF1_OFF2:
1467 case ID_LED_ON1_OFF2:
1468 case ID_LED_OFF1_OFF2:
1469 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1470 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1471 break;
1472 default:
1473 /* Do nothing */
1474 break;
1475 }
1476 }
1477
1478 return 0;
1479 }
1480
1481 /**
1482 * e1000e_setup_led_generic - Configures SW controllable LED
1483 * @hw: pointer to the HW structure
1484 *
1485 * This prepares the SW controllable LED for use and saves the current state
1486 * of the LED so it can be later restored.
1487 **/
1488 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1489 {
1490 u32 ledctl;
1491
1492 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) {
1493 return -E1000_ERR_CONFIG;
1494 }
1495
1496 if (hw->phy.media_type == e1000_media_type_fiber) {
1497 ledctl = er32(LEDCTL);
1498 hw->mac.ledctl_default = ledctl;
1499 /* Turn off LED0 */
1500 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1501 E1000_LEDCTL_LED0_BLINK |
1502 E1000_LEDCTL_LED0_MODE_MASK);
1503 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1504 E1000_LEDCTL_LED0_MODE_SHIFT);
1505 ew32(LEDCTL, ledctl);
1506 } else if (hw->phy.media_type == e1000_media_type_copper) {
1507 ew32(LEDCTL, hw->mac.ledctl_mode1);
1508 }
1509
1510 return 0;
1511 }
1512
1513 /**
1514 * e1000e_cleanup_led_generic - Set LED config to default operation
1515 * @hw: pointer to the HW structure
1516 *
1517 * Remove the current LED configuration and set the LED configuration
1518 * to the default value, saved from the EEPROM.
1519 **/
1520 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1521 {
1522 ew32(LEDCTL, hw->mac.ledctl_default);
1523 return 0;
1524 }
1525
1526 /**
1527 * e1000e_blink_led - Blink LED
1528 * @hw: pointer to the HW structure
1529 *
1530 * Blink the LEDs which are set to be on.
1531 **/
1532 s32 e1000e_blink_led(struct e1000_hw *hw)
1533 {
1534 u32 ledctl_blink = 0;
1535 u32 i;
1536
1537 if (hw->phy.media_type == e1000_media_type_fiber) {
1538 /* always blink LED0 for PCI-E fiber */
1539 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1540 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1541 } else {
1542 /*
1543 * set the blink bit for each LED that's "on" (0x0E)
1544 * in ledctl_mode2
1545 */
1546 ledctl_blink = hw->mac.ledctl_mode2;
1547 for (i = 0; i < 4; i++)
1548 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1549 E1000_LEDCTL_MODE_LED_ON)
1550 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1551 (i * 8));
1552 }
1553
1554 ew32(LEDCTL, ledctl_blink);
1555
1556 return 0;
1557 }
1558
1559 /**
1560 * e1000e_led_on_generic - Turn LED on
1561 * @hw: pointer to the HW structure
1562 *
1563 * Turn LED on.
1564 **/
1565 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1566 {
1567 u32 ctrl;
1568
1569 switch (hw->phy.media_type) {
1570 case e1000_media_type_fiber:
1571 ctrl = er32(CTRL);
1572 ctrl &= ~E1000_CTRL_SWDPIN0;
1573 ctrl |= E1000_CTRL_SWDPIO0;
1574 ew32(CTRL, ctrl);
1575 break;
1576 case e1000_media_type_copper:
1577 ew32(LEDCTL, hw->mac.ledctl_mode2);
1578 break;
1579 default:
1580 break;
1581 }
1582
1583 return 0;
1584 }
1585
1586 /**
1587 * e1000e_led_off_generic - Turn LED off
1588 * @hw: pointer to the HW structure
1589 *
1590 * Turn LED off.
1591 **/
1592 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1593 {
1594 u32 ctrl;
1595
1596 switch (hw->phy.media_type) {
1597 case e1000_media_type_fiber:
1598 ctrl = er32(CTRL);
1599 ctrl |= E1000_CTRL_SWDPIN0;
1600 ctrl |= E1000_CTRL_SWDPIO0;
1601 ew32(CTRL, ctrl);
1602 break;
1603 case e1000_media_type_copper:
1604 ew32(LEDCTL, hw->mac.ledctl_mode1);
1605 break;
1606 default:
1607 break;
1608 }
1609
1610 return 0;
1611 }
1612
1613 /**
1614 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1615 * @hw: pointer to the HW structure
1616 * @no_snoop: bitmap of snoop events
1617 *
1618 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1619 **/
1620 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1621 {
1622 u32 gcr;
1623
1624 if (no_snoop) {
1625 gcr = er32(GCR);
1626 gcr &= ~(PCIE_NO_SNOOP_ALL);
1627 gcr |= no_snoop;
1628 ew32(GCR, gcr);
1629 }
1630 }
1631
1632 /**
1633 * e1000e_disable_pcie_master - Disables PCI-express master access
1634 * @hw: pointer to the HW structure
1635 *
1636 * Returns 0 if successful, else returns -10
1637 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1638 * the master requests to be disabled.
1639 *
1640 * Disables PCI-Express master access and verifies there are no pending
1641 * requests.
1642 **/
1643 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1644 {
1645 u32 ctrl;
1646 s32 timeout = MASTER_DISABLE_TIMEOUT;
1647
1648 ctrl = er32(CTRL);
1649 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1650 ew32(CTRL, ctrl);
1651
1652 while (timeout) {
1653 if (!(er32(STATUS) &
1654 E1000_STATUS_GIO_MASTER_ENABLE))
1655 break;
1656 udelay(100);
1657 timeout--;
1658 }
1659
1660 if (!timeout) {
1661 e_dbg("Master requests are pending.\n");
1662 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1663 }
1664
1665 return 0;
1666 }
1667
1668 /**
1669 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1670 * @hw: pointer to the HW structure
1671 *
1672 * Reset the Adaptive Interframe Spacing throttle to default values.
1673 **/
1674 void e1000e_reset_adaptive(struct e1000_hw *hw)
1675 {
1676 struct e1000_mac_info *mac = &hw->mac;
1677
1678 if (!mac->adaptive_ifs) {
1679 e_dbg("Not in Adaptive IFS mode!\n");
1680 goto out;
1681 }
1682
1683 mac->current_ifs_val = 0;
1684 mac->ifs_min_val = IFS_MIN;
1685 mac->ifs_max_val = IFS_MAX;
1686 mac->ifs_step_size = IFS_STEP;
1687 mac->ifs_ratio = IFS_RATIO;
1688
1689 mac->in_ifs_mode = false;
1690 ew32(AIT, 0);
1691 out:
1692 return;
1693 }
1694
1695 /**
1696 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1697 * @hw: pointer to the HW structure
1698 *
1699 * Update the Adaptive Interframe Spacing Throttle value based on the
1700 * time between transmitted packets and time between collisions.
1701 **/
1702 void e1000e_update_adaptive(struct e1000_hw *hw)
1703 {
1704 struct e1000_mac_info *mac = &hw->mac;
1705
1706 if (!mac->adaptive_ifs) {
1707 e_dbg("Not in Adaptive IFS mode!\n");
1708 goto out;
1709 }
1710
1711 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1712 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1713 mac->in_ifs_mode = true;
1714 if (mac->current_ifs_val < mac->ifs_max_val) {
1715 if (!mac->current_ifs_val)
1716 mac->current_ifs_val = mac->ifs_min_val;
1717 else
1718 mac->current_ifs_val +=
1719 mac->ifs_step_size;
1720 ew32(AIT, mac->current_ifs_val);
1721 }
1722 }
1723 } else {
1724 if (mac->in_ifs_mode &&
1725 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1726 mac->current_ifs_val = 0;
1727 mac->in_ifs_mode = false;
1728 ew32(AIT, 0);
1729 }
1730 }
1731 out:
1732 return;
1733 }
1734
1735 /**
1736 * e1000_raise_eec_clk - Raise EEPROM clock
1737 * @hw: pointer to the HW structure
1738 * @eecd: pointer to the EEPROM
1739 *
1740 * Enable/Raise the EEPROM clock bit.
1741 **/
1742 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1743 {
1744 *eecd = *eecd | E1000_EECD_SK;
1745 ew32(EECD, *eecd);
1746 e1e_flush();
1747 udelay(hw->nvm.delay_usec);
1748 }
1749
1750 /**
1751 * e1000_lower_eec_clk - Lower EEPROM clock
1752 * @hw: pointer to the HW structure
1753 * @eecd: pointer to the EEPROM
1754 *
1755 * Clear/Lower the EEPROM clock bit.
1756 **/
1757 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1758 {
1759 *eecd = *eecd & ~E1000_EECD_SK;
1760 ew32(EECD, *eecd);
1761 e1e_flush();
1762 udelay(hw->nvm.delay_usec);
1763 }
1764
1765 /**
1766 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1767 * @hw: pointer to the HW structure
1768 * @data: data to send to the EEPROM
1769 * @count: number of bits to shift out
1770 *
1771 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1772 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1773 * In order to do this, "data" must be broken down into bits.
1774 **/
1775 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1776 {
1777 struct e1000_nvm_info *nvm = &hw->nvm;
1778 u32 eecd = er32(EECD);
1779 u32 mask;
1780
1781 mask = 0x01 << (count - 1);
1782 if (nvm->type == e1000_nvm_eeprom_spi)
1783 eecd |= E1000_EECD_DO;
1784
1785 do {
1786 eecd &= ~E1000_EECD_DI;
1787
1788 if (data & mask)
1789 eecd |= E1000_EECD_DI;
1790
1791 ew32(EECD, eecd);
1792 e1e_flush();
1793
1794 udelay(nvm->delay_usec);
1795
1796 e1000_raise_eec_clk(hw, &eecd);
1797 e1000_lower_eec_clk(hw, &eecd);
1798
1799 mask >>= 1;
1800 } while (mask);
1801
1802 eecd &= ~E1000_EECD_DI;
1803 ew32(EECD, eecd);
1804 }
1805
1806 /**
1807 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1808 * @hw: pointer to the HW structure
1809 * @count: number of bits to shift in
1810 *
1811 * In order to read a register from the EEPROM, we need to shift 'count' bits
1812 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1813 * the EEPROM (setting the SK bit), and then reading the value of the data out
1814 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1815 * always be clear.
1816 **/
1817 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1818 {
1819 u32 eecd;
1820 u32 i;
1821 u16 data;
1822
1823 eecd = er32(EECD);
1824
1825 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1826 data = 0;
1827
1828 for (i = 0; i < count; i++) {
1829 data <<= 1;
1830 e1000_raise_eec_clk(hw, &eecd);
1831
1832 eecd = er32(EECD);
1833
1834 eecd &= ~E1000_EECD_DI;
1835 if (eecd & E1000_EECD_DO)
1836 data |= 1;
1837
1838 e1000_lower_eec_clk(hw, &eecd);
1839 }
1840
1841 return data;
1842 }
1843
1844 /**
1845 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1846 * @hw: pointer to the HW structure
1847 * @ee_reg: EEPROM flag for polling
1848 *
1849 * Polls the EEPROM status bit for either read or write completion based
1850 * upon the value of 'ee_reg'.
1851 **/
1852 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1853 {
1854 u32 attempts = 100000;
1855 u32 i, reg = 0;
1856
1857 for (i = 0; i < attempts; i++) {
1858 if (ee_reg == E1000_NVM_POLL_READ)
1859 reg = er32(EERD);
1860 else
1861 reg = er32(EEWR);
1862
1863 if (reg & E1000_NVM_RW_REG_DONE)
1864 return 0;
1865
1866 udelay(5);
1867 }
1868
1869 return -E1000_ERR_NVM;
1870 }
1871
1872 /**
1873 * e1000e_acquire_nvm - Generic request for access to EEPROM
1874 * @hw: pointer to the HW structure
1875 *
1876 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1877 * Return successful if access grant bit set, else clear the request for
1878 * EEPROM access and return -E1000_ERR_NVM (-1).
1879 **/
1880 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1881 {
1882 u32 eecd = er32(EECD);
1883 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1884
1885 ew32(EECD, eecd | E1000_EECD_REQ);
1886 eecd = er32(EECD);
1887
1888 while (timeout) {
1889 if (eecd & E1000_EECD_GNT)
1890 break;
1891 udelay(5);
1892 eecd = er32(EECD);
1893 timeout--;
1894 }
1895
1896 if (!timeout) {
1897 eecd &= ~E1000_EECD_REQ;
1898 ew32(EECD, eecd);
1899 e_dbg("Could not acquire NVM grant\n");
1900 return -E1000_ERR_NVM;
1901 }
1902
1903 return 0;
1904 }
1905
1906 /**
1907 * e1000_standby_nvm - Return EEPROM to standby state
1908 * @hw: pointer to the HW structure
1909 *
1910 * Return the EEPROM to a standby state.
1911 **/
1912 static void e1000_standby_nvm(struct e1000_hw *hw)
1913 {
1914 struct e1000_nvm_info *nvm = &hw->nvm;
1915 u32 eecd = er32(EECD);
1916
1917 if (nvm->type == e1000_nvm_eeprom_spi) {
1918 /* Toggle CS to flush commands */
1919 eecd |= E1000_EECD_CS;
1920 ew32(EECD, eecd);
1921 e1e_flush();
1922 udelay(nvm->delay_usec);
1923 eecd &= ~E1000_EECD_CS;
1924 ew32(EECD, eecd);
1925 e1e_flush();
1926 udelay(nvm->delay_usec);
1927 }
1928 }
1929
1930 /**
1931 * e1000_stop_nvm - Terminate EEPROM command
1932 * @hw: pointer to the HW structure
1933 *
1934 * Terminates the current command by inverting the EEPROM's chip select pin.
1935 **/
1936 static void e1000_stop_nvm(struct e1000_hw *hw)
1937 {
1938 u32 eecd;
1939
1940 eecd = er32(EECD);
1941 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1942 /* Pull CS high */
1943 eecd |= E1000_EECD_CS;
1944 e1000_lower_eec_clk(hw, &eecd);
1945 }
1946 }
1947
1948 /**
1949 * e1000e_release_nvm - Release exclusive access to EEPROM
1950 * @hw: pointer to the HW structure
1951 *
1952 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1953 **/
1954 void e1000e_release_nvm(struct e1000_hw *hw)
1955 {
1956 u32 eecd;
1957
1958 e1000_stop_nvm(hw);
1959
1960 eecd = er32(EECD);
1961 eecd &= ~E1000_EECD_REQ;
1962 ew32(EECD, eecd);
1963 }
1964
1965 /**
1966 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1967 * @hw: pointer to the HW structure
1968 *
1969 * Setups the EEPROM for reading and writing.
1970 **/
1971 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1972 {
1973 struct e1000_nvm_info *nvm = &hw->nvm;
1974 u32 eecd = er32(EECD);
1975 u16 timeout = 0;
1976 u8 spi_stat_reg;
1977
1978 if (nvm->type == e1000_nvm_eeprom_spi) {
1979 /* Clear SK and CS */
1980 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1981 ew32(EECD, eecd);
1982 udelay(1);
1983 timeout = NVM_MAX_RETRY_SPI;
1984
1985 /*
1986 * Read "Status Register" repeatedly until the LSB is cleared.
1987 * The EEPROM will signal that the command has been completed
1988 * by clearing bit 0 of the internal status register. If it's
1989 * not cleared within 'timeout', then error out.
1990 */
1991 while (timeout) {
1992 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
1993 hw->nvm.opcode_bits);
1994 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
1995 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
1996 break;
1997
1998 udelay(5);
1999 e1000_standby_nvm(hw);
2000 timeout--;
2001 }
2002
2003 if (!timeout) {
2004 e_dbg("SPI NVM Status error\n");
2005 return -E1000_ERR_NVM;
2006 }
2007 }
2008
2009 return 0;
2010 }
2011
2012 /**
2013 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
2014 * @hw: pointer to the HW structure
2015 * @offset: offset of word in the EEPROM to read
2016 * @words: number of words to read
2017 * @data: word read from the EEPROM
2018 *
2019 * Reads a 16 bit word from the EEPROM using the EERD register.
2020 **/
2021 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2022 {
2023 struct e1000_nvm_info *nvm = &hw->nvm;
2024 u32 i, eerd = 0;
2025 s32 ret_val = 0;
2026
2027 /*
2028 * A check for invalid values: offset too large, too many words,
2029 * too many words for the offset, and not enough words.
2030 */
2031 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2032 (words == 0)) {
2033 e_dbg("nvm parameter(s) out of bounds\n");
2034 return -E1000_ERR_NVM;
2035 }
2036
2037 for (i = 0; i < words; i++) {
2038 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
2039 E1000_NVM_RW_REG_START;
2040
2041 ew32(EERD, eerd);
2042 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
2043 if (ret_val)
2044 break;
2045
2046 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
2047 }
2048
2049 return ret_val;
2050 }
2051
2052 /**
2053 * e1000e_write_nvm_spi - Write to EEPROM using SPI
2054 * @hw: pointer to the HW structure
2055 * @offset: offset within the EEPROM to be written to
2056 * @words: number of words to write
2057 * @data: 16 bit word(s) to be written to the EEPROM
2058 *
2059 * Writes data to EEPROM at offset using SPI interface.
2060 *
2061 * If e1000e_update_nvm_checksum is not called after this function , the
2062 * EEPROM will most likely contain an invalid checksum.
2063 **/
2064 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2065 {
2066 struct e1000_nvm_info *nvm = &hw->nvm;
2067 s32 ret_val;
2068 u16 widx = 0;
2069
2070 /*
2071 * A check for invalid values: offset too large, too many words,
2072 * and not enough words.
2073 */
2074 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2075 (words == 0)) {
2076 e_dbg("nvm parameter(s) out of bounds\n");
2077 return -E1000_ERR_NVM;
2078 }
2079
2080 ret_val = nvm->ops.acquire(hw);
2081 if (ret_val)
2082 return ret_val;
2083
2084 msleep(10);
2085
2086 while (widx < words) {
2087 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
2088
2089 ret_val = e1000_ready_nvm_eeprom(hw);
2090 if (ret_val) {
2091 nvm->ops.release(hw);
2092 return ret_val;
2093 }
2094
2095 e1000_standby_nvm(hw);
2096
2097 /* Send the WRITE ENABLE command (8 bit opcode) */
2098 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2099 nvm->opcode_bits);
2100
2101 e1000_standby_nvm(hw);
2102
2103 /*
2104 * Some SPI eeproms use the 8th address bit embedded in the
2105 * opcode
2106 */
2107 if ((nvm->address_bits == 8) && (offset >= 128))
2108 write_opcode |= NVM_A8_OPCODE_SPI;
2109
2110 /* Send the Write command (8-bit opcode + addr) */
2111 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2112 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2113 nvm->address_bits);
2114
2115 /* Loop to allow for up to whole page write of eeprom */
2116 while (widx < words) {
2117 u16 word_out = data[widx];
2118 word_out = (word_out >> 8) | (word_out << 8);
2119 e1000_shift_out_eec_bits(hw, word_out, 16);
2120 widx++;
2121
2122 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2123 e1000_standby_nvm(hw);
2124 break;
2125 }
2126 }
2127 }
2128
2129 msleep(10);
2130 nvm->ops.release(hw);
2131 return 0;
2132 }
2133
2134 /**
2135 * e1000_read_mac_addr_generic - Read device MAC address
2136 * @hw: pointer to the HW structure
2137 *
2138 * Reads the device MAC address from the EEPROM and stores the value.
2139 * Since devices with two ports use the same EEPROM, we increment the
2140 * last bit in the MAC address for the second port.
2141 **/
2142 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
2143 {
2144 u32 rar_high;
2145 u32 rar_low;
2146 u16 i;
2147
2148 rar_high = er32(RAH(0));
2149 rar_low = er32(RAL(0));
2150
2151 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
2152 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
2153
2154 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
2155 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
2156
2157 for (i = 0; i < ETH_ALEN; i++)
2158 hw->mac.addr[i] = hw->mac.perm_addr[i];
2159
2160 return 0;
2161 }
2162
2163 /**
2164 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2165 * @hw: pointer to the HW structure
2166 *
2167 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2168 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2169 **/
2170 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2171 {
2172 s32 ret_val;
2173 u16 checksum = 0;
2174 u16 i, nvm_data;
2175
2176 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2177 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2178 if (ret_val) {
2179 e_dbg("NVM Read Error\n");
2180 return ret_val;
2181 }
2182 checksum += nvm_data;
2183 }
2184
2185 if (checksum != (u16) NVM_SUM) {
2186 e_dbg("NVM Checksum Invalid\n");
2187 return -E1000_ERR_NVM;
2188 }
2189
2190 return 0;
2191 }
2192
2193 /**
2194 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2195 * @hw: pointer to the HW structure
2196 *
2197 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2198 * up to the checksum. Then calculates the EEPROM checksum and writes the
2199 * value to the EEPROM.
2200 **/
2201 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2202 {
2203 s32 ret_val;
2204 u16 checksum = 0;
2205 u16 i, nvm_data;
2206
2207 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2208 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2209 if (ret_val) {
2210 e_dbg("NVM Read Error while updating checksum.\n");
2211 return ret_val;
2212 }
2213 checksum += nvm_data;
2214 }
2215 checksum = (u16) NVM_SUM - checksum;
2216 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2217 if (ret_val)
2218 e_dbg("NVM Write Error while updating checksum.\n");
2219
2220 return ret_val;
2221 }
2222
2223 /**
2224 * e1000e_reload_nvm - Reloads EEPROM
2225 * @hw: pointer to the HW structure
2226 *
2227 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2228 * extended control register.
2229 **/
2230 void e1000e_reload_nvm(struct e1000_hw *hw)
2231 {
2232 u32 ctrl_ext;
2233
2234 udelay(10);
2235 ctrl_ext = er32(CTRL_EXT);
2236 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2237 ew32(CTRL_EXT, ctrl_ext);
2238 e1e_flush();
2239 }
2240
2241 /**
2242 * e1000_calculate_checksum - Calculate checksum for buffer
2243 * @buffer: pointer to EEPROM
2244 * @length: size of EEPROM to calculate a checksum for
2245 *
2246 * Calculates the checksum for some buffer on a specified length. The
2247 * checksum calculated is returned.
2248 **/
2249 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2250 {
2251 u32 i;
2252 u8 sum = 0;
2253
2254 if (!buffer)
2255 return 0;
2256
2257 for (i = 0; i < length; i++)
2258 sum += buffer[i];
2259
2260 return (u8) (0 - sum);
2261 }
2262
2263 /**
2264 * e1000_mng_enable_host_if - Checks host interface is enabled
2265 * @hw: pointer to the HW structure
2266 *
2267 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2268 *
2269 * This function checks whether the HOST IF is enabled for command operation
2270 * and also checks whether the previous command is completed. It busy waits
2271 * in case of previous command is not completed.
2272 **/
2273 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2274 {
2275 u32 hicr;
2276 u8 i;
2277
2278 /* Check that the host interface is enabled. */
2279 hicr = er32(HICR);
2280 if ((hicr & E1000_HICR_EN) == 0) {
2281 e_dbg("E1000_HOST_EN bit disabled.\n");
2282 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2283 }
2284 /* check the previous command is completed */
2285 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2286 hicr = er32(HICR);
2287 if (!(hicr & E1000_HICR_C))
2288 break;
2289 mdelay(1);
2290 }
2291
2292 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2293 e_dbg("Previous command timeout failed .\n");
2294 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2295 }
2296
2297 return 0;
2298 }
2299
2300 /**
2301 * e1000e_check_mng_mode_generic - check management mode
2302 * @hw: pointer to the HW structure
2303 *
2304 * Reads the firmware semaphore register and returns true (>0) if
2305 * manageability is enabled, else false (0).
2306 **/
2307 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2308 {
2309 u32 fwsm = er32(FWSM);
2310
2311 return (fwsm & E1000_FWSM_MODE_MASK) ==
2312 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2313 }
2314
2315 /**
2316 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2317 * @hw: pointer to the HW structure
2318 *
2319 * Enables packet filtering on transmit packets if manageability is enabled
2320 * and host interface is enabled.
2321 **/
2322 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2323 {
2324 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2325 u32 *buffer = (u32 *)&hw->mng_cookie;
2326 u32 offset;
2327 s32 ret_val, hdr_csum, csum;
2328 u8 i, len;
2329
2330 hw->mac.tx_pkt_filtering = true;
2331
2332 /* No manageability, no filtering */
2333 if (!e1000e_check_mng_mode(hw)) {
2334 hw->mac.tx_pkt_filtering = false;
2335 goto out;
2336 }
2337
2338 /*
2339 * If we can't read from the host interface for whatever
2340 * reason, disable filtering.
2341 */
2342 ret_val = e1000_mng_enable_host_if(hw);
2343 if (ret_val) {
2344 hw->mac.tx_pkt_filtering = false;
2345 goto out;
2346 }
2347
2348 /* Read in the header. Length and offset are in dwords. */
2349 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2350 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2351 for (i = 0; i < len; i++)
2352 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2353 hdr_csum = hdr->checksum;
2354 hdr->checksum = 0;
2355 csum = e1000_calculate_checksum((u8 *)hdr,
2356 E1000_MNG_DHCP_COOKIE_LENGTH);
2357 /*
2358 * If either the checksums or signature don't match, then
2359 * the cookie area isn't considered valid, in which case we
2360 * take the safe route of assuming Tx filtering is enabled.
2361 */
2362 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2363 hw->mac.tx_pkt_filtering = true;
2364 goto out;
2365 }
2366
2367 /* Cookie area is valid, make the final check for filtering. */
2368 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2369 hw->mac.tx_pkt_filtering = false;
2370 goto out;
2371 }
2372
2373 out:
2374 return hw->mac.tx_pkt_filtering;
2375 }
2376
2377 /**
2378 * e1000_mng_write_cmd_header - Writes manageability command header
2379 * @hw: pointer to the HW structure
2380 * @hdr: pointer to the host interface command header
2381 *
2382 * Writes the command header after does the checksum calculation.
2383 **/
2384 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2385 struct e1000_host_mng_command_header *hdr)
2386 {
2387 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2388
2389 /* Write the whole command header structure with new checksum. */
2390
2391 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2392
2393 length >>= 2;
2394 /* Write the relevant command block into the ram area. */
2395 for (i = 0; i < length; i++) {
2396 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2397 *((u32 *) hdr + i));
2398 e1e_flush();
2399 }
2400
2401 return 0;
2402 }
2403
2404 /**
2405 * e1000_mng_host_if_write - Write to the manageability host interface
2406 * @hw: pointer to the HW structure
2407 * @buffer: pointer to the host interface buffer
2408 * @length: size of the buffer
2409 * @offset: location in the buffer to write to
2410 * @sum: sum of the data (not checksum)
2411 *
2412 * This function writes the buffer content at the offset given on the host if.
2413 * It also does alignment considerations to do the writes in most efficient
2414 * way. Also fills up the sum of the buffer in *buffer parameter.
2415 **/
2416 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2417 u16 length, u16 offset, u8 *sum)
2418 {
2419 u8 *tmp;
2420 u8 *bufptr = buffer;
2421 u32 data = 0;
2422 u16 remaining, i, j, prev_bytes;
2423
2424 /* sum = only sum of the data and it is not checksum */
2425
2426 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2427 return -E1000_ERR_PARAM;
2428
2429 tmp = (u8 *)&data;
2430 prev_bytes = offset & 0x3;
2431 offset >>= 2;
2432
2433 if (prev_bytes) {
2434 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2435 for (j = prev_bytes; j < sizeof(u32); j++) {
2436 *(tmp + j) = *bufptr++;
2437 *sum += *(tmp + j);
2438 }
2439 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2440 length -= j - prev_bytes;
2441 offset++;
2442 }
2443
2444 remaining = length & 0x3;
2445 length -= remaining;
2446
2447 /* Calculate length in DWORDs */
2448 length >>= 2;
2449
2450 /*
2451 * The device driver writes the relevant command block into the
2452 * ram area.
2453 */
2454 for (i = 0; i < length; i++) {
2455 for (j = 0; j < sizeof(u32); j++) {
2456 *(tmp + j) = *bufptr++;
2457 *sum += *(tmp + j);
2458 }
2459
2460 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2461 }
2462 if (remaining) {
2463 for (j = 0; j < sizeof(u32); j++) {
2464 if (j < remaining)
2465 *(tmp + j) = *bufptr++;
2466 else
2467 *(tmp + j) = 0;
2468
2469 *sum += *(tmp + j);
2470 }
2471 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2472 }
2473
2474 return 0;
2475 }
2476
2477 /**
2478 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2479 * @hw: pointer to the HW structure
2480 * @buffer: pointer to the host interface
2481 * @length: size of the buffer
2482 *
2483 * Writes the DHCP information to the host interface.
2484 **/
2485 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2486 {
2487 struct e1000_host_mng_command_header hdr;
2488 s32 ret_val;
2489 u32 hicr;
2490
2491 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2492 hdr.command_length = length;
2493 hdr.reserved1 = 0;
2494 hdr.reserved2 = 0;
2495 hdr.checksum = 0;
2496
2497 /* Enable the host interface */
2498 ret_val = e1000_mng_enable_host_if(hw);
2499 if (ret_val)
2500 return ret_val;
2501
2502 /* Populate the host interface with the contents of "buffer". */
2503 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2504 sizeof(hdr), &(hdr.checksum));
2505 if (ret_val)
2506 return ret_val;
2507
2508 /* Write the manageability command header */
2509 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2510 if (ret_val)
2511 return ret_val;
2512
2513 /* Tell the ARC a new command is pending. */
2514 hicr = er32(HICR);
2515 ew32(HICR, hicr | E1000_HICR_C);
2516
2517 return 0;
2518 }
2519
2520 /**
2521 * e1000e_enable_mng_pass_thru - Enable processing of ARP's
2522 * @hw: pointer to the HW structure
2523 *
2524 * Verifies the hardware needs to allow ARPs to be processed by the host.
2525 **/
2526 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2527 {
2528 u32 manc;
2529 u32 fwsm, factps;
2530 bool ret_val = false;
2531
2532 manc = er32(MANC);
2533
2534 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
2535 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
2536 return ret_val;
2537
2538 if (hw->mac.arc_subsystem_valid) {
2539 fwsm = er32(FWSM);
2540 factps = er32(FACTPS);
2541
2542 if (!(factps & E1000_FACTPS_MNGCG) &&
2543 ((fwsm & E1000_FWSM_MODE_MASK) ==
2544 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2545 ret_val = true;
2546 return ret_val;
2547 }
2548 } else {
2549 if ((manc & E1000_MANC_SMBUS_EN) &&
2550 !(manc & E1000_MANC_ASF_EN)) {
2551 ret_val = true;
2552 return ret_val;
2553 }
2554 }
2555
2556 return ret_val;
2557 }
2558
2559 s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
2560 {
2561 s32 ret_val;
2562 u16 nvm_data;
2563
2564 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2565 if (ret_val) {
2566 e_dbg("NVM Read Error\n");
2567 return ret_val;
2568 }
2569 *pba_num = (u32)(nvm_data << 16);
2570
2571 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
2572 if (ret_val) {
2573 e_dbg("NVM Read Error\n");
2574 return ret_val;
2575 }
2576 *pba_num |= nvm_data;
2577
2578 return 0;
2579 }
Linux with added FPC-III support