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Staging: netwave: delete the driver
[linux/fpc-iii.git] / drivers / net / qlcnic / qlcnic.h
blob0da94b208db17ca008ccdecd4e80f3c850d1caf9
1 /*
2 * Copyright (C) 2009 - QLogic Corporation.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
22 *
23 */
24
25 #ifndef _QLCNIC_H_
26 #define _QLCNIC_H_
27
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/types.h>
31 #include <linux/ioport.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ip.h>
36 #include <linux/in.h>
37 #include <linux/tcp.h>
38 #include <linux/skbuff.h>
39 #include <linux/firmware.h>
40
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/timer.h>
44
45 #include <linux/vmalloc.h>
46
47 #include <linux/io.h>
48 #include <asm/byteorder.h>
49
50 #include "qlcnic_hdr.h"
51
52 #define _QLCNIC_LINUX_MAJOR 5
53 #define _QLCNIC_LINUX_MINOR 0
54 #define _QLCNIC_LINUX_SUBVERSION 0
55 #define QLCNIC_LINUX_VERSIONID "5.0.0"
56
57 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
58 #define _major(v) (((v) >> 24) & 0xff)
59 #define _minor(v) (((v) >> 16) & 0xff)
60 #define _build(v) ((v) & 0xffff)
61
62 /* version in image has weird encoding:
63 * 7:0 - major
64 * 15:8 - minor
65 * 31:16 - build (little endian)
66 */
67 #define QLCNIC_DECODE_VERSION(v) \
68 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
69
70 #define QLCNIC_NUM_FLASH_SECTORS (64)
71 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
72 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
73 * QLCNIC_FLASH_SECTOR_SIZE)
74
75 #define RCV_DESC_RINGSIZE(rds_ring) \
76 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
77 #define RCV_BUFF_RINGSIZE(rds_ring) \
78 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
79 #define STATUS_DESC_RINGSIZE(sds_ring) \
80 (sizeof(struct status_desc) * (sds_ring)->num_desc)
81 #define TX_BUFF_RINGSIZE(tx_ring) \
82 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
83 #define TX_DESC_RINGSIZE(tx_ring) \
84 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
85
86 #define QLCNIC_P3P_A0 0x50
87
88 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
89
90 #define FIRST_PAGE_GROUP_START 0
91 #define FIRST_PAGE_GROUP_END 0x100000
92
93 #define P3_MAX_MTU (9600)
94 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
95
96 #define QLCNIC_P3_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
97 #define QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3_MAX_MTU)
98 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
99 #define QLCNIC_LRO_BUFFER_EXTRA 2048
100
101 #define QLCNIC_RX_LRO_BUFFER_LENGTH (8060)
102
103 /* Opcodes to be used with the commands */
104 #define TX_ETHER_PKT 0x01
105 #define TX_TCP_PKT 0x02
106 #define TX_UDP_PKT 0x03
107 #define TX_IP_PKT 0x04
108 #define TX_TCP_LSO 0x05
109 #define TX_TCP_LSO6 0x06
110 #define TX_IPSEC 0x07
111 #define TX_IPSEC_CMD 0x0a
112 #define TX_TCPV6_PKT 0x0b
113 #define TX_UDPV6_PKT 0x0c
114
115 /* Tx defines */
116 #define MAX_BUFFERS_PER_CMD 32
117 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4)
118 #define QLCNIC_MAX_TX_TIMEOUTS 2
119
120 /*
121 * Following are the states of the Phantom. Phantom will set them and
122 * Host will read to check if the fields are correct.
123 */
124 #define PHAN_INITIALIZE_FAILED 0xffff
125 #define PHAN_INITIALIZE_COMPLETE 0xff01
126
127 /* Host writes the following to notify that it has done the init-handshake */
128 #define PHAN_INITIALIZE_ACK 0xf00f
129 #define PHAN_PEG_RCV_INITIALIZED 0xff01
130
131 #define NUM_RCV_DESC_RINGS 3
132 #define NUM_STS_DESC_RINGS 4
133
134 #define RCV_RING_NORMAL 0
135 #define RCV_RING_JUMBO 1
136 #define RCV_RING_LRO 2
137
138 #define MIN_CMD_DESCRIPTORS 64
139 #define MIN_RCV_DESCRIPTORS 64
140 #define MIN_JUMBO_DESCRIPTORS 32
141
142 #define MAX_CMD_DESCRIPTORS 1024
143 #define MAX_RCV_DESCRIPTORS_1G 4096
144 #define MAX_RCV_DESCRIPTORS_10G 8192
145 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
146 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
147 #define MAX_LRO_RCV_DESCRIPTORS 8
148
149 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
150 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
151
152 #define get_next_index(index, length) \
153 (((index) + 1) & ((length) - 1))
154
155 #define MPORT_MULTI_FUNCTION_MODE 0x2222
156
157 /*
158 * Following data structures describe the descriptors that will be used.
159 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
160 * we are doing LSO (above the 1500 size packet) only.
161 */
162
163 #define FLAGS_VLAN_TAGGED 0x10
164 #define FLAGS_VLAN_OOB 0x40
165
166 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
167 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
168 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
169 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
170 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
171 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
172
173 #define qlcnic_set_tx_port(_desc, _port) \
174 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
175
176 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
177 ((_desc)->flags_opcode = \
178 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
179
180 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
181 ((_desc)->nfrags__length = \
182 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
183
184 struct cmd_desc_type0 {
185 u8 tcp_hdr_offset; /* For LSO only */
186 u8 ip_hdr_offset; /* For LSO only */
187 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
188 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
189
190 __le64 addr_buffer2;
191
192 __le16 reference_handle;
193 __le16 mss;
194 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
195 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
196 __le16 conn_id; /* IPSec offoad only */
197
198 __le64 addr_buffer3;
199 __le64 addr_buffer1;
200
201 __le16 buffer_length[4];
202
203 __le64 addr_buffer4;
204
205 __le32 reserved2;
206 __le16 reserved;
207 __le16 vlan_TCI;
208
209 } __attribute__ ((aligned(64)));
210
211 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
212 struct rcv_desc {
213 __le16 reference_handle;
214 __le16 reserved;
215 __le32 buffer_length; /* allocated buffer length (usually 2K) */
216 __le64 addr_buffer;
217 };
218
219 /* opcode field in status_desc */
220 #define QLCNIC_SYN_OFFLOAD 0x03
221 #define QLCNIC_RXPKT_DESC 0x04
222 #define QLCNIC_OLD_RXPKT_DESC 0x3f
223 #define QLCNIC_RESPONSE_DESC 0x05
224 #define QLCNIC_LRO_DESC 0x12
225
226 /* for status field in status_desc */
227 #define STATUS_CKSUM_OK (2)
228
229 /* owner bits of status_desc */
230 #define STATUS_OWNER_HOST (0x1ULL << 56)
231 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
232
233 /* Status descriptor:
234 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
235 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
236 53-55 desc_cnt, 56-57 owner, 58-63 opcode
237 */
238 #define qlcnic_get_sts_port(sts_data) \
239 ((sts_data) & 0x0F)
240 #define qlcnic_get_sts_status(sts_data) \
241 (((sts_data) >> 4) & 0x0F)
242 #define qlcnic_get_sts_type(sts_data) \
243 (((sts_data) >> 8) & 0x0F)
244 #define qlcnic_get_sts_totallength(sts_data) \
245 (((sts_data) >> 12) & 0xFFFF)
246 #define qlcnic_get_sts_refhandle(sts_data) \
247 (((sts_data) >> 28) & 0xFFFF)
248 #define qlcnic_get_sts_prot(sts_data) \
249 (((sts_data) >> 44) & 0x0F)
250 #define qlcnic_get_sts_pkt_offset(sts_data) \
251 (((sts_data) >> 48) & 0x1F)
252 #define qlcnic_get_sts_desc_cnt(sts_data) \
253 (((sts_data) >> 53) & 0x7)
254 #define qlcnic_get_sts_opcode(sts_data) \
255 (((sts_data) >> 58) & 0x03F)
256
257 #define qlcnic_get_lro_sts_refhandle(sts_data) \
258 ((sts_data) & 0x0FFFF)
259 #define qlcnic_get_lro_sts_length(sts_data) \
260 (((sts_data) >> 16) & 0x0FFFF)
261 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
262 (((sts_data) >> 32) & 0x0FF)
263 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
264 (((sts_data) >> 40) & 0x0FF)
265 #define qlcnic_get_lro_sts_timestamp(sts_data) \
266 (((sts_data) >> 48) & 0x1)
267 #define qlcnic_get_lro_sts_type(sts_data) \
268 (((sts_data) >> 49) & 0x7)
269 #define qlcnic_get_lro_sts_push_flag(sts_data) \
270 (((sts_data) >> 52) & 0x1)
271 #define qlcnic_get_lro_sts_seq_number(sts_data) \
272 ((sts_data) & 0x0FFFFFFFF)
273
274
275 struct status_desc {
276 __le64 status_desc_data[2];
277 } __attribute__ ((aligned(16)));
278
279 /* UNIFIED ROMIMAGE */
280 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
281 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
282 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
283 #define QLCNIC_UNI_DIR_SECT_FW 0x7
284
285 /*Offsets */
286 #define QLCNIC_UNI_CHIP_REV_OFF 10
287 #define QLCNIC_UNI_FLAGS_OFF 11
288 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
289 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
290 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
291
292 struct uni_table_desc{
293 u32 findex;
294 u32 num_entries;
295 u32 entry_size;
296 u32 reserved[5];
297 };
298
299 struct uni_data_desc{
300 u32 findex;
301 u32 size;
302 u32 reserved[5];
303 };
304
305 /* Magic number to let user know flash is programmed */
306 #define QLCNIC_BDINFO_MAGIC 0x12345678
307
308 #define QLCNIC_BRDTYPE_P3_REF_QG 0x0021
309 #define QLCNIC_BRDTYPE_P3_HMEZ 0x0022
310 #define QLCNIC_BRDTYPE_P3_10G_CX4_LP 0x0023
311 #define QLCNIC_BRDTYPE_P3_4_GB 0x0024
312 #define QLCNIC_BRDTYPE_P3_IMEZ 0x0025
313 #define QLCNIC_BRDTYPE_P3_10G_SFP_PLUS 0x0026
314 #define QLCNIC_BRDTYPE_P3_10000_BASE_T 0x0027
315 #define QLCNIC_BRDTYPE_P3_XG_LOM 0x0028
316 #define QLCNIC_BRDTYPE_P3_4_GB_MM 0x0029
317 #define QLCNIC_BRDTYPE_P3_10G_SFP_CT 0x002a
318 #define QLCNIC_BRDTYPE_P3_10G_SFP_QT 0x002b
319 #define QLCNIC_BRDTYPE_P3_10G_CX4 0x0031
320 #define QLCNIC_BRDTYPE_P3_10G_XFP 0x0032
321 #define QLCNIC_BRDTYPE_P3_10G_TP 0x0080
322
323 /* Flash memory map */
324 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
325 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
326 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
327 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
328
329 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
330 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
331 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
332 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
333
334 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
335 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
336
337 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
338 #define QLCNIC_UNIFIED_ROMIMAGE 0
339 #define QLCNIC_FLASH_ROMIMAGE 1
340 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
341
342 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
343 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
344
345 extern char qlcnic_driver_name[];
346
347 /* Number of status descriptors to handle per interrupt */
348 #define MAX_STATUS_HANDLE (64)
349
350 /*
351 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
352 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
353 */
354 struct qlcnic_skb_frag {
355 u64 dma;
356 u64 length;
357 };
358
359 struct qlcnic_recv_crb {
360 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
361 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
362 u32 sw_int_mask[NUM_STS_DESC_RINGS];
363 };
364
365 /* Following defines are for the state of the buffers */
366 #define QLCNIC_BUFFER_FREE 0
367 #define QLCNIC_BUFFER_BUSY 1
368
369 /*
370 * There will be one qlcnic_buffer per skb packet. These will be
371 * used to save the dma info for pci_unmap_page()
372 */
373 struct qlcnic_cmd_buffer {
374 struct sk_buff *skb;
375 struct qlcnic_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
376 u32 frag_count;
377 };
378
379 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
380 struct qlcnic_rx_buffer {
381 struct list_head list;
382 struct sk_buff *skb;
383 u64 dma;
384 u16 ref_handle;
385 u16 state;
386 };
387
388 /* Board types */
389 #define QLCNIC_GBE 0x01
390 #define QLCNIC_XGBE 0x02
391
392 /*
393 * One hardware_context{} per adapter
394 * contains interrupt info as well shared hardware info.
395 */
396 struct qlcnic_hardware_context {
397 void __iomem *pci_base0;
398 void __iomem *ocm_win_crb;
399
400 unsigned long pci_len0;
401
402 u32 ocm_win;
403 u32 crb_win;
404
405 rwlock_t crb_lock;
406 struct mutex mem_lock;
407
408 u8 cut_through;
409 u8 revision_id;
410 u8 pci_func;
411 u8 linkup;
412 u16 port_type;
413 u16 board_type;
414 };
415
416 struct qlcnic_adapter_stats {
417 u64 xmitcalled;
418 u64 xmitfinished;
419 u64 rxdropped;
420 u64 txdropped;
421 u64 csummed;
422 u64 rx_pkts;
423 u64 lro_pkts;
424 u64 rxbytes;
425 u64 txbytes;
426 u64 lrobytes;
427 u64 lso_frames;
428 u64 xmit_on;
429 u64 xmit_off;
430 u64 skb_alloc_failure;
431 };
432
433 /*
434 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
435 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
436 */
437 struct qlcnic_host_rds_ring {
438 u32 producer;
439 u32 num_desc;
440 u32 dma_size;
441 u32 skb_size;
442 u32 flags;
443 void __iomem *crb_rcv_producer;
444 struct rcv_desc *desc_head;
445 struct qlcnic_rx_buffer *rx_buf_arr;
446 struct list_head free_list;
447 spinlock_t lock;
448 dma_addr_t phys_addr;
449 };
450
451 struct qlcnic_host_sds_ring {
452 u32 consumer;
453 u32 num_desc;
454 void __iomem *crb_sts_consumer;
455 void __iomem *crb_intr_mask;
456
457 struct status_desc *desc_head;
458 struct qlcnic_adapter *adapter;
459 struct napi_struct napi;
460 struct list_head free_list[NUM_RCV_DESC_RINGS];
461
462 int irq;
463
464 dma_addr_t phys_addr;
465 char name[IFNAMSIZ+4];
466 };
467
468 struct qlcnic_host_tx_ring {
469 u32 producer;
470 __le32 *hw_consumer;
471 u32 sw_consumer;
472 void __iomem *crb_cmd_producer;
473 u32 num_desc;
474
475 struct netdev_queue *txq;
476
477 struct qlcnic_cmd_buffer *cmd_buf_arr;
478 struct cmd_desc_type0 *desc_head;
479 dma_addr_t phys_addr;
480 dma_addr_t hw_cons_phys_addr;
481 };
482
483 /*
484 * Receive context. There is one such structure per instance of the
485 * receive processing. Any state information that is relevant to
486 * the receive, and is must be in this structure. The global data may be
487 * present elsewhere.
488 */
489 struct qlcnic_recv_context {
490 u32 state;
491 u16 context_id;
492 u16 virt_port;
493
494 struct qlcnic_host_rds_ring *rds_rings;
495 struct qlcnic_host_sds_ring *sds_rings;
496 };
497
498 /* HW context creation */
499
500 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
501 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
502 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
503
504 #define QLCNIC_CDRP_CMD_BIT 0x80000000
505
506 /*
507 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
508 * in the crb QLCNIC_CDRP_CRB_OFFSET.
509 */
510 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
511 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
512
513 #define QLCNIC_CDRP_RSP_OK 0x00000001
514 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
515 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
516
517 /*
518 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
519 * the crb QLCNIC_CDRP_CRB_OFFSET.
520 */
521 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
522 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
523
524 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
525 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
526 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
527 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
528 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
529 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
530 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
531 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
532 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
533 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
534 #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
535 #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
536 #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
537 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
538 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
539 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
540 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
541 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
542 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
543 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
544 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
545 #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
546 #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
547 #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
548 #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
549 #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
550 #define QLCNIC_CDRP_CMD_MAX 0x0000001f
551
552 #define QLCNIC_RCODE_SUCCESS 0
553 #define QLCNIC_RCODE_TIMEOUT 17
554 #define QLCNIC_DESTROY_CTX_RESET 0
555
556 /*
557 * Capabilities Announced
558 */
559 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
560 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
561 #define QLCNIC_CAP0_LSO (1 << 6)
562 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
563 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
564
565 /*
566 * Context state
567 */
568 #define QLCHAL_VERSION 1
569
570 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
571
572 /*
573 * Rx context
574 */
575
576 struct qlcnic_hostrq_sds_ring {
577 __le64 host_phys_addr; /* Ring base addr */
578 __le32 ring_size; /* Ring entries */
579 __le16 msi_index;
580 __le16 rsvd; /* Padding */
581 };
582
583 struct qlcnic_hostrq_rds_ring {
584 __le64 host_phys_addr; /* Ring base addr */
585 __le64 buff_size; /* Packet buffer size */
586 __le32 ring_size; /* Ring entries */
587 __le32 ring_kind; /* Class of ring */
588 };
589
590 struct qlcnic_hostrq_rx_ctx {
591 __le64 host_rsp_dma_addr; /* Response dma'd here */
592 __le32 capabilities[4]; /* Flag bit vector */
593 __le32 host_int_crb_mode; /* Interrupt crb usage */
594 __le32 host_rds_crb_mode; /* RDS crb usage */
595 /* These ring offsets are relative to data[0] below */
596 __le32 rds_ring_offset; /* Offset to RDS config */
597 __le32 sds_ring_offset; /* Offset to SDS config */
598 __le16 num_rds_rings; /* Count of RDS rings */
599 __le16 num_sds_rings; /* Count of SDS rings */
600 __le16 rsvd1; /* Padding */
601 __le16 rsvd2; /* Padding */
602 u8 reserved[128]; /* reserve space for future expansion*/
603 /* MUST BE 64-bit aligned.
604 The following is packed:
605 - N hostrq_rds_rings
606 - N hostrq_sds_rings */
607 char data[0];
608 };
609
610 struct qlcnic_cardrsp_rds_ring{
611 __le32 host_producer_crb; /* Crb to use */
612 __le32 rsvd1; /* Padding */
613 };
614
615 struct qlcnic_cardrsp_sds_ring {
616 __le32 host_consumer_crb; /* Crb to use */
617 __le32 interrupt_crb; /* Crb to use */
618 };
619
620 struct qlcnic_cardrsp_rx_ctx {
621 /* These ring offsets are relative to data[0] below */
622 __le32 rds_ring_offset; /* Offset to RDS config */
623 __le32 sds_ring_offset; /* Offset to SDS config */
624 __le32 host_ctx_state; /* Starting State */
625 __le32 num_fn_per_port; /* How many PCI fn share the port */
626 __le16 num_rds_rings; /* Count of RDS rings */
627 __le16 num_sds_rings; /* Count of SDS rings */
628 __le16 context_id; /* Handle for context */
629 u8 phys_port; /* Physical id of port */
630 u8 virt_port; /* Virtual/Logical id of port */
631 u8 reserved[128]; /* save space for future expansion */
632 /* MUST BE 64-bit aligned.
633 The following is packed:
634 - N cardrsp_rds_rings
635 - N cardrs_sds_rings */
636 char data[0];
637 };
638
639 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
640 (sizeof(HOSTRQ_RX) + \
641 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
642 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
643
644 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
645 (sizeof(CARDRSP_RX) + \
646 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
647 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
648
649 /*
650 * Tx context
651 */
652
653 struct qlcnic_hostrq_cds_ring {
654 __le64 host_phys_addr; /* Ring base addr */
655 __le32 ring_size; /* Ring entries */
656 __le32 rsvd; /* Padding */
657 };
658
659 struct qlcnic_hostrq_tx_ctx {
660 __le64 host_rsp_dma_addr; /* Response dma'd here */
661 __le64 cmd_cons_dma_addr; /* */
662 __le64 dummy_dma_addr; /* */
663 __le32 capabilities[4]; /* Flag bit vector */
664 __le32 host_int_crb_mode; /* Interrupt crb usage */
665 __le32 rsvd1; /* Padding */
666 __le16 rsvd2; /* Padding */
667 __le16 interrupt_ctl;
668 __le16 msi_index;
669 __le16 rsvd3; /* Padding */
670 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
671 u8 reserved[128]; /* future expansion */
672 };
673
674 struct qlcnic_cardrsp_cds_ring {
675 __le32 host_producer_crb; /* Crb to use */
676 __le32 interrupt_crb; /* Crb to use */
677 };
678
679 struct qlcnic_cardrsp_tx_ctx {
680 __le32 host_ctx_state; /* Starting state */
681 __le16 context_id; /* Handle for context */
682 u8 phys_port; /* Physical id of port */
683 u8 virt_port; /* Virtual/Logical id of port */
684 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
685 u8 reserved[128]; /* future expansion */
686 };
687
688 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
689 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
690
691 /* CRB */
692
693 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
694 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
695 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
696 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
697
698 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
699 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
700 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
701 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
702 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
703
704
705 /* MAC */
706
707 #define MC_COUNT_P3 38
708
709 #define QLCNIC_MAC_NOOP 0
710 #define QLCNIC_MAC_ADD 1
711 #define QLCNIC_MAC_DEL 2
712
713 struct qlcnic_mac_list_s {
714 struct list_head list;
715 uint8_t mac_addr[ETH_ALEN+2];
716 };
717
718 /*
719 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
720 * adjusted based on configured MTU.
721 */
722 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
723 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
724 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
725 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
726
727 #define QLCNIC_INTR_DEFAULT 0x04
728
729 union qlcnic_nic_intr_coalesce_data {
730 struct {
731 u16 rx_packets;
732 u16 rx_time_us;
733 u16 tx_packets;
734 u16 tx_time_us;
735 } data;
736 u64 word;
737 };
738
739 struct qlcnic_nic_intr_coalesce {
740 u16 stats_time_us;
741 u16 rate_sample_time;
742 u16 flags;
743 u16 rsvd_1;
744 u32 low_threshold;
745 u32 high_threshold;
746 union qlcnic_nic_intr_coalesce_data normal;
747 union qlcnic_nic_intr_coalesce_data low;
748 union qlcnic_nic_intr_coalesce_data high;
749 union qlcnic_nic_intr_coalesce_data irq;
750 };
751
752 #define QLCNIC_HOST_REQUEST 0x13
753 #define QLCNIC_REQUEST 0x14
754
755 #define QLCNIC_MAC_EVENT 0x1
756
757 #define QLCNIC_IP_UP 2
758 #define QLCNIC_IP_DOWN 3
759
760 /*
761 * Driver --> Firmware
762 */
763 #define QLCNIC_H2C_OPCODE_START 0
764 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1
765 #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2
766 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
767 #define QLCNIC_H2C_OPCODE_CONFIG_LED 4
768 #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
769 #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6
770 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7
771 #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8
772 #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
773 #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
774 #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
775 #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
776 #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
777 #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
778 #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
779 #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
780 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
781 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
782 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 19
783 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
784 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
785 #define QLCNIC_C2C_OPCODE 22
786 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
787 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
788 #define QLCNIC_H2C_OPCODE_LAST 25
789 /*
790 * Firmware --> Driver
791 */
792
793 #define QLCNIC_C2H_OPCODE_START 128
794 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
795 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
796 #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
797 #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
798 #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
799 #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
800 #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
801 #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
802 #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
803 #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
804 #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
805 #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
806 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
807 #define QLCNIC_C2H_OPCODE_LAST 142
808
809 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
810 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
811 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
812
813 #define QLCNIC_LRO_REQUEST_CLEANUP 4
814
815 /* Capabilites received */
816 #define QLCNIC_FW_CAPABILITY_BDG (1 << 8)
817 #define QLCNIC_FW_CAPABILITY_FVLANTX (1 << 9)
818 #define QLCNIC_FW_CAPABILITY_HW_LRO (1 << 10)
819
820 /* module types */
821 #define LINKEVENT_MODULE_NOT_PRESENT 1
822 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
823 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
824 #define LINKEVENT_MODULE_OPTICAL_LRM 4
825 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
826 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
827 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
828 #define LINKEVENT_MODULE_TWINAX 8
829
830 #define LINKSPEED_10GBPS 10000
831 #define LINKSPEED_1GBPS 1000
832 #define LINKSPEED_100MBPS 100
833 #define LINKSPEED_10MBPS 10
834
835 #define LINKSPEED_ENCODED_10MBPS 0
836 #define LINKSPEED_ENCODED_100MBPS 1
837 #define LINKSPEED_ENCODED_1GBPS 2
838
839 #define LINKEVENT_AUTONEG_DISABLED 0
840 #define LINKEVENT_AUTONEG_ENABLED 1
841
842 #define LINKEVENT_HALF_DUPLEX 0
843 #define LINKEVENT_FULL_DUPLEX 1
844
845 #define LINKEVENT_LINKSPEED_MBPS 0
846 #define LINKEVENT_LINKSPEED_ENCODED 1
847
848 #define AUTO_FW_RESET_ENABLED 0x01
849 /* firmware response header:
850 * 63:58 - message type
851 * 57:56 - owner
852 * 55:53 - desc count
853 * 52:48 - reserved
854 * 47:40 - completion id
855 * 39:32 - opcode
856 * 31:16 - error code
857 * 15:00 - reserved
858 */
859 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
860 ((msg_hdr >> 32) & 0xFF)
861
862 struct qlcnic_fw_msg {
863 union {
864 struct {
865 u64 hdr;
866 u64 body[7];
867 };
868 u64 words[8];
869 };
870 };
871
872 struct qlcnic_nic_req {
873 __le64 qhdr;
874 __le64 req_hdr;
875 __le64 words[6];
876 };
877
878 struct qlcnic_mac_req {
879 u8 op;
880 u8 tag;
881 u8 mac_addr[6];
882 };
883
884 #define QLCNIC_MSI_ENABLED 0x02
885 #define QLCNIC_MSIX_ENABLED 0x04
886 #define QLCNIC_LRO_ENABLED 0x08
887 #define QLCNIC_BRIDGE_ENABLED 0X10
888 #define QLCNIC_DIAG_ENABLED 0x20
889 #define QLCNIC_IS_MSI_FAMILY(adapter) \
890 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
891
892 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
893 #define QLCNIC_MSIX_TBL_SPACE 8192
894 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
895
896 #define QLCNIC_NETDEV_WEIGHT 128
897 #define QLCNIC_ADAPTER_UP_MAGIC 777
898
899 #define __QLCNIC_FW_ATTACHED 0
900 #define __QLCNIC_DEV_UP 1
901 #define __QLCNIC_RESETTING 2
902 #define __QLCNIC_START_FW 4
903
904 #define QLCNIC_INTERRUPT_TEST 1
905 #define QLCNIC_LOOPBACK_TEST 2
906
907 struct qlcnic_adapter {
908 struct qlcnic_hardware_context ahw;
909
910 struct net_device *netdev;
911 struct pci_dev *pdev;
912 struct list_head mac_list;
913
914 spinlock_t tx_clean_lock;
915
916 u16 num_txd;
917 u16 num_rxd;
918 u16 num_jumbo_rxd;
919 u16 num_lro_rxd;
920
921 u8 max_rds_rings;
922 u8 max_sds_rings;
923 u8 driver_mismatch;
924 u8 msix_supported;
925 u8 rx_csum;
926 u8 pci_using_dac;
927 u8 portnum;
928 u8 physical_port;
929
930 u8 mc_enabled;
931 u8 max_mc_count;
932 u8 rss_supported;
933 u8 rsrvd1;
934 u8 fw_wait_cnt;
935 u8 fw_fail_cnt;
936 u8 tx_timeo_cnt;
937 u8 need_fw_reset;
938
939 u8 has_link_events;
940 u8 fw_type;
941 u16 tx_context_id;
942 u16 mtu;
943 u16 is_up;
944
945 u16 link_speed;
946 u16 link_duplex;
947 u16 link_autoneg;
948 u16 module_type;
949
950 u32 capabilities;
951 u32 flags;
952 u32 irq;
953 u32 temp;
954
955 u32 int_vec_bit;
956 u32 heartbit;
957
958 u8 dev_state;
959 u8 diag_test;
960 u8 diag_cnt;
961 u8 rsrd1;
962 u16 rsrd2;
963
964 u8 mac_addr[ETH_ALEN];
965
966 struct qlcnic_adapter_stats stats;
967
968 struct qlcnic_recv_context recv_ctx;
969 struct qlcnic_host_tx_ring *tx_ring;
970
971 void __iomem *tgt_mask_reg;
972 void __iomem *tgt_status_reg;
973 void __iomem *crb_int_state_reg;
974 void __iomem *isr_int_vec;
975
976 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
977
978 struct delayed_work fw_work;
979
980 struct work_struct tx_timeout_task;
981
982 struct qlcnic_nic_intr_coalesce coal;
983
984 unsigned long state;
985 __le32 file_prd_off; /*File fw product offset*/
986 u32 fw_version;
987 const struct firmware *fw;
988 };
989
990 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
991 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
992
993 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
994 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
995 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
996 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
997
998 #define QLCRD32(adapter, off) \
999 (qlcnic_hw_read_wx_2M(adapter, off))
1000 #define QLCWR32(adapter, off, val) \
1001 (qlcnic_hw_write_wx_2M(adapter, off, val))
1002
1003 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1004 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1005
1006 #define qlcnic_rom_lock(a) \
1007 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1008 #define qlcnic_rom_unlock(a) \
1009 qlcnic_pcie_sem_unlock((a), 2)
1010 #define qlcnic_phy_lock(a) \
1011 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1012 #define qlcnic_phy_unlock(a) \
1013 qlcnic_pcie_sem_unlock((a), 3)
1014 #define qlcnic_api_lock(a) \
1015 qlcnic_pcie_sem_lock((a), 5, 0)
1016 #define qlcnic_api_unlock(a) \
1017 qlcnic_pcie_sem_unlock((a), 5)
1018 #define qlcnic_sw_lock(a) \
1019 qlcnic_pcie_sem_lock((a), 6, 0)
1020 #define qlcnic_sw_unlock(a) \
1021 qlcnic_pcie_sem_unlock((a), 6)
1022 #define crb_win_lock(a) \
1023 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1024 #define crb_win_unlock(a) \
1025 qlcnic_pcie_sem_unlock((a), 7)
1026
1027 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1028 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1029 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1030
1031 /* Functions from qlcnic_init.c */
1032 int qlcnic_phantom_init(struct qlcnic_adapter *adapter);
1033 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1034 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1035 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1036 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1037 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1038
1039 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1040 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1041 u8 *bytes, size_t size);
1042 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1043 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1044
1045 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1046
1047 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1048 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1049
1050 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1051 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1052
1053 int qlcnic_init_firmware(struct qlcnic_adapter *adapter);
1054 void qlcnic_watchdog_task(struct work_struct *work);
1055 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
1056 struct qlcnic_host_rds_ring *rds_ring);
1057 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1058 void qlcnic_set_multi(struct net_device *netdev);
1059 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1060 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1061 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1062 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1063 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd);
1064 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1065 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1066
1067 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1068 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1069 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1070 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, int enable);
1071 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1072 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1073 struct qlcnic_host_tx_ring *tx_ring);
1074 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u64 *mac);
1075 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter);
1076 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter);
1077
1078 /* Functions from qlcnic_main.c */
1079 int qlcnic_reset_context(struct qlcnic_adapter *);
1080 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1081 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1082 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1083 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1084 int qlcnic_check_loopback_buff(unsigned char *data);
1085 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1086 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1087
1088 /*
1089 * QLOGIC Board information
1090 */
1091
1092 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1093 struct qlcnic_brdinfo {
1094 unsigned short vendor;
1095 unsigned short device;
1096 unsigned short sub_vendor;
1097 unsigned short sub_device;
1098 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1099 };
1100
1101 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1102 {0x1077, 0x8020, 0x1077, 0x203,
1103 "8200 Series Single Port 10GbE Converged Network Adapter "
1104 "(TCP/IP Networking)"},
1105 {0x1077, 0x8020, 0x1077, 0x207,
1106 "8200 Series Dual Port 10GbE Converged Network Adapter "
1107 "(TCP/IP Networking)"},
1108 {0x1077, 0x8020, 0x1077, 0x20b,
1109 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1110 {0x1077, 0x8020, 0x1077, 0x20c,
1111 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1112 {0x1077, 0x8020, 0x1077, 0x20f,
1113 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1114 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1115 };
1116
1117 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1118
1119 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1120 {
1121 smp_mb();
1122 if (tx_ring->producer < tx_ring->sw_consumer)
1123 return tx_ring->sw_consumer - tx_ring->producer;
1124 else
1125 return tx_ring->sw_consumer + tx_ring->num_desc -
1126 tx_ring->producer;
1127 }
1128
1129 extern const struct ethtool_ops qlcnic_ethtool_ops;
1130
1131 #endif /* __QLCNIC_H_ */
Linux with added FPC-III support