arch/arm/mach-prima2/rstc.c

   1 /*
   2  * reset controller for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/mutex.h>
  11 #include <linux/io.h>
  12 #include <linux/delay.h>
  13 #include <linux/device.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16
  17 void __iomem *sirfsoc_rstc_base;
  18 static DEFINE_MUTEX(rstc_lock);
  19
  20 static struct of_device_id rstc_ids[]  = {
  21         { .compatible = "sirf,prima2-rstc" },
  22         { .compatible = "sirf,marco-rstc" },
  23         {},
  24 };
  25
  26 static int __init sirfsoc_of_rstc_init(void)
  27 {
  28         struct device_node *np;
  29
  30         np = of_find_matching_node(NULL, rstc_ids);
  31         if (!np)
  32                 panic("unable to find compatible rstc node in dtb\n");
  33
  34         sirfsoc_rstc_base = of_iomap(np, 0);
  35         if (!sirfsoc_rstc_base)
  36                 panic("unable to map rstc cpu registers\n");
  37
  38         of_node_put(np);
  39
  40         return 0;
  41 }
  42 early_initcall(sirfsoc_of_rstc_init);
  43
  44 int sirfsoc_reset_device(struct device *dev)
  45 {
  46         u32 reset_bit;
  47
  48         if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit))
  49                 return -EINVAL;
  50
  51         mutex_lock(&rstc_lock);
  52
  53         if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) {
  54                 /*
  55                  * Writing 1 to this bit resets corresponding block. Writing 0 to this
  56                  * bit de-asserts reset signal of the corresponding block.
  57                  * datasheet doesn't require explicit delay between the set and clear
  58                  * of reset bit. it could be shorter if tests pass.
  59                  */
  60                 writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
  61                         sirfsoc_rstc_base + (reset_bit / 32) * 4);
  62                 msleep(10);
  63                 writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
  64                         sirfsoc_rstc_base + (reset_bit / 32) * 4);
  65         } else {
  66                 /*
  67                  * For MARCO and POLO
  68                  * Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
  69                  * register de-asserts reset signal of the corresponding block.
  70                  * datasheet doesn't require explicit delay between the set and clear
  71                  * of reset bit. it could be shorter if tests pass.
  72                  */
  73                 writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
  74                 msleep(10);
  75                 writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
  76         }
  77
  78         mutex_unlock(&rstc_lock);
  79
  80         return 0;
  81 }
  82
  83 #define SIRFSOC_SYS_RST_BIT  BIT(31)
  84
  85 void sirfsoc_restart(char mode, const char *cmd)
  86 {
  87         writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
  88 }