1 /* linux/arch/arm/mach-s3c2443/dma.c
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2443 DMA selection
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/serial_core.h>
23 #include <plat/dma-s3c24xx.h>
26 #include <plat/regs-serial.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-dma.h>
29 #include <mach/regs-lcd.h>
30 #include <plat/regs-spi.h>
33 [0] = (x) | DMA_CH_VALID, \
34 [1] = (x) | DMA_CH_VALID, \
35 [2] = (x) | DMA_CH_VALID, \
36 [3] = (x) | DMA_CH_VALID, \
37 [4] = (x) | DMA_CH_VALID, \
38 [5] = (x) | DMA_CH_VALID, \
41 static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings
[] = {
44 .channels
= MAP(S3C2443_DMAREQSEL_XDREQ0
),
48 .channels
= MAP(S3C2443_DMAREQSEL_XDREQ1
),
50 [DMACH_SDI
] = { /* only on S3C2443 */
52 .channels
= MAP(S3C2443_DMAREQSEL_SDI
),
56 .channels
= MAP(S3C2443_DMAREQSEL_SPI0RX
),
60 .channels
= MAP(S3C2443_DMAREQSEL_SPI0TX
),
62 [DMACH_SPI1_RX
] = { /* only on S3C2443/S3C2450 */
64 .channels
= MAP(S3C2443_DMAREQSEL_SPI1RX
),
66 [DMACH_SPI1_TX
] = { /* only on S3C2443/S3C2450 */
68 .channels
= MAP(S3C2443_DMAREQSEL_SPI1TX
),
72 .channels
= MAP(S3C2443_DMAREQSEL_UART0_0
),
76 .channels
= MAP(S3C2443_DMAREQSEL_UART1_0
),
80 .channels
= MAP(S3C2443_DMAREQSEL_UART2_0
),
84 .channels
= MAP(S3C2443_DMAREQSEL_UART3_0
),
86 [DMACH_UART0_SRC2
] = {
88 .channels
= MAP(S3C2443_DMAREQSEL_UART0_1
),
90 [DMACH_UART1_SRC2
] = {
92 .channels
= MAP(S3C2443_DMAREQSEL_UART1_1
),
94 [DMACH_UART2_SRC2
] = {
96 .channels
= MAP(S3C2443_DMAREQSEL_UART2_1
),
98 [DMACH_UART3_SRC2
] = {
100 .channels
= MAP(S3C2443_DMAREQSEL_UART3_1
),
104 .channels
= MAP(S3C2443_DMAREQSEL_TIMER
),
108 .channels
= MAP(S3C2443_DMAREQSEL_I2SRX
),
112 .channels
= MAP(S3C2443_DMAREQSEL_I2STX
),
116 .channels
= MAP(S3C2443_DMAREQSEL_PCMIN
),
120 .channels
= MAP(S3C2443_DMAREQSEL_PCMOUT
),
124 .channels
= MAP(S3C2443_DMAREQSEL_MICIN
),
128 static void s3c2443_dma_select(struct s3c2410_dma_chan
*chan
,
129 struct s3c24xx_dma_map
*map
)
131 writel(map
->channels
[0] | S3C2443_DMAREQSEL_HW
,
132 chan
->regs
+ S3C2443_DMA_DMAREQSEL
);
135 static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel
= {
136 .select
= s3c2443_dma_select
,
138 .map
= s3c2443_dma_mappings
,
139 .map_size
= ARRAY_SIZE(s3c2443_dma_mappings
),
142 static int __init
s3c2443_dma_add(struct device
*dev
,
143 struct subsys_interface
*sif
)
145 s3c24xx_dma_init(6, IRQ_S3C2443_DMA0
, 0x100);
146 return s3c24xx_dma_init_map(&s3c2443_dma_sel
);
149 #ifdef CONFIG_CPU_S3C2416
150 /* S3C2416 DMA contains the same selection table as the S3C2443 */
151 static struct subsys_interface s3c2416_dma_interface
= {
152 .name
= "s3c2416_dma",
153 .subsys
= &s3c2416_subsys
,
154 .add_dev
= s3c2443_dma_add
,
157 static int __init
s3c2416_dma_init(void)
159 return subsys_interface_register(&s3c2416_dma_interface
);
162 arch_initcall(s3c2416_dma_init
);
165 #ifdef CONFIG_CPU_S3C2443
166 static struct subsys_interface s3c2443_dma_interface
= {
167 .name
= "s3c2443_dma",
168 .subsys
= &s3c2443_subsys
,
169 .add_dev
= s3c2443_dma_add
,
172 static int __init
s3c2443_dma_init(void)
174 return subsys_interface_register(&s3c2443_dma_interface
);
177 arch_initcall(s3c2443_dma_init
);