2 * r8a73a4 clock framework support
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/sh_clk.h>
24 #include <linux/clkdev.h>
25 #include <mach/common.h>
27 #define CPG_BASE 0xe6150000
30 #define MPCKCR 0xe6150080
31 #define SMSTPCR2 0xe6150138
32 #define SMSTPCR5 0xe6150144
34 static struct clk_mapping cpg_mapping
= {
39 static struct clk extalr_clk
= {
41 .mapping
= &cpg_mapping
,
44 static struct clk extal1_clk
= {
46 .mapping
= &cpg_mapping
,
49 static struct clk extal2_clk
= {
51 .mapping
= &cpg_mapping
,
54 static struct clk
*main_clks
[] = {
61 MSTP217
, MSTP216
, MSTP207
, MSTP206
, MSTP204
, MSTP203
,
66 static struct clk mstp_clks
[MSTP_NR
] = {
67 [MSTP204
] = SH_CLK_MSTP32(&extal2_clk
, SMSTPCR2
, 4, 0), /* SCIFA0 */
68 [MSTP203
] = SH_CLK_MSTP32(&extal2_clk
, SMSTPCR2
, 3, 0), /* SCIFA1 */
69 [MSTP206
] = SH_CLK_MSTP32(&extal2_clk
, SMSTPCR2
, 6, 0), /* SCIFB0 */
70 [MSTP207
] = SH_CLK_MSTP32(&extal2_clk
, SMSTPCR2
, 7, 0), /* SCIFB1 */
71 [MSTP216
] = SH_CLK_MSTP32(&extal2_clk
, SMSTPCR2
, 16, 0), /* SCIFB2 */
72 [MSTP217
] = SH_CLK_MSTP32(&extal2_clk
, SMSTPCR2
, 17, 0), /* SCIFB3 */
73 [MSTP522
] = SH_CLK_MSTP32(&extal2_clk
, SMSTPCR5
, 22, 0), /* Thermal */
76 static struct clk_lookup lookups
[] = {
77 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks
[MSTP204
]),
78 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks
[MSTP203
]),
79 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks
[MSTP206
]),
80 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks
[MSTP207
]),
81 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks
[MSTP216
]),
82 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks
[MSTP217
]),
83 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks
[MSTP522
]),
86 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks
[MSTP522
]),
89 void __init
r8a73a4_clock_init(void)
91 void __iomem
*cpg_base
, *reg
;
94 /* fix MPCLK to EXTAL2 for now.
95 * this is needed until more detailed clock topology is supported
97 cpg_base
= ioremap_nocache(CPG_BASE
, CPG_LEN
);
99 reg
= cpg_base
+ (MPCKCR
- CPG_BASE
);
100 iowrite32(ioread32(reg
) | 1 << 7 | 0x0c, reg
); /* set CKSEL */
103 for (k
= 0; !ret
&& (k
< ARRAY_SIZE(main_clks
)); k
++)
104 ret
= clk_register(main_clks
[k
]);
107 ret
= sh_clk_mstp_register(mstp_clks
, MSTP_NR
);
109 clkdev_add_table(lookups
, ARRAY_SIZE(lookups
));
114 panic("failed to setup r8a73a4 clocks\n");