arch/arm/mach-ux500/pm.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010-2013
   3  * Author: Rickard Andersson <rickard.andersson@stericsson.com> for
   4  *         ST-Ericsson.
   5  * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
   6  * License terms: GNU General Public License (GPL) version 2
   7  *
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/irqchip/arm-gic.h>
  12 #include <linux/delay.h>
  13 #include <linux/io.h>
  14 #include <linux/platform_data/arm-ux500-pm.h>
  15
  16 #include "db8500-regs.h"
  17
  18 /* ARM WFI Standby signal register */
  19 #define PRCM_ARM_WFI_STANDBY    (prcmu_base + 0x130)
  20 #define PRCM_ARM_WFI_STANDBY_WFI0               0x08
  21 #define PRCM_ARM_WFI_STANDBY_WFI1               0x10
  22 #define PRCM_IOCR               (prcmu_base + 0x310)
  23 #define PRCM_IOCR_IOFORCE                       0x1
  24
  25 /* Dual A9 core interrupt management unit registers */
  26 #define PRCM_A9_MASK_REQ        (prcmu_base + 0x328)
  27 #define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ       0x1
  28
  29 #define PRCM_A9_MASK_ACK        (prcmu_base + 0x32c)
  30 #define PRCM_ARMITMSK31TO0      (prcmu_base + 0x11c)
  31 #define PRCM_ARMITMSK63TO32     (prcmu_base + 0x120)
  32 #define PRCM_ARMITMSK95TO64     (prcmu_base + 0x124)
  33 #define PRCM_ARMITMSK127TO96    (prcmu_base + 0x128)
  34 #define PRCM_POWER_STATE_VAL    (prcmu_base + 0x25C)
  35 #define PRCM_ARMITVAL31TO0      (prcmu_base + 0x260)
  36 #define PRCM_ARMITVAL63TO32     (prcmu_base + 0x264)
  37 #define PRCM_ARMITVAL95TO64     (prcmu_base + 0x268)
  38 #define PRCM_ARMITVAL127TO96    (prcmu_base + 0x26C)
  39
  40 static void __iomem *prcmu_base;
  41
  42 /* This function decouple the gic from the prcmu */
  43 int prcmu_gic_decouple(void)
  44 {
  45         u32 val = readl(PRCM_A9_MASK_REQ);
  46
  47         /* Set bit 0 register value to 1 */
  48         writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
  49                PRCM_A9_MASK_REQ);
  50
  51         /* Make sure the register is updated */
  52         readl(PRCM_A9_MASK_REQ);
  53
  54         /* Wait a few cycles for the gic mask completion */
  55         udelay(1);
  56
  57         return 0;
  58 }
  59
  60 /* This function recouple the gic with the prcmu */
  61 int prcmu_gic_recouple(void)
  62 {
  63         u32 val = readl(PRCM_A9_MASK_REQ);
  64
  65         /* Set bit 0 register value to 0 */
  66         writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
  67
  68         return 0;
  69 }
  70
  71 #define PRCMU_GIC_NUMBER_REGS 5
  72
  73 /*
  74  * This function checks if there are pending irq on the gic. It only
  75  * makes sense if the gic has been decoupled before with the
  76  * db8500_prcmu_gic_decouple function. Disabling an interrupt only
  77  * disables the forwarding of the interrupt to any CPU interface. It
  78  * does not prevent the interrupt from changing state, for example
  79  * becoming pending, or active and pending if it is already
  80  * active. Hence, we have to check the interrupt is pending *and* is
  81  * active.
  82  */
  83 bool prcmu_gic_pending_irq(void)
  84 {
  85         u32 pr; /* Pending register */
  86         u32 er; /* Enable register */
  87         void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
  88         int i;
  89
  90         /* 5 registers. STI & PPI not skipped */
  91         for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
  92
  93                 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
  94                 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
  95
  96                 if (pr & er)
  97                         return true; /* There is a pending interrupt */
  98         }
  99
 100         return false;
 101 }
 102
 103 /*
 104  * This function checks if there are pending interrupt on the
 105  * prcmu which has been delegated to monitor the irqs with the
 106  * db8500_prcmu_copy_gic_settings function.
 107  */
 108 bool prcmu_pending_irq(void)
 109 {
 110         u32 it, im;
 111         int i;
 112
 113         for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
 114                 it = readl(PRCM_ARMITVAL31TO0 + i * 4);
 115                 im = readl(PRCM_ARMITMSK31TO0 + i * 4);
 116                 if (it & im)
 117                         return true; /* There is a pending interrupt */
 118         }
 119
 120         return false;
 121 }
 122
 123 /*
 124  * This function checks if the specified cpu is in in WFI. It's usage
 125  * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
 126  * function. Of course passing smp_processor_id() to this function will
 127  * always return false...
 128  */
 129 bool prcmu_is_cpu_in_wfi(int cpu)
 130 {
 131         return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
 132                      PRCM_ARM_WFI_STANDBY_WFI0;
 133 }
 134
 135 /*
 136  * This function copies the gic SPI settings to the prcmu in order to
 137  * monitor them and abort/finish the retention/off sequence or state.
 138  */
 139 int prcmu_copy_gic_settings(void)
 140 {
 141         u32 er; /* Enable register */
 142         void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
 143         int i;
 144
 145         /* We skip the STI and PPI */
 146         for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
 147                 er = readl_relaxed(dist_base +
 148                                    GIC_DIST_ENABLE_SET + (i + 1) * 4);
 149                 writel(er, PRCM_ARMITMSK31TO0 + i * 4);
 150         }
 151
 152         return 0;
 153 }
 154
 155 void __init ux500_pm_init(u32 phy_base, u32 size)
 156 {
 157         prcmu_base = ioremap(phy_base, size);
 158         if (!prcmu_base) {
 159                 pr_err("could not remap PRCMU for PM functions\n");
 160                 return;
 161         }
 162         /*
 163          * On watchdog reboot the GIC is in some cases decoupled.
 164          * This will make sure that the GIC is correctly configured.
 165          */
 166         prcmu_gic_recouple();
 167 }