| blob | 8f96aa40f5107987edf065c451d4d0879e5e108c |
1 /*
2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
3 *
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020e.
25 *
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
27 */
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/hwcap.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
37 #include "proc-macros.S"
39 /*
40 * This is the maximum size of an area which will be invalidated
41 * using the single invalidate entry instructions. Anything larger
42 * than this, and we go for the whole cache.
43 *
44 * This value should be chosen such that we choose the cheapest
45 * alternative.
46 */
47 #define MAX_AREA_SIZE 32768
49 /*
50 * The size of one data cache line.
51 */
52 #define CACHE_DLINESIZE 32
54 /*
55 * The number of data cache segments.
56 */
57 #define CACHE_DSEGMENTS 16
59 /*
60 * The number of lines in a cache segment.
61 */
62 #define CACHE_DENTRIES 64
64 /*
65 * This is the size at which it becomes more efficient to
66 * clean the whole cache, rather than using the individual
67 * cache line maintenance instructions.
68 */
69 #define CACHE_DLIMIT 32768
71 .text
72 /*
73 * cpu_arm1020e_proc_init()
74 */
75 ENTRY(cpu_arm1020e_proc_init)
76 mov pc, lr
78 /*
79 * cpu_arm1020e_proc_fin()
80 */
81 ENTRY(cpu_arm1020e_proc_fin)
82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 mov pc, lr
88 /*
89 * cpu_arm1020e_reset(loc)
90 *
91 * Perform a soft reset of the system. Put the CPU into the
92 * same state as it would be if it had been reset, and branch
93 * to what would be the reset vector.
94 *
95 * loc: location to jump to for soft reset
96 */
97 .align 5
98 .pushsection .idmap.text, "ax"
99 ENTRY(cpu_arm1020e_reset)
100 mov ip, #0
101 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
102 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 #ifdef CONFIG_MMU
104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 #endif
106 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
107 bic ip, ip, #0x000f @ ............wcam
108 bic ip, ip, #0x1100 @ ...i...s........
109 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
110 mov pc, r0
111 ENDPROC(cpu_arm1020e_reset)
112 .popsection
114 /*
115 * cpu_arm1020e_do_idle()
116 */
117 .align 5
118 ENTRY(cpu_arm1020e_do_idle)
119 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
120 mov pc, lr
122 /* ================================= CACHE ================================ */
124 .align 5
126 /*
127 * flush_icache_all()
128 *
129 * Unconditionally clean and invalidate the entire icache.
130 */
131 ENTRY(arm1020e_flush_icache_all)
132 #ifndef CONFIG_CPU_ICACHE_DISABLE
133 mov r0, #0
134 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
135 #endif
136 mov pc, lr
137 ENDPROC(arm1020e_flush_icache_all)
139 /*
140 * flush_user_cache_all()
141 *
142 * Invalidate all cache entries in a particular address
143 * space.
144 */
145 ENTRY(arm1020e_flush_user_cache_all)
146 /* FALLTHROUGH */
147 /*
148 * flush_kern_cache_all()
149 *
150 * Clean and invalidate the entire cache.
151 */
152 ENTRY(arm1020e_flush_kern_cache_all)
153 mov r2, #VM_EXEC
154 mov ip, #0
155 __flush_whole_cache:
156 #ifndef CONFIG_CPU_DCACHE_DISABLE
157 mcr p15, 0, ip, c7, c10, 4 @ drain WB
158 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
159 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
160 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
161 subs r3, r3, #1 << 26
162 bcs 2b @ entries 63 to 0
163 subs r1, r1, #1 << 5
164 bcs 1b @ segments 15 to 0
165 #endif
166 tst r2, #VM_EXEC
167 #ifndef CONFIG_CPU_ICACHE_DISABLE
168 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
169 #endif
170 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
171 mov pc, lr
173 /*
174 * flush_user_cache_range(start, end, flags)
175 *
176 * Invalidate a range of cache entries in the specified
177 * address space.
178 *
179 * - start - start address (inclusive)
180 * - end - end address (exclusive)
181 * - flags - vm_flags for this space
182 */
183 ENTRY(arm1020e_flush_user_cache_range)
184 mov ip, #0
185 sub r3, r1, r0 @ calculate total size
186 cmp r3, #CACHE_DLIMIT
187 bhs __flush_whole_cache
189 #ifndef CONFIG_CPU_DCACHE_DISABLE
190 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
191 add r0, r0, #CACHE_DLINESIZE
192 cmp r0, r1
193 blo 1b
194 #endif
195 tst r2, #VM_EXEC
196 #ifndef CONFIG_CPU_ICACHE_DISABLE
197 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
198 #endif
199 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
200 mov pc, lr
202 /*
203 * coherent_kern_range(start, end)
204 *
205 * Ensure coherency between the Icache and the Dcache in the
206 * region described by start. If you have non-snooping
207 * Harvard caches, you need to implement this function.
208 *
209 * - start - virtual start address
210 * - end - virtual end address
211 */
212 ENTRY(arm1020e_coherent_kern_range)
213 /* FALLTHROUGH */
214 /*
215 * coherent_user_range(start, end)
216 *
217 * Ensure coherency between the Icache and the Dcache in the
218 * region described by start. If you have non-snooping
219 * Harvard caches, you need to implement this function.
220 *
221 * - start - virtual start address
222 * - end - virtual end address
223 */
224 ENTRY(arm1020e_coherent_user_range)
225 mov ip, #0
226 bic r0, r0, #CACHE_DLINESIZE - 1
227 1:
228 #ifndef CONFIG_CPU_DCACHE_DISABLE
229 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
230 #endif
231 #ifndef CONFIG_CPU_ICACHE_DISABLE
232 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
233 #endif
234 add r0, r0, #CACHE_DLINESIZE
235 cmp r0, r1
236 blo 1b
237 mcr p15, 0, ip, c7, c10, 4 @ drain WB
238 mov r0, #0
239 mov pc, lr
241 /*
242 * flush_kern_dcache_area(void *addr, size_t size)
243 *
244 * Ensure no D cache aliasing occurs, either with itself or
245 * the I cache
246 *
247 * - addr - kernel address
248 * - size - region size
249 */
250 ENTRY(arm1020e_flush_kern_dcache_area)
251 mov ip, #0
252 #ifndef CONFIG_CPU_DCACHE_DISABLE
253 add r1, r0, r1
254 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
255 add r0, r0, #CACHE_DLINESIZE
256 cmp r0, r1
257 blo 1b
258 #endif
259 mcr p15, 0, ip, c7, c10, 4 @ drain WB
260 mov pc, lr
262 /*
263 * dma_inv_range(start, end)
264 *
265 * Invalidate (discard) the specified virtual address range.
266 * May not write back any entries. If 'start' or 'end'
267 * are not cache line aligned, those lines must be written
268 * back.
269 *
270 * - start - virtual start address
271 * - end - virtual end address
272 *
273 * (same as v4wb)
274 */
275 arm1020e_dma_inv_range:
276 mov ip, #0
277 #ifndef CONFIG_CPU_DCACHE_DISABLE
278 tst r0, #CACHE_DLINESIZE - 1
279 bic r0, r0, #CACHE_DLINESIZE - 1
280 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
281 tst r1, #CACHE_DLINESIZE - 1
282 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
283 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
284 add r0, r0, #CACHE_DLINESIZE
285 cmp r0, r1
286 blo 1b
287 #endif
288 mcr p15, 0, ip, c7, c10, 4 @ drain WB
289 mov pc, lr
291 /*
292 * dma_clean_range(start, end)
293 *
294 * Clean the specified virtual address range.
295 *
296 * - start - virtual start address
297 * - end - virtual end address
298 *
299 * (same as v4wb)
300 */
301 arm1020e_dma_clean_range:
302 mov ip, #0
303 #ifndef CONFIG_CPU_DCACHE_DISABLE
304 bic r0, r0, #CACHE_DLINESIZE - 1
305 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
306 add r0, r0, #CACHE_DLINESIZE
307 cmp r0, r1
308 blo 1b
309 #endif
310 mcr p15, 0, ip, c7, c10, 4 @ drain WB
311 mov pc, lr
313 /*
314 * dma_flush_range(start, end)
315 *
316 * Clean and invalidate the specified virtual address range.
317 *
318 * - start - virtual start address
319 * - end - virtual end address
320 */
321 ENTRY(arm1020e_dma_flush_range)
322 mov ip, #0
323 #ifndef CONFIG_CPU_DCACHE_DISABLE
324 bic r0, r0, #CACHE_DLINESIZE - 1
325 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
326 add r0, r0, #CACHE_DLINESIZE
327 cmp r0, r1
328 blo 1b
329 #endif
330 mcr p15, 0, ip, c7, c10, 4 @ drain WB
331 mov pc, lr
333 /*
334 * dma_map_area(start, size, dir)
335 * - start - kernel virtual start address
336 * - size - size of region
337 * - dir - DMA direction
338 */
339 ENTRY(arm1020e_dma_map_area)
340 add r1, r1, r0
341 cmp r2, #DMA_TO_DEVICE
342 beq arm1020e_dma_clean_range
343 bcs arm1020e_dma_inv_range
344 b arm1020e_dma_flush_range
345 ENDPROC(arm1020e_dma_map_area)
347 /*
348 * dma_unmap_area(start, size, dir)
349 * - start - kernel virtual start address
350 * - size - size of region
351 * - dir - DMA direction
352 */
353 ENTRY(arm1020e_dma_unmap_area)
354 mov pc, lr
355 ENDPROC(arm1020e_dma_unmap_area)
357 .globl arm1020e_flush_kern_cache_louis
358 .equ arm1020e_flush_kern_cache_louis, arm1020e_flush_kern_cache_all
360 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
361 define_cache_functions arm1020e
363 .align 5
364 ENTRY(cpu_arm1020e_dcache_clean_area)
365 #ifndef CONFIG_CPU_DCACHE_DISABLE
366 mov ip, #0
367 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
368 add r0, r0, #CACHE_DLINESIZE
369 subs r1, r1, #CACHE_DLINESIZE
370 bhi 1b
371 #endif
372 mov pc, lr
374 /* =============================== PageTable ============================== */
376 /*
377 * cpu_arm1020e_switch_mm(pgd)
378 *
379 * Set the translation base pointer to be as described by pgd.
380 *
381 * pgd: new page tables
382 */
383 .align 5
384 ENTRY(cpu_arm1020e_switch_mm)
385 #ifdef CONFIG_MMU
386 #ifndef CONFIG_CPU_DCACHE_DISABLE
387 mcr p15, 0, r3, c7, c10, 4
388 mov r1, #0xF @ 16 segments
389 1: mov r3, #0x3F @ 64 entries
390 2: mov ip, r3, LSL #26 @ shift up entry
391 orr ip, ip, r1, LSL #5 @ shift in/up index
392 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
393 mov ip, #0
394 subs r3, r3, #1
395 cmp r3, #0
396 bge 2b @ entries 3F to 0
397 subs r1, r1, #1
398 cmp r1, #0
399 bge 1b @ segments 15 to 0
401 #endif
402 mov r1, #0
403 #ifndef CONFIG_CPU_ICACHE_DISABLE
404 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
405 #endif
406 mcr p15, 0, r1, c7, c10, 4 @ drain WB
407 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
408 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
409 #endif
410 mov pc, lr
412 /*
413 * cpu_arm1020e_set_pte(ptep, pte)
414 *
415 * Set a PTE and flush it out
416 */
417 .align 5
418 ENTRY(cpu_arm1020e_set_pte_ext)
419 #ifdef CONFIG_MMU
420 armv3_set_pte_ext
421 mov r0, r0
422 #ifndef CONFIG_CPU_DCACHE_DISABLE
423 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
424 #endif
425 #endif /* CONFIG_MMU */
426 mov pc, lr
428 __CPUINIT
430 .type __arm1020e_setup, #function
431 __arm1020e_setup:
432 mov r0, #0
433 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
434 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
435 #ifdef CONFIG_MMU
436 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
437 #endif
438 adr r5, arm1020e_crval
439 ldmia r5, {r5, r6}
440 mrc p15, 0, r0, c1, c0 @ get control register v4
441 bic r0, r0, r5
442 orr r0, r0, r6
443 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
444 orr r0, r0, #0x4000 @ .R.. .... .... ....
445 #endif
446 mov pc, lr
447 .size __arm1020e_setup, . - __arm1020e_setup
449 /*
450 * R
451 * .RVI ZFRS BLDP WCAM
452 * .011 1001 ..11 0101
453 */
454 .type arm1020e_crval, #object
455 arm1020e_crval:
456 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
458 __INITDATA
459 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
460 define_processor_functions arm1020e, dabort=v4t_early_abort, pabort=legacy_pabort
462 .section ".rodata"
464 string cpu_arch_name, "armv5te"
465 string cpu_elf_name, "v5"
466 string cpu_arm1020e_name, "ARM1020E"
468 .align
470 .section ".proc.info.init", #alloc, #execinstr
472 .type __arm1020e_proc_info,#object
473 __arm1020e_proc_info:
474 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
475 .long 0xff0ffff0
476 .long PMD_TYPE_SECT | \
477 PMD_BIT4 | \
478 PMD_SECT_AP_WRITE | \
479 PMD_SECT_AP_READ
480 .long PMD_TYPE_SECT | \
481 PMD_BIT4 | \
482 PMD_SECT_AP_WRITE | \
483 PMD_SECT_AP_READ
484 b __arm1020e_setup
485 .long cpu_arch_name
486 .long cpu_elf_name
487 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
488 .long cpu_arm1020e_name
489 .long arm1020e_processor_functions
490 .long v4wbi_tlb_fns
491 .long v4wb_user_fns
492 .long arm1020e_cache_fns
493 .size __arm1020e_proc_info, . - __arm1020e_proc_info