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Staging: Panel: panel: Fixed checkpatch line length warnings
[linux/fpc-iii.git] / arch / mips / kernel / cpu-probe.c
blob4bbffdb9024ffb9cf437adb4fd5243e75e68a88c
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/fpu.h>
24 #include <asm/mipsregs.h>
25 #include <asm/watch.h>
26 #include <asm/elf.h>
27 #include <asm/spram.h>
28 #include <asm/uaccess.h>
29
30 /*
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
35 * the CPU very much.
36 */
37 void (*cpu_wait)(void);
38 EXPORT_SYMBOL(cpu_wait);
39
40 static void r3081_wait(void)
41 {
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
44 }
45
46 static void r39xx_wait(void)
47 {
48 local_irq_disable();
49 if (!need_resched())
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51 local_irq_enable();
52 }
53
54 extern void r4k_wait(void);
55
56 /*
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
62 */
63 void r4k_wait_irqoff(void)
64 {
65 local_irq_disable();
66 if (!need_resched())
67 __asm__(" .set push \n"
68 " .set mips3 \n"
69 " wait \n"
70 " .set pop \n");
71 local_irq_enable();
72 __asm__(" .globl __pastwait \n"
73 "__pastwait: \n");
74 }
75
76 /*
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
79 */
80 static void rm7k_wait_irqoff(void)
81 {
82 local_irq_disable();
83 if (!need_resched())
84 __asm__(
85 " .set push \n"
86 " .set mips3 \n"
87 " .set noat \n"
88 " mfc0 $1, $12 \n"
89 " sync \n"
90 " mtc0 $1, $12 # stalls until W stage \n"
91 " wait \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
93 " .set pop \n");
94 local_irq_enable();
95 }
96
97 /*
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
101 */
102 static void au1k_wait(void)
103 {
104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
107 " sync \n"
108 " nop \n"
109 " wait \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " .set mips0 \n"
115 : : "r" (au1k_wait));
116 }
117
118 static int __initdata nowait;
119
120 static int __init wait_disable(char *s)
121 {
122 nowait = 1;
123
124 return 1;
125 }
126
127 __setup("nowait", wait_disable);
128
129 static int __cpuinitdata mips_fpu_disabled;
130
131 static int __init fpu_disable(char *s)
132 {
133 cpu_data[0].options &= ~MIPS_CPU_FPU;
134 mips_fpu_disabled = 1;
135
136 return 1;
137 }
138
139 __setup("nofpu", fpu_disable);
140
141 int __cpuinitdata mips_dsp_disabled;
142
143 static int __init dsp_disable(char *s)
144 {
145 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
146 mips_dsp_disabled = 1;
147
148 return 1;
149 }
150
151 __setup("nodsp", dsp_disable);
152
153 void __init check_wait(void)
154 {
155 struct cpuinfo_mips *c = &current_cpu_data;
156
157 if (nowait) {
158 printk("Wait instruction disabled.\n");
159 return;
160 }
161
162 switch (c->cputype) {
163 case CPU_R3081:
164 case CPU_R3081E:
165 cpu_wait = r3081_wait;
166 break;
167 case CPU_TX3927:
168 cpu_wait = r39xx_wait;
169 break;
170 case CPU_R4200:
171 /* case CPU_R4300: */
172 case CPU_R4600:
173 case CPU_R4640:
174 case CPU_R4650:
175 case CPU_R4700:
176 case CPU_R5000:
177 case CPU_R5500:
178 case CPU_NEVADA:
179 case CPU_4KC:
180 case CPU_4KEC:
181 case CPU_4KSC:
182 case CPU_5KC:
183 case CPU_25KF:
184 case CPU_PR4450:
185 case CPU_BMIPS3300:
186 case CPU_BMIPS4350:
187 case CPU_BMIPS4380:
188 case CPU_BMIPS5000:
189 case CPU_CAVIUM_OCTEON:
190 case CPU_CAVIUM_OCTEON_PLUS:
191 case CPU_CAVIUM_OCTEON2:
192 case CPU_JZRISC:
193 case CPU_LOONGSON1:
194 case CPU_XLR:
195 case CPU_XLP:
196 cpu_wait = r4k_wait;
197 break;
198
199 case CPU_RM7000:
200 cpu_wait = rm7k_wait_irqoff;
201 break;
202
203 case CPU_M14KC:
204 case CPU_M14KEC:
205 case CPU_24K:
206 case CPU_34K:
207 case CPU_1004K:
208 cpu_wait = r4k_wait;
209 if (read_c0_config7() & MIPS_CONF7_WII)
210 cpu_wait = r4k_wait_irqoff;
211 break;
212
213 case CPU_74K:
214 cpu_wait = r4k_wait;
215 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
216 cpu_wait = r4k_wait_irqoff;
217 break;
218
219 case CPU_TX49XX:
220 cpu_wait = r4k_wait_irqoff;
221 break;
222 case CPU_ALCHEMY:
223 cpu_wait = au1k_wait;
224 break;
225 case CPU_20KC:
226 /*
227 * WAIT on Rev1.0 has E1, E2, E3 and E16.
228 * WAIT on Rev2.0 and Rev3.0 has E16.
229 * Rev3.1 WAIT is nop, why bother
230 */
231 if ((c->processor_id & 0xff) <= 0x64)
232 break;
233
234 /*
235 * Another rev is incremeting c0_count at a reduced clock
236 * rate while in WAIT mode. So we basically have the choice
237 * between using the cp0 timer as clocksource or avoiding
238 * the WAIT instruction. Until more details are known,
239 * disable the use of WAIT for 20Kc entirely.
240 cpu_wait = r4k_wait;
241 */
242 break;
243 case CPU_RM9000:
244 if ((c->processor_id & 0x00ff) >= 0x40)
245 cpu_wait = r4k_wait;
246 break;
247 default:
248 break;
249 }
250 }
251
252 static inline void check_errata(void)
253 {
254 struct cpuinfo_mips *c = &current_cpu_data;
255
256 switch (c->cputype) {
257 case CPU_34K:
258 /*
259 * Erratum "RPS May Cause Incorrect Instruction Execution"
260 * This code only handles VPE0, any SMP/SMTC/RTOS code
261 * making use of VPE1 will be responsable for that VPE.
262 */
263 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
264 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
265 break;
266 default:
267 break;
268 }
269 }
270
271 void __init check_bugs32(void)
272 {
273 check_errata();
274 }
275
276 /*
277 * Probe whether cpu has config register by trying to play with
278 * alternate cache bit and see whether it matters.
279 * It's used by cpu_probe to distinguish between R3000A and R3081.
280 */
281 static inline int cpu_has_confreg(void)
282 {
283 #ifdef CONFIG_CPU_R3000
284 extern unsigned long r3k_cache_size(unsigned long);
285 unsigned long size1, size2;
286 unsigned long cfg = read_c0_conf();
287
288 size1 = r3k_cache_size(ST0_ISC);
289 write_c0_conf(cfg ^ R30XX_CONF_AC);
290 size2 = r3k_cache_size(ST0_ISC);
291 write_c0_conf(cfg);
292 return size1 != size2;
293 #else
294 return 0;
295 #endif
296 }
297
298 static inline void set_elf_platform(int cpu, const char *plat)
299 {
300 if (cpu == 0)
301 __elf_platform = plat;
302 }
303
304 /*
305 * Get the FPU Implementation/Revision.
306 */
307 static inline unsigned long cpu_get_fpu_id(void)
308 {
309 unsigned long tmp, fpu_id;
310
311 tmp = read_c0_status();
312 __enable_fpu();
313 fpu_id = read_32bit_cp1_register(CP1_REVISION);
314 write_c0_status(tmp);
315 return fpu_id;
316 }
317
318 /*
319 * Check the CPU has an FPU the official way.
320 */
321 static inline int __cpu_has_fpu(void)
322 {
323 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
324 }
325
326 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
327 {
328 #ifdef __NEED_VMBITS_PROBE
329 write_c0_entryhi(0x3fffffffffffe000ULL);
330 back_to_back_c0_hazard();
331 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
332 #endif
333 }
334
335 static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
336 {
337 switch (isa) {
338 case MIPS_CPU_ISA_M64R2:
339 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
340 case MIPS_CPU_ISA_M64R1:
341 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
342 case MIPS_CPU_ISA_V:
343 c->isa_level |= MIPS_CPU_ISA_V;
344 case MIPS_CPU_ISA_IV:
345 c->isa_level |= MIPS_CPU_ISA_IV;
346 case MIPS_CPU_ISA_III:
347 c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II |
348 MIPS_CPU_ISA_III;
349 break;
350
351 case MIPS_CPU_ISA_M32R2:
352 c->isa_level |= MIPS_CPU_ISA_M32R2;
353 case MIPS_CPU_ISA_M32R1:
354 c->isa_level |= MIPS_CPU_ISA_M32R1;
355 case MIPS_CPU_ISA_II:
356 c->isa_level |= MIPS_CPU_ISA_II;
357 case MIPS_CPU_ISA_I:
358 c->isa_level |= MIPS_CPU_ISA_I;
359 break;
360 }
361 }
362
363 static char unknown_isa[] __cpuinitdata = KERN_ERR \
364 "Unsupported ISA type, c0.config0: %d.";
365
366 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
367 {
368 unsigned int config0;
369 int isa;
370
371 config0 = read_c0_config();
372
373 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
374 c->options |= MIPS_CPU_TLB;
375 isa = (config0 & MIPS_CONF_AT) >> 13;
376 switch (isa) {
377 case 0:
378 switch ((config0 & MIPS_CONF_AR) >> 10) {
379 case 0:
380 set_isa(c, MIPS_CPU_ISA_M32R1);
381 break;
382 case 1:
383 set_isa(c, MIPS_CPU_ISA_M32R2);
384 break;
385 default:
386 goto unknown;
387 }
388 break;
389 case 2:
390 switch ((config0 & MIPS_CONF_AR) >> 10) {
391 case 0:
392 set_isa(c, MIPS_CPU_ISA_M64R1);
393 break;
394 case 1:
395 set_isa(c, MIPS_CPU_ISA_M64R2);
396 break;
397 default:
398 goto unknown;
399 }
400 break;
401 default:
402 goto unknown;
403 }
404
405 return config0 & MIPS_CONF_M;
406
407 unknown:
408 panic(unknown_isa, config0);
409 }
410
411 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
412 {
413 unsigned int config1;
414
415 config1 = read_c0_config1();
416
417 if (config1 & MIPS_CONF1_MD)
418 c->ases |= MIPS_ASE_MDMX;
419 if (config1 & MIPS_CONF1_WR)
420 c->options |= MIPS_CPU_WATCH;
421 if (config1 & MIPS_CONF1_CA)
422 c->ases |= MIPS_ASE_MIPS16;
423 if (config1 & MIPS_CONF1_EP)
424 c->options |= MIPS_CPU_EJTAG;
425 if (config1 & MIPS_CONF1_FP) {
426 c->options |= MIPS_CPU_FPU;
427 c->options |= MIPS_CPU_32FPR;
428 }
429 if (cpu_has_tlb)
430 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
431
432 return config1 & MIPS_CONF_M;
433 }
434
435 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
436 {
437 unsigned int config2;
438
439 config2 = read_c0_config2();
440
441 if (config2 & MIPS_CONF2_SL)
442 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
443
444 return config2 & MIPS_CONF_M;
445 }
446
447 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
448 {
449 unsigned int config3;
450
451 config3 = read_c0_config3();
452
453 if (config3 & MIPS_CONF3_SM) {
454 c->ases |= MIPS_ASE_SMARTMIPS;
455 c->options |= MIPS_CPU_RIXI;
456 }
457 if (config3 & MIPS_CONF3_RXI)
458 c->options |= MIPS_CPU_RIXI;
459 if (config3 & MIPS_CONF3_DSP)
460 c->ases |= MIPS_ASE_DSP;
461 if (config3 & MIPS_CONF3_DSP2P)
462 c->ases |= MIPS_ASE_DSP2P;
463 if (config3 & MIPS_CONF3_VINT)
464 c->options |= MIPS_CPU_VINT;
465 if (config3 & MIPS_CONF3_VEIC)
466 c->options |= MIPS_CPU_VEIC;
467 if (config3 & MIPS_CONF3_MT)
468 c->ases |= MIPS_ASE_MIPSMT;
469 if (config3 & MIPS_CONF3_ULRI)
470 c->options |= MIPS_CPU_ULRI;
471 if (config3 & MIPS_CONF3_ISA)
472 c->options |= MIPS_CPU_MICROMIPS;
473 #ifdef CONFIG_CPU_MICROMIPS
474 write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE);
475 #endif
476 if (config3 & MIPS_CONF3_VZ)
477 c->ases |= MIPS_ASE_VZ;
478
479 return config3 & MIPS_CONF_M;
480 }
481
482 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
483 {
484 unsigned int config4;
485
486 config4 = read_c0_config4();
487
488 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
489 && cpu_has_tlb)
490 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
491
492 c->kscratch_mask = (config4 >> 16) & 0xff;
493
494 return config4 & MIPS_CONF_M;
495 }
496
497 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
498 {
499 int ok;
500
501 /* MIPS32 or MIPS64 compliant CPU. */
502 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
503 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
504
505 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
506
507 ok = decode_config0(c); /* Read Config registers. */
508 BUG_ON(!ok); /* Arch spec violation! */
509 if (ok)
510 ok = decode_config1(c);
511 if (ok)
512 ok = decode_config2(c);
513 if (ok)
514 ok = decode_config3(c);
515 if (ok)
516 ok = decode_config4(c);
517
518 mips_probe_watch_registers(c);
519
520 if (cpu_has_mips_r2)
521 c->core = read_c0_ebase() & 0x3ff;
522 }
523
524 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
525 | MIPS_CPU_COUNTER)
526
527 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
528 {
529 switch (c->processor_id & 0xff00) {
530 case PRID_IMP_R2000:
531 c->cputype = CPU_R2000;
532 __cpu_name[cpu] = "R2000";
533 set_isa(c, MIPS_CPU_ISA_I);
534 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
535 MIPS_CPU_NOFPUEX;
536 if (__cpu_has_fpu())
537 c->options |= MIPS_CPU_FPU;
538 c->tlbsize = 64;
539 break;
540 case PRID_IMP_R3000:
541 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
542 if (cpu_has_confreg()) {
543 c->cputype = CPU_R3081E;
544 __cpu_name[cpu] = "R3081";
545 } else {
546 c->cputype = CPU_R3000A;
547 __cpu_name[cpu] = "R3000A";
548 }
549 } else {
550 c->cputype = CPU_R3000;
551 __cpu_name[cpu] = "R3000";
552 }
553 set_isa(c, MIPS_CPU_ISA_I);
554 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
555 MIPS_CPU_NOFPUEX;
556 if (__cpu_has_fpu())
557 c->options |= MIPS_CPU_FPU;
558 c->tlbsize = 64;
559 break;
560 case PRID_IMP_R4000:
561 if (read_c0_config() & CONF_SC) {
562 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
563 c->cputype = CPU_R4400PC;
564 __cpu_name[cpu] = "R4400PC";
565 } else {
566 c->cputype = CPU_R4000PC;
567 __cpu_name[cpu] = "R4000PC";
568 }
569 } else {
570 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
571 c->cputype = CPU_R4400SC;
572 __cpu_name[cpu] = "R4400SC";
573 } else {
574 c->cputype = CPU_R4000SC;
575 __cpu_name[cpu] = "R4000SC";
576 }
577 }
578
579 set_isa(c, MIPS_CPU_ISA_III);
580 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
581 MIPS_CPU_WATCH | MIPS_CPU_VCE |
582 MIPS_CPU_LLSC;
583 c->tlbsize = 48;
584 break;
585 case PRID_IMP_VR41XX:
586 set_isa(c, MIPS_CPU_ISA_III);
587 c->options = R4K_OPTS;
588 c->tlbsize = 32;
589 switch (c->processor_id & 0xf0) {
590 case PRID_REV_VR4111:
591 c->cputype = CPU_VR4111;
592 __cpu_name[cpu] = "NEC VR4111";
593 break;
594 case PRID_REV_VR4121:
595 c->cputype = CPU_VR4121;
596 __cpu_name[cpu] = "NEC VR4121";
597 break;
598 case PRID_REV_VR4122:
599 if ((c->processor_id & 0xf) < 0x3) {
600 c->cputype = CPU_VR4122;
601 __cpu_name[cpu] = "NEC VR4122";
602 } else {
603 c->cputype = CPU_VR4181A;
604 __cpu_name[cpu] = "NEC VR4181A";
605 }
606 break;
607 case PRID_REV_VR4130:
608 if ((c->processor_id & 0xf) < 0x4) {
609 c->cputype = CPU_VR4131;
610 __cpu_name[cpu] = "NEC VR4131";
611 } else {
612 c->cputype = CPU_VR4133;
613 c->options |= MIPS_CPU_LLSC;
614 __cpu_name[cpu] = "NEC VR4133";
615 }
616 break;
617 default:
618 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
619 c->cputype = CPU_VR41XX;
620 __cpu_name[cpu] = "NEC Vr41xx";
621 break;
622 }
623 break;
624 case PRID_IMP_R4300:
625 c->cputype = CPU_R4300;
626 __cpu_name[cpu] = "R4300";
627 set_isa(c, MIPS_CPU_ISA_III);
628 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
629 MIPS_CPU_LLSC;
630 c->tlbsize = 32;
631 break;
632 case PRID_IMP_R4600:
633 c->cputype = CPU_R4600;
634 __cpu_name[cpu] = "R4600";
635 set_isa(c, MIPS_CPU_ISA_III);
636 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
637 MIPS_CPU_LLSC;
638 c->tlbsize = 48;
639 break;
640 #if 0
641 case PRID_IMP_R4650:
642 /*
643 * This processor doesn't have an MMU, so it's not
644 * "real easy" to run Linux on it. It is left purely
645 * for documentation. Commented out because it shares
646 * it's c0_prid id number with the TX3900.
647 */
648 c->cputype = CPU_R4650;
649 __cpu_name[cpu] = "R4650";
650 set_isa(c, MIPS_CPU_ISA_III);
651 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
652 c->tlbsize = 48;
653 break;
654 #endif
655 case PRID_IMP_TX39:
656 set_isa(c, MIPS_CPU_ISA_I);
657 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
658
659 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
660 c->cputype = CPU_TX3927;
661 __cpu_name[cpu] = "TX3927";
662 c->tlbsize = 64;
663 } else {
664 switch (c->processor_id & 0xff) {
665 case PRID_REV_TX3912:
666 c->cputype = CPU_TX3912;
667 __cpu_name[cpu] = "TX3912";
668 c->tlbsize = 32;
669 break;
670 case PRID_REV_TX3922:
671 c->cputype = CPU_TX3922;
672 __cpu_name[cpu] = "TX3922";
673 c->tlbsize = 64;
674 break;
675 }
676 }
677 break;
678 case PRID_IMP_R4700:
679 c->cputype = CPU_R4700;
680 __cpu_name[cpu] = "R4700";
681 set_isa(c, MIPS_CPU_ISA_III);
682 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
683 MIPS_CPU_LLSC;
684 c->tlbsize = 48;
685 break;
686 case PRID_IMP_TX49:
687 c->cputype = CPU_TX49XX;
688 __cpu_name[cpu] = "R49XX";
689 set_isa(c, MIPS_CPU_ISA_III);
690 c->options = R4K_OPTS | MIPS_CPU_LLSC;
691 if (!(c->processor_id & 0x08))
692 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
693 c->tlbsize = 48;
694 break;
695 case PRID_IMP_R5000:
696 c->cputype = CPU_R5000;
697 __cpu_name[cpu] = "R5000";
698 set_isa(c, MIPS_CPU_ISA_IV);
699 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
700 MIPS_CPU_LLSC;
701 c->tlbsize = 48;
702 break;
703 case PRID_IMP_R5432:
704 c->cputype = CPU_R5432;
705 __cpu_name[cpu] = "R5432";
706 set_isa(c, MIPS_CPU_ISA_IV);
707 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
708 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
709 c->tlbsize = 48;
710 break;
711 case PRID_IMP_R5500:
712 c->cputype = CPU_R5500;
713 __cpu_name[cpu] = "R5500";
714 set_isa(c, MIPS_CPU_ISA_IV);
715 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
716 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
717 c->tlbsize = 48;
718 break;
719 case PRID_IMP_NEVADA:
720 c->cputype = CPU_NEVADA;
721 __cpu_name[cpu] = "Nevada";
722 set_isa(c, MIPS_CPU_ISA_IV);
723 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
724 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
725 c->tlbsize = 48;
726 break;
727 case PRID_IMP_R6000:
728 c->cputype = CPU_R6000;
729 __cpu_name[cpu] = "R6000";
730 set_isa(c, MIPS_CPU_ISA_II);
731 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
732 MIPS_CPU_LLSC;
733 c->tlbsize = 32;
734 break;
735 case PRID_IMP_R6000A:
736 c->cputype = CPU_R6000A;
737 __cpu_name[cpu] = "R6000A";
738 set_isa(c, MIPS_CPU_ISA_II);
739 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
740 MIPS_CPU_LLSC;
741 c->tlbsize = 32;
742 break;
743 case PRID_IMP_RM7000:
744 c->cputype = CPU_RM7000;
745 __cpu_name[cpu] = "RM7000";
746 set_isa(c, MIPS_CPU_ISA_IV);
747 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
748 MIPS_CPU_LLSC;
749 /*
750 * Undocumented RM7000: Bit 29 in the info register of
751 * the RM7000 v2.0 indicates if the TLB has 48 or 64
752 * entries.
753 *
754 * 29 1 => 64 entry JTLB
755 * 0 => 48 entry JTLB
756 */
757 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
758 break;
759 case PRID_IMP_RM9000:
760 c->cputype = CPU_RM9000;
761 __cpu_name[cpu] = "RM9000";
762 set_isa(c, MIPS_CPU_ISA_IV);
763 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
764 MIPS_CPU_LLSC;
765 /*
766 * Bit 29 in the info register of the RM9000
767 * indicates if the TLB has 48 or 64 entries.
768 *
769 * 29 1 => 64 entry JTLB
770 * 0 => 48 entry JTLB
771 */
772 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
773 break;
774 case PRID_IMP_R8000:
775 c->cputype = CPU_R8000;
776 __cpu_name[cpu] = "RM8000";
777 set_isa(c, MIPS_CPU_ISA_IV);
778 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
779 MIPS_CPU_FPU | MIPS_CPU_32FPR |
780 MIPS_CPU_LLSC;
781 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
782 break;
783 case PRID_IMP_R10000:
784 c->cputype = CPU_R10000;
785 __cpu_name[cpu] = "R10000";
786 set_isa(c, MIPS_CPU_ISA_IV);
787 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
788 MIPS_CPU_FPU | MIPS_CPU_32FPR |
789 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
790 MIPS_CPU_LLSC;
791 c->tlbsize = 64;
792 break;
793 case PRID_IMP_R12000:
794 c->cputype = CPU_R12000;
795 __cpu_name[cpu] = "R12000";
796 set_isa(c, MIPS_CPU_ISA_IV);
797 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
798 MIPS_CPU_FPU | MIPS_CPU_32FPR |
799 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
800 MIPS_CPU_LLSC;
801 c->tlbsize = 64;
802 break;
803 case PRID_IMP_R14000:
804 c->cputype = CPU_R14000;
805 __cpu_name[cpu] = "R14000";
806 set_isa(c, MIPS_CPU_ISA_IV);
807 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
808 MIPS_CPU_FPU | MIPS_CPU_32FPR |
809 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
810 MIPS_CPU_LLSC;
811 c->tlbsize = 64;
812 break;
813 case PRID_IMP_LOONGSON2:
814 c->cputype = CPU_LOONGSON2;
815 __cpu_name[cpu] = "ICT Loongson-2";
816
817 switch (c->processor_id & PRID_REV_MASK) {
818 case PRID_REV_LOONGSON2E:
819 set_elf_platform(cpu, "loongson2e");
820 break;
821 case PRID_REV_LOONGSON2F:
822 set_elf_platform(cpu, "loongson2f");
823 break;
824 }
825
826 set_isa(c, MIPS_CPU_ISA_III);
827 c->options = R4K_OPTS |
828 MIPS_CPU_FPU | MIPS_CPU_LLSC |
829 MIPS_CPU_32FPR;
830 c->tlbsize = 64;
831 break;
832 case PRID_IMP_LOONGSON1:
833 decode_configs(c);
834
835 c->cputype = CPU_LOONGSON1;
836
837 switch (c->processor_id & PRID_REV_MASK) {
838 case PRID_REV_LOONGSON1B:
839 __cpu_name[cpu] = "Loongson 1B";
840 break;
841 }
842
843 break;
844 }
845 }
846
847 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
848 {
849 decode_configs(c);
850 switch (c->processor_id & 0xff00) {
851 case PRID_IMP_4KC:
852 c->cputype = CPU_4KC;
853 __cpu_name[cpu] = "MIPS 4Kc";
854 break;
855 case PRID_IMP_4KEC:
856 case PRID_IMP_4KECR2:
857 c->cputype = CPU_4KEC;
858 __cpu_name[cpu] = "MIPS 4KEc";
859 break;
860 case PRID_IMP_4KSC:
861 case PRID_IMP_4KSD:
862 c->cputype = CPU_4KSC;
863 __cpu_name[cpu] = "MIPS 4KSc";
864 break;
865 case PRID_IMP_5KC:
866 c->cputype = CPU_5KC;
867 __cpu_name[cpu] = "MIPS 5Kc";
868 break;
869 case PRID_IMP_5KE:
870 c->cputype = CPU_5KE;
871 __cpu_name[cpu] = "MIPS 5KE";
872 break;
873 case PRID_IMP_20KC:
874 c->cputype = CPU_20KC;
875 __cpu_name[cpu] = "MIPS 20Kc";
876 break;
877 case PRID_IMP_24K:
878 c->cputype = CPU_24K;
879 __cpu_name[cpu] = "MIPS 24Kc";
880 break;
881 case PRID_IMP_24KE:
882 c->cputype = CPU_24K;
883 __cpu_name[cpu] = "MIPS 24KEc";
884 break;
885 case PRID_IMP_25KF:
886 c->cputype = CPU_25KF;
887 __cpu_name[cpu] = "MIPS 25Kc";
888 break;
889 case PRID_IMP_34K:
890 c->cputype = CPU_34K;
891 __cpu_name[cpu] = "MIPS 34Kc";
892 break;
893 case PRID_IMP_74K:
894 c->cputype = CPU_74K;
895 __cpu_name[cpu] = "MIPS 74Kc";
896 break;
897 case PRID_IMP_M14KC:
898 c->cputype = CPU_M14KC;
899 __cpu_name[cpu] = "MIPS M14Kc";
900 break;
901 case PRID_IMP_M14KEC:
902 c->cputype = CPU_M14KEC;
903 __cpu_name[cpu] = "MIPS M14KEc";
904 break;
905 case PRID_IMP_1004K:
906 c->cputype = CPU_1004K;
907 __cpu_name[cpu] = "MIPS 1004Kc";
908 break;
909 case PRID_IMP_1074K:
910 c->cputype = CPU_74K;
911 __cpu_name[cpu] = "MIPS 1074Kc";
912 break;
913 }
914
915 spram_config();
916 }
917
918 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
919 {
920 decode_configs(c);
921 switch (c->processor_id & 0xff00) {
922 case PRID_IMP_AU1_REV1:
923 case PRID_IMP_AU1_REV2:
924 c->cputype = CPU_ALCHEMY;
925 switch ((c->processor_id >> 24) & 0xff) {
926 case 0:
927 __cpu_name[cpu] = "Au1000";
928 break;
929 case 1:
930 __cpu_name[cpu] = "Au1500";
931 break;
932 case 2:
933 __cpu_name[cpu] = "Au1100";
934 break;
935 case 3:
936 __cpu_name[cpu] = "Au1550";
937 break;
938 case 4:
939 __cpu_name[cpu] = "Au1200";
940 if ((c->processor_id & 0xff) == 2)
941 __cpu_name[cpu] = "Au1250";
942 break;
943 case 5:
944 __cpu_name[cpu] = "Au1210";
945 break;
946 default:
947 __cpu_name[cpu] = "Au1xxx";
948 break;
949 }
950 break;
951 }
952 }
953
954 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
955 {
956 decode_configs(c);
957
958 switch (c->processor_id & 0xff00) {
959 case PRID_IMP_SB1:
960 c->cputype = CPU_SB1;
961 __cpu_name[cpu] = "SiByte SB1";
962 /* FPU in pass1 is known to have issues. */
963 if ((c->processor_id & 0xff) < 0x02)
964 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
965 break;
966 case PRID_IMP_SB1A:
967 c->cputype = CPU_SB1A;
968 __cpu_name[cpu] = "SiByte SB1A";
969 break;
970 }
971 }
972
973 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
974 {
975 decode_configs(c);
976 switch (c->processor_id & 0xff00) {
977 case PRID_IMP_SR71000:
978 c->cputype = CPU_SR71000;
979 __cpu_name[cpu] = "Sandcraft SR71000";
980 c->scache.ways = 8;
981 c->tlbsize = 64;
982 break;
983 }
984 }
985
986 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
987 {
988 decode_configs(c);
989 switch (c->processor_id & 0xff00) {
990 case PRID_IMP_PR4450:
991 c->cputype = CPU_PR4450;
992 __cpu_name[cpu] = "Philips PR4450";
993 set_isa(c, MIPS_CPU_ISA_M32R1);
994 break;
995 }
996 }
997
998 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
999 {
1000 decode_configs(c);
1001 switch (c->processor_id & 0xff00) {
1002 case PRID_IMP_BMIPS32_REV4:
1003 case PRID_IMP_BMIPS32_REV8:
1004 c->cputype = CPU_BMIPS32;
1005 __cpu_name[cpu] = "Broadcom BMIPS32";
1006 set_elf_platform(cpu, "bmips32");
1007 break;
1008 case PRID_IMP_BMIPS3300:
1009 case PRID_IMP_BMIPS3300_ALT:
1010 case PRID_IMP_BMIPS3300_BUG:
1011 c->cputype = CPU_BMIPS3300;
1012 __cpu_name[cpu] = "Broadcom BMIPS3300";
1013 set_elf_platform(cpu, "bmips3300");
1014 break;
1015 case PRID_IMP_BMIPS43XX: {
1016 int rev = c->processor_id & 0xff;
1017
1018 if (rev >= PRID_REV_BMIPS4380_LO &&
1019 rev <= PRID_REV_BMIPS4380_HI) {
1020 c->cputype = CPU_BMIPS4380;
1021 __cpu_name[cpu] = "Broadcom BMIPS4380";
1022 set_elf_platform(cpu, "bmips4380");
1023 } else {
1024 c->cputype = CPU_BMIPS4350;
1025 __cpu_name[cpu] = "Broadcom BMIPS4350";
1026 set_elf_platform(cpu, "bmips4350");
1027 }
1028 break;
1029 }
1030 case PRID_IMP_BMIPS5000:
1031 c->cputype = CPU_BMIPS5000;
1032 __cpu_name[cpu] = "Broadcom BMIPS5000";
1033 set_elf_platform(cpu, "bmips5000");
1034 c->options |= MIPS_CPU_ULRI;
1035 break;
1036 }
1037 }
1038
1039 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1040 {
1041 decode_configs(c);
1042 switch (c->processor_id & 0xff00) {
1043 case PRID_IMP_CAVIUM_CN38XX:
1044 case PRID_IMP_CAVIUM_CN31XX:
1045 case PRID_IMP_CAVIUM_CN30XX:
1046 c->cputype = CPU_CAVIUM_OCTEON;
1047 __cpu_name[cpu] = "Cavium Octeon";
1048 goto platform;
1049 case PRID_IMP_CAVIUM_CN58XX:
1050 case PRID_IMP_CAVIUM_CN56XX:
1051 case PRID_IMP_CAVIUM_CN50XX:
1052 case PRID_IMP_CAVIUM_CN52XX:
1053 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1054 __cpu_name[cpu] = "Cavium Octeon+";
1055 platform:
1056 set_elf_platform(cpu, "octeon");
1057 break;
1058 case PRID_IMP_CAVIUM_CN61XX:
1059 case PRID_IMP_CAVIUM_CN63XX:
1060 case PRID_IMP_CAVIUM_CN66XX:
1061 case PRID_IMP_CAVIUM_CN68XX:
1062 c->cputype = CPU_CAVIUM_OCTEON2;
1063 __cpu_name[cpu] = "Cavium Octeon II";
1064 set_elf_platform(cpu, "octeon2");
1065 break;
1066 default:
1067 printk(KERN_INFO "Unknown Octeon chip!\n");
1068 c->cputype = CPU_UNKNOWN;
1069 break;
1070 }
1071 }
1072
1073 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1074 {
1075 decode_configs(c);
1076 /* JZRISC does not implement the CP0 counter. */
1077 c->options &= ~MIPS_CPU_COUNTER;
1078 switch (c->processor_id & 0xff00) {
1079 case PRID_IMP_JZRISC:
1080 c->cputype = CPU_JZRISC;
1081 __cpu_name[cpu] = "Ingenic JZRISC";
1082 break;
1083 default:
1084 panic("Unknown Ingenic Processor ID!");
1085 break;
1086 }
1087 }
1088
1089 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1090 {
1091 decode_configs(c);
1092
1093 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1094 c->cputype = CPU_ALCHEMY;
1095 __cpu_name[cpu] = "Au1300";
1096 /* following stuff is not for Alchemy */
1097 return;
1098 }
1099
1100 c->options = (MIPS_CPU_TLB |
1101 MIPS_CPU_4KEX |
1102 MIPS_CPU_COUNTER |
1103 MIPS_CPU_DIVEC |
1104 MIPS_CPU_WATCH |
1105 MIPS_CPU_EJTAG |
1106 MIPS_CPU_LLSC);
1107
1108 switch (c->processor_id & 0xff00) {
1109 case PRID_IMP_NETLOGIC_XLP8XX:
1110 case PRID_IMP_NETLOGIC_XLP3XX:
1111 c->cputype = CPU_XLP;
1112 __cpu_name[cpu] = "Netlogic XLP";
1113 break;
1114
1115 case PRID_IMP_NETLOGIC_XLR732:
1116 case PRID_IMP_NETLOGIC_XLR716:
1117 case PRID_IMP_NETLOGIC_XLR532:
1118 case PRID_IMP_NETLOGIC_XLR308:
1119 case PRID_IMP_NETLOGIC_XLR532C:
1120 case PRID_IMP_NETLOGIC_XLR516C:
1121 case PRID_IMP_NETLOGIC_XLR508C:
1122 case PRID_IMP_NETLOGIC_XLR308C:
1123 c->cputype = CPU_XLR;
1124 __cpu_name[cpu] = "Netlogic XLR";
1125 break;
1126
1127 case PRID_IMP_NETLOGIC_XLS608:
1128 case PRID_IMP_NETLOGIC_XLS408:
1129 case PRID_IMP_NETLOGIC_XLS404:
1130 case PRID_IMP_NETLOGIC_XLS208:
1131 case PRID_IMP_NETLOGIC_XLS204:
1132 case PRID_IMP_NETLOGIC_XLS108:
1133 case PRID_IMP_NETLOGIC_XLS104:
1134 case PRID_IMP_NETLOGIC_XLS616B:
1135 case PRID_IMP_NETLOGIC_XLS608B:
1136 case PRID_IMP_NETLOGIC_XLS416B:
1137 case PRID_IMP_NETLOGIC_XLS412B:
1138 case PRID_IMP_NETLOGIC_XLS408B:
1139 case PRID_IMP_NETLOGIC_XLS404B:
1140 c->cputype = CPU_XLR;
1141 __cpu_name[cpu] = "Netlogic XLS";
1142 break;
1143
1144 default:
1145 pr_info("Unknown Netlogic chip id [%02x]!\n",
1146 c->processor_id);
1147 c->cputype = CPU_XLR;
1148 break;
1149 }
1150
1151 if (c->cputype == CPU_XLP) {
1152 set_isa(c, MIPS_CPU_ISA_M64R2);
1153 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1154 /* This will be updated again after all threads are woken up */
1155 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1156 } else {
1157 set_isa(c, MIPS_CPU_ISA_M64R1);
1158 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1159 }
1160 }
1161
1162 #ifdef CONFIG_64BIT
1163 /* For use by uaccess.h */
1164 u64 __ua_limit;
1165 EXPORT_SYMBOL(__ua_limit);
1166 #endif
1167
1168 const char *__cpu_name[NR_CPUS];
1169 const char *__elf_platform;
1170
1171 __cpuinit void cpu_probe(void)
1172 {
1173 struct cpuinfo_mips *c = &current_cpu_data;
1174 unsigned int cpu = smp_processor_id();
1175
1176 c->processor_id = PRID_IMP_UNKNOWN;
1177 c->fpu_id = FPIR_IMP_NONE;
1178 c->cputype = CPU_UNKNOWN;
1179
1180 c->processor_id = read_c0_prid();
1181 switch (c->processor_id & 0xff0000) {
1182 case PRID_COMP_LEGACY:
1183 cpu_probe_legacy(c, cpu);
1184 break;
1185 case PRID_COMP_MIPS:
1186 cpu_probe_mips(c, cpu);
1187 break;
1188 case PRID_COMP_ALCHEMY:
1189 cpu_probe_alchemy(c, cpu);
1190 break;
1191 case PRID_COMP_SIBYTE:
1192 cpu_probe_sibyte(c, cpu);
1193 break;
1194 case PRID_COMP_BROADCOM:
1195 cpu_probe_broadcom(c, cpu);
1196 break;
1197 case PRID_COMP_SANDCRAFT:
1198 cpu_probe_sandcraft(c, cpu);
1199 break;
1200 case PRID_COMP_NXP:
1201 cpu_probe_nxp(c, cpu);
1202 break;
1203 case PRID_COMP_CAVIUM:
1204 cpu_probe_cavium(c, cpu);
1205 break;
1206 case PRID_COMP_INGENIC:
1207 cpu_probe_ingenic(c, cpu);
1208 break;
1209 case PRID_COMP_NETLOGIC:
1210 cpu_probe_netlogic(c, cpu);
1211 break;
1212 }
1213
1214 BUG_ON(!__cpu_name[cpu]);
1215 BUG_ON(c->cputype == CPU_UNKNOWN);
1216
1217 /*
1218 * Platform code can force the cpu type to optimize code
1219 * generation. In that case be sure the cpu type is correctly
1220 * manually setup otherwise it could trigger some nasty bugs.
1221 */
1222 BUG_ON(current_cpu_type() != c->cputype);
1223
1224 if (mips_fpu_disabled)
1225 c->options &= ~MIPS_CPU_FPU;
1226
1227 if (mips_dsp_disabled)
1228 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1229
1230 if (c->options & MIPS_CPU_FPU) {
1231 c->fpu_id = cpu_get_fpu_id();
1232
1233 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1234 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1235 if (c->fpu_id & MIPS_FPIR_3D)
1236 c->ases |= MIPS_ASE_MIPS3D;
1237 }
1238 }
1239
1240 if (cpu_has_mips_r2) {
1241 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1242 /* R2 has Performance Counter Interrupt indicator */
1243 c->options |= MIPS_CPU_PCI;
1244 }
1245 else
1246 c->srsets = 1;
1247
1248 cpu_probe_vmbits(c);
1249
1250 #ifdef CONFIG_64BIT
1251 if (cpu == 0)
1252 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1253 #endif
1254 }
1255
1256 __cpuinit void cpu_report(void)
1257 {
1258 struct cpuinfo_mips *c = &current_cpu_data;
1259
1260 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1261 c->processor_id, cpu_name_string());
1262 if (c->options & MIPS_CPU_FPU)
1263 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1264 }
Linux with added FPC-III support