arch/openrisc/include/asm/spr_defs.h

   1 /*
   2  * OpenRISC Linux
   3  *
   4  * SPR Definitions
   5  *
   6  * Copyright (C) 2000 Damjan Lampret
   7  * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
   8  * Copyright (C) 2008, 2010 Embecosm Limited
   9  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  10  * et al.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This file is part of OpenRISC 1000 Architectural Simulator.
  18  */
  19
  20 #ifndef SPR_DEFS__H
  21 #define SPR_DEFS__H
  22
  23 /* Definition of special-purpose registers (SPRs). */
  24
  25 #define MAX_GRPS (32)
  26 #define MAX_SPRS_PER_GRP_BITS (11)
  27 #define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
  28 #define MAX_SPRS (0x10000)
  29
  30 /* Base addresses for the groups */
  31 #define SPRGROUP_SYS    (0 << MAX_SPRS_PER_GRP_BITS)
  32 #define SPRGROUP_DMMU   (1 << MAX_SPRS_PER_GRP_BITS)
  33 #define SPRGROUP_IMMU   (2 << MAX_SPRS_PER_GRP_BITS)
  34 #define SPRGROUP_DC     (3 << MAX_SPRS_PER_GRP_BITS)
  35 #define SPRGROUP_IC     (4 << MAX_SPRS_PER_GRP_BITS)
  36 #define SPRGROUP_MAC    (5 << MAX_SPRS_PER_GRP_BITS)
  37 #define SPRGROUP_D      (6 << MAX_SPRS_PER_GRP_BITS)
  38 #define SPRGROUP_PC     (7 << MAX_SPRS_PER_GRP_BITS)
  39 #define SPRGROUP_PM     (8 << MAX_SPRS_PER_GRP_BITS)
  40 #define SPRGROUP_PIC    (9 << MAX_SPRS_PER_GRP_BITS)
  41 #define SPRGROUP_TT     (10 << MAX_SPRS_PER_GRP_BITS)
  42 #define SPRGROUP_FP     (11 << MAX_SPRS_PER_GRP_BITS)
  43
  44 /* System control and status group */
  45 #define SPR_VR          (SPRGROUP_SYS + 0)
  46 #define SPR_UPR         (SPRGROUP_SYS + 1)
  47 #define SPR_CPUCFGR     (SPRGROUP_SYS + 2)
  48 #define SPR_DMMUCFGR    (SPRGROUP_SYS + 3)
  49 #define SPR_IMMUCFGR    (SPRGROUP_SYS + 4)
  50 #define SPR_DCCFGR      (SPRGROUP_SYS + 5)
  51 #define SPR_ICCFGR      (SPRGROUP_SYS + 6)
  52 #define SPR_DCFGR       (SPRGROUP_SYS + 7)
  53 #define SPR_PCCFGR      (SPRGROUP_SYS + 8)
  54 #define SPR_NPC         (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
  55 #define SPR_SR          (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
  56 #define SPR_PPC         (SPRGROUP_SYS + 18)  /* CZ 21/06/01 */
  57 #define SPR_FPCSR       (SPRGROUP_SYS + 20)  /* CZ 21/06/01 */
  58 #define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
  59 #define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
  60 #define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
  61 #define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
  62 #define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
  63 #define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
  64 #define SPR_GPR_BASE    (SPRGROUP_SYS + 1024)
  65
  66 /* Data MMU group */
  67 #define SPR_DMMUCR      (SPRGROUP_DMMU + 0)
  68 #define SPR_DTLBEIR     (SPRGROUP_DMMU + 2)
  69 #define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
  70 #define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
  71 #define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
  72 #define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
  73
  74 /* Instruction MMU group */
  75 #define SPR_IMMUCR      (SPRGROUP_IMMU + 0)
  76 #define SPR_ITLBEIR     (SPRGROUP_IMMU + 2)
  77 #define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
  78 #define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
  79 #define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
  80 #define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
  81
  82 /* Data cache group */
  83 #define SPR_DCCR        (SPRGROUP_DC + 0)
  84 #define SPR_DCBPR       (SPRGROUP_DC + 1)
  85 #define SPR_DCBFR       (SPRGROUP_DC + 2)
  86 #define SPR_DCBIR       (SPRGROUP_DC + 3)
  87 #define SPR_DCBWR       (SPRGROUP_DC + 4)
  88 #define SPR_DCBLR       (SPRGROUP_DC + 5)
  89 #define SPR_DCR_BASE(WAY)       (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
  90 #define SPR_DCR_LAST(WAY)       (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
  91
  92 /* Instruction cache group */
  93 #define SPR_ICCR        (SPRGROUP_IC + 0)
  94 #define SPR_ICBPR       (SPRGROUP_IC + 1)
  95 #define SPR_ICBIR       (SPRGROUP_IC + 2)
  96 #define SPR_ICBLR       (SPRGROUP_IC + 3)
  97 #define SPR_ICR_BASE(WAY)       (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
  98 #define SPR_ICR_LAST(WAY)       (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
  99
 100 /* MAC group */
 101 #define SPR_MACLO       (SPRGROUP_MAC + 1)
 102 #define SPR_MACHI       (SPRGROUP_MAC + 2)
 103
 104 /* Debug group */
 105 #define SPR_DVR(N)      (SPRGROUP_D + (N))
 106 #define SPR_DCR(N)      (SPRGROUP_D + 8 + (N))
 107 #define SPR_DMR1        (SPRGROUP_D + 16)
 108 #define SPR_DMR2        (SPRGROUP_D + 17)
 109 #define SPR_DWCR0       (SPRGROUP_D + 18)
 110 #define SPR_DWCR1       (SPRGROUP_D + 19)
 111 #define SPR_DSR         (SPRGROUP_D + 20)
 112 #define SPR_DRR         (SPRGROUP_D + 21)
 113
 114 /* Performance counters group */
 115 #define SPR_PCCR(N)     (SPRGROUP_PC + (N))
 116 #define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))
 117
 118 /* Power management group */
 119 #define SPR_PMR (SPRGROUP_PM + 0)
 120
 121 /* PIC group */
 122 #define SPR_PICMR (SPRGROUP_PIC + 0)
 123 #define SPR_PICPR (SPRGROUP_PIC + 1)
 124 #define SPR_PICSR (SPRGROUP_PIC + 2)
 125
 126 /* Tick Timer group */
 127 #define SPR_TTMR (SPRGROUP_TT + 0)
 128 #define SPR_TTCR (SPRGROUP_TT + 1)
 129
 130 /*
 131  * Bit definitions for the Version Register
 132  *
 133  */
 134 #define SPR_VR_VER      0xff000000  /* Processor version */
 135 #define SPR_VR_CFG      0x00ff0000  /* Processor configuration */
 136 #define SPR_VR_RES      0x0000ffc0  /* Reserved */
 137 #define SPR_VR_REV      0x0000003f  /* Processor revision */
 138
 139 #define SPR_VR_VER_OFF  24
 140 #define SPR_VR_CFG_OFF  16
 141 #define SPR_VR_REV_OFF  0
 142
 143 /*
 144  * Bit definitions for the Unit Present Register
 145  *
 146  */
 147 #define SPR_UPR_UP         0x00000001  /* UPR present */
 148 #define SPR_UPR_DCP        0x00000002  /* Data cache present */
 149 #define SPR_UPR_ICP        0x00000004  /* Instruction cache present */
 150 #define SPR_UPR_DMP        0x00000008  /* Data MMU present */
 151 #define SPR_UPR_IMP        0x00000010  /* Instruction MMU present */
 152 #define SPR_UPR_MP         0x00000020  /* MAC present */
 153 #define SPR_UPR_DUP        0x00000040  /* Debug unit present */
 154 #define SPR_UPR_PCUP       0x00000080  /* Performance counters unit present */
 155 #define SPR_UPR_PMP        0x00000100  /* Power management present */
 156 #define SPR_UPR_PICP       0x00000200  /* PIC present */
 157 #define SPR_UPR_TTP        0x00000400  /* Tick timer present */
 158 #define SPR_UPR_RES        0x00fe0000  /* Reserved */
 159 #define SPR_UPR_CUP        0xff000000  /* Context units present */
 160
 161 /*
 162  * JPB: Bit definitions for the CPU configuration register
 163  *
 164  */
 165 #define SPR_CPUCFGR_NSGF   0x0000000f  /* Number of shadow GPR files */
 166 #define SPR_CPUCFGR_CGF    0x00000010  /* Custom GPR file */
 167 #define SPR_CPUCFGR_OB32S  0x00000020  /* ORBIS32 supported */
 168 #define SPR_CPUCFGR_OB64S  0x00000040  /* ORBIS64 supported */
 169 #define SPR_CPUCFGR_OF32S  0x00000080  /* ORFPX32 supported */
 170 #define SPR_CPUCFGR_OF64S  0x00000100  /* ORFPX64 supported */
 171 #define SPR_CPUCFGR_OV64S  0x00000200  /* ORVDX64 supported */
 172 #define SPR_CPUCFGR_RES    0xfffffc00  /* Reserved */
 173
 174 /*
 175  * JPB: Bit definitions for the Debug configuration register and other
 176  * constants.
 177  *
 178  */
 179
 180 #define SPR_DCFGR_NDP      0x00000007  /* Number of matchpoints mask */
 181 #define SPR_DCFGR_NDP1     0x00000000  /* One matchpoint supported */
 182 #define SPR_DCFGR_NDP2     0x00000001  /* Two matchpoints supported */
 183 #define SPR_DCFGR_NDP3     0x00000002  /* Three matchpoints supported */
 184 #define SPR_DCFGR_NDP4     0x00000003  /* Four matchpoints supported */
 185 #define SPR_DCFGR_NDP5     0x00000004  /* Five matchpoints supported */
 186 #define SPR_DCFGR_NDP6     0x00000005  /* Six matchpoints supported */
 187 #define SPR_DCFGR_NDP7     0x00000006  /* Seven matchpoints supported */
 188 #define SPR_DCFGR_NDP8     0x00000007  /* Eight matchpoints supported */
 189 #define SPR_DCFGR_WPCI     0x00000008  /* Watchpoint counters implemented */
 190
 191 #define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
 192                                2 == n ? SPR_DCFGR_NDP2 : \
 193                                3 == n ? SPR_DCFGR_NDP3 : \
 194                                4 == n ? SPR_DCFGR_NDP4 : \
 195                                5 == n ? SPR_DCFGR_NDP5 : \
 196                                6 == n ? SPR_DCFGR_NDP6 : \
 197                                7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
 198 #define MAX_MATCHPOINTS  8
 199 #define MAX_WATCHPOINTS  (MAX_MATCHPOINTS + 2)
 200
 201 /*
 202  * Bit definitions for the Supervision Register
 203  *
 204  */
 205 #define SPR_SR_SM          0x00000001  /* Supervisor Mode */
 206 #define SPR_SR_TEE         0x00000002  /* Tick timer Exception Enable */
 207 #define SPR_SR_IEE         0x00000004  /* Interrupt Exception Enable */
 208 #define SPR_SR_DCE         0x00000008  /* Data Cache Enable */
 209 #define SPR_SR_ICE         0x00000010  /* Instruction Cache Enable */
 210 #define SPR_SR_DME         0x00000020  /* Data MMU Enable */
 211 #define SPR_SR_IME         0x00000040  /* Instruction MMU Enable */
 212 #define SPR_SR_LEE         0x00000080  /* Little Endian Enable */
 213 #define SPR_SR_CE          0x00000100  /* CID Enable */
 214 #define SPR_SR_F           0x00000200  /* Condition Flag */
 215 #define SPR_SR_CY          0x00000400  /* Carry flag */
 216 #define SPR_SR_OV          0x00000800  /* Overflow flag */
 217 #define SPR_SR_OVE         0x00001000  /* Overflow flag Exception */
 218 #define SPR_SR_DSX         0x00002000  /* Delay Slot Exception */
 219 #define SPR_SR_EPH         0x00004000  /* Exception Prefix High */
 220 #define SPR_SR_FO          0x00008000  /* Fixed one */
 221 #define SPR_SR_SUMRA       0x00010000  /* Supervisor SPR read access */
 222 #define SPR_SR_RES         0x0ffe0000  /* Reserved */
 223 #define SPR_SR_CID         0xf0000000  /* Context ID */
 224
 225 /*
 226  * Bit definitions for the Data MMU Control Register
 227  *
 228  */
 229 #define SPR_DMMUCR_P2S     0x0000003e  /* Level 2 Page Size */
 230 #define SPR_DMMUCR_P1S     0x000007c0  /* Level 1 Page Size */
 231 #define SPR_DMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
 232 #define SPR_DMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
 233
 234 /*
 235  * Bit definitions for the Instruction MMU Control Register
 236  *
 237  */
 238 #define SPR_IMMUCR_P2S     0x0000003e  /* Level 2 Page Size */
 239 #define SPR_IMMUCR_P1S     0x000007c0  /* Level 1 Page Size */
 240 #define SPR_IMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
 241 #define SPR_IMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
 242
 243 /*
 244  * Bit definitions for the Data TLB Match Register
 245  *
 246  */
 247 #define SPR_DTLBMR_V       0x00000001  /* Valid */
 248 #define SPR_DTLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
 249 #define SPR_DTLBMR_CID     0x0000003c  /* Context ID */
 250 #define SPR_DTLBMR_LRU     0x000000c0  /* Least Recently Used */
 251 #define SPR_DTLBMR_VPN     0xfffff000  /* Virtual Page Number */
 252
 253 /*
 254  * Bit definitions for the Data TLB Translate Register
 255  *
 256  */
 257 #define SPR_DTLBTR_CC      0x00000001  /* Cache Coherency */
 258 #define SPR_DTLBTR_CI      0x00000002  /* Cache Inhibit */
 259 #define SPR_DTLBTR_WBC     0x00000004  /* Write-Back Cache */
 260 #define SPR_DTLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
 261 #define SPR_DTLBTR_A       0x00000010  /* Accessed */
 262 #define SPR_DTLBTR_D       0x00000020  /* Dirty */
 263 #define SPR_DTLBTR_URE     0x00000040  /* User Read Enable */
 264 #define SPR_DTLBTR_UWE     0x00000080  /* User Write Enable */
 265 #define SPR_DTLBTR_SRE     0x00000100  /* Supervisor Read Enable */
 266 #define SPR_DTLBTR_SWE     0x00000200  /* Supervisor Write Enable */
 267 #define SPR_DTLBTR_PPN     0xfffff000  /* Physical Page Number */
 268
 269 /*
 270  * Bit definitions for the Instruction TLB Match Register
 271  *
 272  */
 273 #define SPR_ITLBMR_V       0x00000001  /* Valid */
 274 #define SPR_ITLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
 275 #define SPR_ITLBMR_CID     0x0000003c  /* Context ID */
 276 #define SPR_ITLBMR_LRU     0x000000c0  /* Least Recently Used */
 277 #define SPR_ITLBMR_VPN     0xfffff000  /* Virtual Page Number */
 278
 279 /*
 280  * Bit definitions for the Instruction TLB Translate Register
 281  *
 282  */
 283 #define SPR_ITLBTR_CC      0x00000001  /* Cache Coherency */
 284 #define SPR_ITLBTR_CI      0x00000002  /* Cache Inhibit */
 285 #define SPR_ITLBTR_WBC     0x00000004  /* Write-Back Cache */
 286 #define SPR_ITLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
 287 #define SPR_ITLBTR_A       0x00000010  /* Accessed */
 288 #define SPR_ITLBTR_D       0x00000020  /* Dirty */
 289 #define SPR_ITLBTR_SXE     0x00000040  /* User Read Enable */
 290 #define SPR_ITLBTR_UXE     0x00000080  /* User Write Enable */
 291 #define SPR_ITLBTR_PPN     0xfffff000  /* Physical Page Number */
 292
 293 /*
 294  * Bit definitions for Data Cache Control register
 295  *
 296  */
 297 #define SPR_DCCR_EW        0x000000ff  /* Enable ways */
 298
 299 /*
 300  * Bit definitions for Insn Cache Control register
 301  *
 302  */
 303 #define SPR_ICCR_EW        0x000000ff  /* Enable ways */
 304
 305 /*
 306  * Bit definitions for Data Cache Configuration Register
 307  *
 308  */
 309
 310 #define SPR_DCCFGR_NCW          0x00000007
 311 #define SPR_DCCFGR_NCS          0x00000078
 312 #define SPR_DCCFGR_CBS          0x00000080
 313 #define SPR_DCCFGR_CWS          0x00000100
 314 #define SPR_DCCFGR_CCRI         0x00000200
 315 #define SPR_DCCFGR_CBIRI        0x00000400
 316 #define SPR_DCCFGR_CBPRI        0x00000800
 317 #define SPR_DCCFGR_CBLRI        0x00001000
 318 #define SPR_DCCFGR_CBFRI        0x00002000
 319 #define SPR_DCCFGR_CBWBRI       0x00004000
 320
 321 #define SPR_DCCFGR_NCW_OFF      0
 322 #define SPR_DCCFGR_NCS_OFF      3
 323 #define SPR_DCCFGR_CBS_OFF      7
 324
 325 /*
 326  * Bit definitions for Instruction Cache Configuration Register
 327  *
 328  */
 329 #define SPR_ICCFGR_NCW          0x00000007
 330 #define SPR_ICCFGR_NCS          0x00000078
 331 #define SPR_ICCFGR_CBS          0x00000080
 332 #define SPR_ICCFGR_CCRI         0x00000200
 333 #define SPR_ICCFGR_CBIRI        0x00000400
 334 #define SPR_ICCFGR_CBPRI        0x00000800
 335 #define SPR_ICCFGR_CBLRI        0x00001000
 336
 337 #define SPR_ICCFGR_NCW_OFF      0
 338 #define SPR_ICCFGR_NCS_OFF      3
 339 #define SPR_ICCFGR_CBS_OFF      7
 340
 341 /*
 342  * Bit definitions for Data MMU Configuration Register
 343  *
 344  */
 345
 346 #define SPR_DMMUCFGR_NTW        0x00000003
 347 #define SPR_DMMUCFGR_NTS        0x0000001C
 348 #define SPR_DMMUCFGR_NAE        0x000000E0
 349 #define SPR_DMMUCFGR_CRI        0x00000100
 350 #define SPR_DMMUCFGR_PRI        0x00000200
 351 #define SPR_DMMUCFGR_TEIRI      0x00000400
 352 #define SPR_DMMUCFGR_HTR        0x00000800
 353
 354 #define SPR_DMMUCFGR_NTW_OFF    0
 355 #define SPR_DMMUCFGR_NTS_OFF    2
 356
 357 /*
 358  * Bit definitions for Instruction MMU Configuration Register
 359  *
 360  */
 361
 362 #define SPR_IMMUCFGR_NTW        0x00000003
 363 #define SPR_IMMUCFGR_NTS        0x0000001C
 364 #define SPR_IMMUCFGR_NAE        0x000000E0
 365 #define SPR_IMMUCFGR_CRI        0x00000100
 366 #define SPR_IMMUCFGR_PRI        0x00000200
 367 #define SPR_IMMUCFGR_TEIRI      0x00000400
 368 #define SPR_IMMUCFGR_HTR        0x00000800
 369
 370 #define SPR_IMMUCFGR_NTW_OFF    0
 371 #define SPR_IMMUCFGR_NTS_OFF    2
 372
 373 /*
 374  * Bit definitions for Debug Control registers
 375  *
 376  */
 377 #define SPR_DCR_DP      0x00000001  /* DVR/DCR present */
 378 #define SPR_DCR_CC      0x0000000e  /* Compare condition */
 379 #define SPR_DCR_SC      0x00000010  /* Signed compare */
 380 #define SPR_DCR_CT      0x000000e0  /* Compare to */
 381
 382 /* Bit results with SPR_DCR_CC mask */
 383 #define SPR_DCR_CC_MASKED 0x00000000
 384 #define SPR_DCR_CC_EQUAL  0x00000002
 385 #define SPR_DCR_CC_LESS   0x00000004
 386 #define SPR_DCR_CC_LESSE  0x00000006
 387 #define SPR_DCR_CC_GREAT  0x00000008
 388 #define SPR_DCR_CC_GREATE 0x0000000a
 389 #define SPR_DCR_CC_NEQUAL 0x0000000c
 390
 391 /* Bit results with SPR_DCR_CT mask */
 392 #define SPR_DCR_CT_DISABLED 0x00000000
 393 #define SPR_DCR_CT_IFEA     0x00000020
 394 #define SPR_DCR_CT_LEA      0x00000040
 395 #define SPR_DCR_CT_SEA      0x00000060
 396 #define SPR_DCR_CT_LD       0x00000080
 397 #define SPR_DCR_CT_SD       0x000000a0
 398 #define SPR_DCR_CT_LSEA     0x000000c0
 399 #define SPR_DCR_CT_LSD      0x000000e0
 400 /* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
 401
 402 /*
 403  * Bit definitions for Debug Mode 1 register
 404  *
 405  */
 406 #define SPR_DMR1_CW       0x000fffff  /* Chain register pair data */
 407 #define SPR_DMR1_CW0_AND  0x00000001
 408 #define SPR_DMR1_CW0_OR   0x00000002
 409 #define SPR_DMR1_CW0      (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
 410 #define SPR_DMR1_CW1_AND  0x00000004
 411 #define SPR_DMR1_CW1_OR   0x00000008
 412 #define SPR_DMR1_CW1      (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
 413 #define SPR_DMR1_CW2_AND  0x00000010
 414 #define SPR_DMR1_CW2_OR   0x00000020
 415 #define SPR_DMR1_CW2      (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
 416 #define SPR_DMR1_CW3_AND  0x00000040
 417 #define SPR_DMR1_CW3_OR   0x00000080
 418 #define SPR_DMR1_CW3      (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
 419 #define SPR_DMR1_CW4_AND  0x00000100
 420 #define SPR_DMR1_CW4_OR   0x00000200
 421 #define SPR_DMR1_CW4      (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
 422 #define SPR_DMR1_CW5_AND  0x00000400
 423 #define SPR_DMR1_CW5_OR   0x00000800
 424 #define SPR_DMR1_CW5      (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
 425 #define SPR_DMR1_CW6_AND  0x00001000
 426 #define SPR_DMR1_CW6_OR   0x00002000
 427 #define SPR_DMR1_CW6      (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
 428 #define SPR_DMR1_CW7_AND  0x00004000
 429 #define SPR_DMR1_CW7_OR   0x00008000
 430 #define SPR_DMR1_CW7      (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
 431 #define SPR_DMR1_CW8_AND  0x00010000
 432 #define SPR_DMR1_CW8_OR   0x00020000
 433 #define SPR_DMR1_CW8      (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
 434 #define SPR_DMR1_CW9_AND  0x00040000
 435 #define SPR_DMR1_CW9_OR   0x00080000
 436 #define SPR_DMR1_CW9      (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
 437 #define SPR_DMR1_RES1      0x00300000  /* Reserved */
 438 #define SPR_DMR1_ST       0x00400000  /* Single-step trace*/
 439 #define SPR_DMR1_BT       0x00800000  /* Branch trace */
 440 #define SPR_DMR1_RES2     0xff000000  /* Reserved */
 441
 442 /*
 443  * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
 444  *
 445  */
 446 #define SPR_DMR2_WCE0      0x00000001  /* Watchpoint counter 0 enable */
 447 #define SPR_DMR2_WCE1      0x00000002  /* Watchpoint counter 0 enable */
 448 #define SPR_DMR2_AWTC      0x00000ffc  /* Assign watchpoints to counters */
 449 #define SPR_DMR2_AWTC_OFF           2  /* Bit offset to AWTC field */
 450 #define SPR_DMR2_WGB       0x003ff000  /* Watchpoints generating breakpoint */
 451 #define SPR_DMR2_WGB_OFF           12  /* Bit offset to WGB field */
 452 #define SPR_DMR2_WBS       0xffc00000  /* JPB: Watchpoint status */
 453 #define SPR_DMR2_WBS_OFF           22  /* Bit offset to WBS field */
 454
 455 /*
 456  * Bit definitions for Debug watchpoint counter registers
 457  *
 458  */
 459 #define SPR_DWCR_COUNT      0x0000ffff  /* Count */
 460 #define SPR_DWCR_MATCH      0xffff0000  /* Match */
 461 #define SPR_DWCR_MATCH_OFF          16  /* Match bit offset */
 462
 463 /*
 464  * Bit definitions for Debug stop register
 465  *
 466  */
 467 #define SPR_DSR_RSTE    0x00000001  /* Reset exception */
 468 #define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */
 469 #define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */
 470 #define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */
 471 #define SPR_DSR_TTE     0x00000010  /* Tick Timer exception */
 472 #define SPR_DSR_AE      0x00000020  /* Alignment exception */
 473 #define SPR_DSR_IIE     0x00000040  /* Illegal Instruction exception */
 474 #define SPR_DSR_IE      0x00000080  /* Interrupt exception */
 475 #define SPR_DSR_DME     0x00000100  /* DTLB miss exception */
 476 #define SPR_DSR_IME     0x00000200  /* ITLB miss exception */
 477 #define SPR_DSR_RE      0x00000400  /* Range exception */
 478 #define SPR_DSR_SCE     0x00000800  /* System call exception */
 479 #define SPR_DSR_FPE     0x00001000  /* Floating Point Exception */
 480 #define SPR_DSR_TE      0x00002000  /* Trap exception */
 481
 482 /*
 483  * Bit definitions for Debug reason register
 484  *
 485  */
 486 #define SPR_DRR_RSTE    0x00000001  /* Reset exception */
 487 #define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */
 488 #define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */
 489 #define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */
 490 #define SPR_DRR_TTE     0x00000010  /* Tick Timer exception */
 491 #define SPR_DRR_AE      0x00000020  /* Alignment exception */
 492 #define SPR_DRR_IIE     0x00000040  /* Illegal Instruction exception */
 493 #define SPR_DRR_IE      0x00000080  /* Interrupt exception */
 494 #define SPR_DRR_DME     0x00000100  /* DTLB miss exception */
 495 #define SPR_DRR_IME     0x00000200  /* ITLB miss exception */
 496 #define SPR_DRR_RE      0x00000400  /* Range exception */
 497 #define SPR_DRR_SCE     0x00000800  /* System call exception */
 498 #define SPR_DRR_FPE     0x00001000  /* Floating Point Exception */
 499 #define SPR_DRR_TE      0x00002000  /* Trap exception */
 500
 501 /*
 502  * Bit definitions for Performance counters mode registers
 503  *
 504  */
 505 #define SPR_PCMR_CP     0x00000001  /* Counter present */
 506 #define SPR_PCMR_UMRA   0x00000002  /* User mode read access */
 507 #define SPR_PCMR_CISM   0x00000004  /* Count in supervisor mode */
 508 #define SPR_PCMR_CIUM   0x00000008  /* Count in user mode */
 509 #define SPR_PCMR_LA     0x00000010  /* Load access event */
 510 #define SPR_PCMR_SA     0x00000020  /* Store access event */
 511 #define SPR_PCMR_IF     0x00000040  /* Instruction fetch event*/
 512 #define SPR_PCMR_DCM    0x00000080  /* Data cache miss event */
 513 #define SPR_PCMR_ICM    0x00000100  /* Insn cache miss event */
 514 #define SPR_PCMR_IFS    0x00000200  /* Insn fetch stall event */
 515 #define SPR_PCMR_LSUS   0x00000400  /* LSU stall event */
 516 #define SPR_PCMR_BS     0x00000800  /* Branch stall event */
 517 #define SPR_PCMR_DTLBM  0x00001000  /* DTLB miss event */
 518 #define SPR_PCMR_ITLBM  0x00002000  /* ITLB miss event */
 519 #define SPR_PCMR_DDS    0x00004000  /* Data dependency stall event */
 520 #define SPR_PCMR_WPE    0x03ff8000  /* Watchpoint events */
 521
 522 /*
 523  * Bit definitions for the Power management register
 524  *
 525  */
 526 #define SPR_PMR_SDF     0x0000000f  /* Slow down factor */
 527 #define SPR_PMR_DME     0x00000010  /* Doze mode enable */
 528 #define SPR_PMR_SME     0x00000020  /* Sleep mode enable */
 529 #define SPR_PMR_DCGE    0x00000040  /* Dynamic clock gating enable */
 530 #define SPR_PMR_SUME    0x00000080  /* Suspend mode enable */
 531
 532 /*
 533  * Bit definitions for PICMR
 534  *
 535  */
 536 #define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
 537
 538 /*
 539  * Bit definitions for PICPR
 540  *
 541  */
 542 #define SPR_PICPR_IPRIO 0xfffffffc  /* Interrupt priority */
 543
 544 /*
 545  * Bit definitions for PICSR
 546  *
 547  */
 548 #define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
 549
 550 /*
 551  * Bit definitions for Tick Timer Control Register
 552  *
 553  */
 554
 555 #define SPR_TTCR_CNT    0xffffffff  /* Count, time period */
 556 #define SPR_TTMR_TP     0x0fffffff  /* Time period */
 557 #define SPR_TTMR_IP     0x10000000  /* Interrupt Pending */
 558 #define SPR_TTMR_IE     0x20000000  /* Interrupt Enable */
 559 #define SPR_TTMR_DI     0x00000000  /* Disabled */
 560 #define SPR_TTMR_RT     0x40000000  /* Restart tick */
 561 #define SPR_TTMR_SR     0x80000000  /* Single run */
 562 #define SPR_TTMR_CR     0xc0000000  /* Continuous run */
 563 #define SPR_TTMR_M      0xc0000000  /* Tick mode */
 564
 565 /*
 566  * Bit definitions for the FP Control Status Register
 567  *
 568  */
 569 #define SPR_FPCSR_FPEE  0x00000001  /* Floating Point Exception Enable */
 570 #define SPR_FPCSR_RM    0x00000006  /* Rounding Mode */
 571 #define SPR_FPCSR_OVF   0x00000008  /* Overflow Flag */
 572 #define SPR_FPCSR_UNF   0x00000010  /* Underflow Flag */
 573 #define SPR_FPCSR_SNF   0x00000020  /* SNAN Flag */
 574 #define SPR_FPCSR_QNF   0x00000040  /* QNAN Flag */
 575 #define SPR_FPCSR_ZF    0x00000080  /* Zero Flag */
 576 #define SPR_FPCSR_IXF   0x00000100  /* Inexact Flag */
 577 #define SPR_FPCSR_IVF   0x00000200  /* Invalid Flag */
 578 #define SPR_FPCSR_INF   0x00000400  /* Infinity Flag */
 579 #define SPR_FPCSR_DZF   0x00000800  /* Divide By Zero Flag */
 580 #define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
 581                         SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF |  \
 582                         SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
 583
 584 #define FPCSR_RM_RN (0<<1)
 585 #define FPCSR_RM_RZ (1<<1)
 586 #define FPCSR_RM_RIP (2<<1)
 587 #define FPCSR_RM_RIN (3<<1)
 588
 589 /*
 590  * l.nop constants
 591  *
 592  */
 593 #define NOP_NOP          0x0000      /* Normal nop instruction */
 594 #define NOP_EXIT         0x0001      /* End of simulation */
 595 #define NOP_REPORT       0x0002      /* Simple report */
 596 /*#define NOP_PRINTF       0x0003       Simprintf instruction (obsolete)*/
 597 #define NOP_PUTC         0x0004      /* JPB: Simputc instruction */
 598 #define NOP_CNT_RESET    0x0005      /* Reset statistics counters */
 599 #define NOP_GET_TICKS    0x0006      /* JPB: Get # ticks running */
 600 #define NOP_GET_PS       0x0007      /* JPB: Get picosecs/cycle */
 601 #define NOP_REPORT_FIRST 0x0400      /* Report with number */
 602 #define NOP_REPORT_LAST  0x03ff      /* Report with number */
 603
 604 #endif  /* SPR_DEFS__H */