drivers/fpga/altera-cvp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * FPGA Manager Driver for Altera Arria/Cyclone/Stratix CvP
   4  *
   5  * Copyright (C) 2017 DENX Software Engineering
   6  *
   7  * Anatolij Gustschin <agust@denx.de>
   8  *
   9  * Manage Altera FPGA firmware using PCIe CvP.
  10  * Firmware must be in binary "rbf" format.
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/fpga/fpga-mgr.h>
  16 #include <linux/module.h>
  17 #include <linux/pci.h>
  18 #include <linux/sizes.h>
  19
  20 #define CVP_BAR         0       /* BAR used for data transfer in memory mode */
  21 #define CVP_DUMMY_WR    244     /* dummy writes to clear CvP state machine */
  22 #define TIMEOUT_US      2000    /* CVP STATUS timeout for USERMODE polling */
  23
  24 /* Vendor Specific Extended Capability Registers */
  25 #define VSE_PCIE_EXT_CAP_ID             0x200
  26 #define VSE_PCIE_EXT_CAP_ID_VAL         0x000b  /* 16bit */
  27
  28 #define VSE_CVP_STATUS                  0x21c   /* 32bit */
  29 #define VSE_CVP_STATUS_CFG_RDY          BIT(18) /* CVP_CONFIG_READY */
  30 #define VSE_CVP_STATUS_CFG_ERR          BIT(19) /* CVP_CONFIG_ERROR */
  31 #define VSE_CVP_STATUS_CVP_EN           BIT(20) /* ctrl block is enabling CVP */
  32 #define VSE_CVP_STATUS_USERMODE         BIT(21) /* USERMODE */
  33 #define VSE_CVP_STATUS_CFG_DONE         BIT(23) /* CVP_CONFIG_DONE */
  34 #define VSE_CVP_STATUS_PLD_CLK_IN_USE   BIT(24) /* PLD_CLK_IN_USE */
  35
  36 #define VSE_CVP_MODE_CTRL               0x220   /* 32bit */
  37 #define VSE_CVP_MODE_CTRL_CVP_MODE      BIT(0)  /* CVP (1) or normal mode (0) */
  38 #define VSE_CVP_MODE_CTRL_HIP_CLK_SEL   BIT(1) /* PMA (1) or fabric clock (0) */
  39 #define VSE_CVP_MODE_CTRL_NUMCLKS_OFF   8       /* NUMCLKS bits offset */
  40 #define VSE_CVP_MODE_CTRL_NUMCLKS_MASK  GENMASK(15, 8)
  41
  42 #define VSE_CVP_DATA                    0x228   /* 32bit */
  43 #define VSE_CVP_PROG_CTRL               0x22c   /* 32bit */
  44 #define VSE_CVP_PROG_CTRL_CONFIG        BIT(0)
  45 #define VSE_CVP_PROG_CTRL_START_XFER    BIT(1)
  46
  47 #define VSE_UNCOR_ERR_STATUS            0x234   /* 32bit */
  48 #define VSE_UNCOR_ERR_CVP_CFG_ERR       BIT(5)  /* CVP_CONFIG_ERROR_LATCHED */
  49
  50 #define DRV_NAME                "altera-cvp"
  51 #define ALTERA_CVP_MGR_NAME     "Altera CvP FPGA Manager"
  52
  53 /* Optional CvP config error status check for debugging */
  54 static bool altera_cvp_chkcfg;
  55
  56 struct altera_cvp_conf {
  57         struct fpga_manager     *mgr;
  58         struct pci_dev          *pci_dev;
  59         void __iomem            *map;
  60         void                    (*write_data)(struct altera_cvp_conf *, u32);
  61         char                    mgr_name[64];
  62         u8                      numclks;
  63 };
  64
  65 static enum fpga_mgr_states altera_cvp_state(struct fpga_manager *mgr)
  66 {
  67         struct altera_cvp_conf *conf = mgr->priv;
  68         u32 status;
  69
  70         pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &status);
  71
  72         if (status & VSE_CVP_STATUS_CFG_DONE)
  73                 return FPGA_MGR_STATE_OPERATING;
  74
  75         if (status & VSE_CVP_STATUS_CVP_EN)
  76                 return FPGA_MGR_STATE_POWER_UP;
  77
  78         return FPGA_MGR_STATE_UNKNOWN;
  79 }
  80
  81 static void altera_cvp_write_data_iomem(struct altera_cvp_conf *conf, u32 val)
  82 {
  83         writel(val, conf->map);
  84 }
  85
  86 static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val)
  87 {
  88         pci_write_config_dword(conf->pci_dev, VSE_CVP_DATA, val);
  89 }
  90
  91 /* switches between CvP clock and internal clock */
  92 static void altera_cvp_dummy_write(struct altera_cvp_conf *conf)
  93 {
  94         unsigned int i;
  95         u32 val;
  96
  97         /* set 1 CVP clock cycle for every CVP Data Register Write */
  98         pci_read_config_dword(conf->pci_dev, VSE_CVP_MODE_CTRL, &val);
  99         val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
 100         val |= 1 << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
 101         pci_write_config_dword(conf->pci_dev, VSE_CVP_MODE_CTRL, val);
 102
 103         for (i = 0; i < CVP_DUMMY_WR; i++)
 104                 conf->write_data(conf, 0); /* dummy data, could be any value */
 105 }
 106
 107 static int altera_cvp_wait_status(struct altera_cvp_conf *conf, u32 status_mask,
 108                                   u32 status_val, int timeout_us)
 109 {
 110         unsigned int retries;
 111         u32 val;
 112
 113         retries = timeout_us / 10;
 114         if (timeout_us % 10)
 115                 retries++;
 116
 117         do {
 118                 pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &val);
 119                 if ((val & status_mask) == status_val)
 120                         return 0;
 121
 122                 /* use small usleep value to re-check and break early */
 123                 usleep_range(10, 11);
 124         } while (--retries);
 125
 126         return -ETIMEDOUT;
 127 }
 128
 129 static int altera_cvp_teardown(struct fpga_manager *mgr,
 130                                struct fpga_image_info *info)
 131 {
 132         struct altera_cvp_conf *conf = mgr->priv;
 133         struct pci_dev *pdev = conf->pci_dev;
 134         int ret;
 135         u32 val;
 136
 137         /* STEP 12 - reset START_XFER bit */
 138         pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val);
 139         val &= ~VSE_CVP_PROG_CTRL_START_XFER;
 140         pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val);
 141
 142         /* STEP 13 - reset CVP_CONFIG bit */
 143         val &= ~VSE_CVP_PROG_CTRL_CONFIG;
 144         pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val);
 145
 146         /*
 147          * STEP 14
 148          * - set CVP_NUMCLKS to 1 and then issue CVP_DUMMY_WR dummy
 149          *   writes to the HIP
 150          */
 151         altera_cvp_dummy_write(conf); /* from CVP clock to internal clock */
 152
 153         /* STEP 15 - poll CVP_CONFIG_READY bit for 0 with 10us timeout */
 154         ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0, 10);
 155         if (ret)
 156                 dev_err(&mgr->dev, "CFG_RDY == 0 timeout\n");
 157
 158         return ret;
 159 }
 160
 161 static int altera_cvp_write_init(struct fpga_manager *mgr,
 162                                  struct fpga_image_info *info,
 163                                  const char *buf, size_t count)
 164 {
 165         struct altera_cvp_conf *conf = mgr->priv;
 166         struct pci_dev *pdev = conf->pci_dev;
 167         u32 iflags, val;
 168         int ret;
 169
 170         iflags = info ? info->flags : 0;
 171
 172         if (iflags & FPGA_MGR_PARTIAL_RECONFIG) {
 173                 dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
 174                 return -EINVAL;
 175         }
 176
 177         /* Determine allowed clock to data ratio */
 178         if (iflags & FPGA_MGR_COMPRESSED_BITSTREAM)
 179                 conf->numclks = 8; /* ratio for all compressed images */
 180         else if (iflags & FPGA_MGR_ENCRYPTED_BITSTREAM)
 181                 conf->numclks = 4; /* for uncompressed and encrypted images */
 182         else
 183                 conf->numclks = 1; /* for uncompressed and unencrypted images */
 184
 185         /* STEP 1 - read CVP status and check CVP_EN flag */
 186         pci_read_config_dword(pdev, VSE_CVP_STATUS, &val);
 187         if (!(val & VSE_CVP_STATUS_CVP_EN)) {
 188                 dev_err(&mgr->dev, "CVP mode off: 0x%04x\n", val);
 189                 return -ENODEV;
 190         }
 191
 192         if (val & VSE_CVP_STATUS_CFG_RDY) {
 193                 dev_warn(&mgr->dev, "CvP already started, teardown first\n");
 194                 ret = altera_cvp_teardown(mgr, info);
 195                 if (ret)
 196                         return ret;
 197         }
 198
 199         /*
 200          * STEP 2
 201          * - set HIP_CLK_SEL and CVP_MODE (must be set in the order mentioned)
 202          */
 203         /* switch from fabric to PMA clock */
 204         pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val);
 205         val |= VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
 206         pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val);
 207
 208         /* set CVP mode */
 209         pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val);
 210         val |= VSE_CVP_MODE_CTRL_CVP_MODE;
 211         pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val);
 212
 213         /*
 214          * STEP 3
 215          * - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
 216          */
 217         altera_cvp_dummy_write(conf);
 218
 219         /* STEP 4 - set CVP_CONFIG bit */
 220         pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val);
 221         /* request control block to begin transfer using CVP */
 222         val |= VSE_CVP_PROG_CTRL_CONFIG;
 223         pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val);
 224
 225         /* STEP 5 - poll CVP_CONFIG READY for 1 with 10us timeout */
 226         ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY,
 227                                      VSE_CVP_STATUS_CFG_RDY, 10);
 228         if (ret) {
 229                 dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
 230                 return ret;
 231         }
 232
 233         /*
 234          * STEP 6
 235          * - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
 236          */
 237         altera_cvp_dummy_write(conf);
 238
 239         /* STEP 7 - set START_XFER */
 240         pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val);
 241         val |= VSE_CVP_PROG_CTRL_START_XFER;
 242         pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val);
 243
 244         /* STEP 8 - start transfer (set CVP_NUMCLKS for bitstream) */
 245         pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val);
 246         val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
 247         val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
 248         pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val);
 249
 250         return 0;
 251 }
 252
 253 static inline int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
 254 {
 255         struct altera_cvp_conf *conf = mgr->priv;
 256         u32 val;
 257
 258         /* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */
 259         pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &val);
 260         if (val & VSE_CVP_STATUS_CFG_ERR) {
 261                 dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n",
 262                         bytes);
 263                 return -EPROTO;
 264         }
 265         return 0;
 266 }
 267
 268 static int altera_cvp_write(struct fpga_manager *mgr, const char *buf,
 269                             size_t count)
 270 {
 271         struct altera_cvp_conf *conf = mgr->priv;
 272         const u32 *data;
 273         size_t done, remaining;
 274         int status = 0;
 275         u32 mask;
 276
 277         /* STEP 9 - write 32-bit data from RBF file to CVP data register */
 278         data = (u32 *)buf;
 279         remaining = count;
 280         done = 0;
 281
 282         while (remaining >= 4) {
 283                 conf->write_data(conf, *data++);
 284                 done += 4;
 285                 remaining -= 4;
 286
 287                 /*
 288                  * STEP 10 (optional) and STEP 11
 289                  * - check error flag
 290                  * - loop until data transfer completed
 291                  * Config images can be huge (more than 40 MiB), so
 292                  * only check after a new 4k data block has been written.
 293                  * This reduces the number of checks and speeds up the
 294                  * configuration process.
 295                  */
 296                 if (altera_cvp_chkcfg && !(done % SZ_4K)) {
 297                         status = altera_cvp_chk_error(mgr, done);
 298                         if (status < 0)
 299                                 return status;
 300                 }
 301         }
 302
 303         /* write up to 3 trailing bytes, if any */
 304         mask = BIT(remaining * 8) - 1;
 305         if (mask)
 306                 conf->write_data(conf, *data & mask);
 307
 308         if (altera_cvp_chkcfg)
 309                 status = altera_cvp_chk_error(mgr, count);
 310
 311         return status;
 312 }
 313
 314 static int altera_cvp_write_complete(struct fpga_manager *mgr,
 315                                      struct fpga_image_info *info)
 316 {
 317         struct altera_cvp_conf *conf = mgr->priv;
 318         struct pci_dev *pdev = conf->pci_dev;
 319         int ret;
 320         u32 mask;
 321         u32 val;
 322
 323         ret = altera_cvp_teardown(mgr, info);
 324         if (ret)
 325                 return ret;
 326
 327         /* STEP 16 - check CVP_CONFIG_ERROR_LATCHED bit */
 328         pci_read_config_dword(pdev, VSE_UNCOR_ERR_STATUS, &val);
 329         if (val & VSE_UNCOR_ERR_CVP_CFG_ERR) {
 330                 dev_err(&mgr->dev, "detected CVP_CONFIG_ERROR_LATCHED!\n");
 331                 return -EPROTO;
 332         }
 333
 334         /* STEP 17 - reset CVP_MODE and HIP_CLK_SEL bit */
 335         pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val);
 336         val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
 337         val &= ~VSE_CVP_MODE_CTRL_CVP_MODE;
 338         pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val);
 339
 340         /* STEP 18 - poll PLD_CLK_IN_USE and USER_MODE bits */
 341         mask = VSE_CVP_STATUS_PLD_CLK_IN_USE | VSE_CVP_STATUS_USERMODE;
 342         ret = altera_cvp_wait_status(conf, mask, mask, TIMEOUT_US);
 343         if (ret)
 344                 dev_err(&mgr->dev, "PLD_CLK_IN_USE|USERMODE timeout\n");
 345
 346         return ret;
 347 }
 348
 349 static const struct fpga_manager_ops altera_cvp_ops = {
 350         .state          = altera_cvp_state,
 351         .write_init     = altera_cvp_write_init,
 352         .write          = altera_cvp_write,
 353         .write_complete = altera_cvp_write_complete,
 354 };
 355
 356 static ssize_t chkcfg_show(struct device_driver *dev, char *buf)
 357 {
 358         return snprintf(buf, 3, "%d\n", altera_cvp_chkcfg);
 359 }
 360
 361 static ssize_t chkcfg_store(struct device_driver *drv, const char *buf,
 362                             size_t count)
 363 {
 364         int ret;
 365
 366         ret = kstrtobool(buf, &altera_cvp_chkcfg);
 367         if (ret)
 368                 return ret;
 369
 370         return count;
 371 }
 372
 373 static DRIVER_ATTR_RW(chkcfg);
 374
 375 static int altera_cvp_probe(struct pci_dev *pdev,
 376                             const struct pci_device_id *dev_id);
 377 static void altera_cvp_remove(struct pci_dev *pdev);
 378
 379 static struct pci_device_id altera_cvp_id_tbl[] = {
 380         { PCI_VDEVICE(ALTERA, PCI_ANY_ID) },
 381         { }
 382 };
 383 MODULE_DEVICE_TABLE(pci, altera_cvp_id_tbl);
 384
 385 static struct pci_driver altera_cvp_driver = {
 386         .name   = DRV_NAME,
 387         .id_table = altera_cvp_id_tbl,
 388         .probe  = altera_cvp_probe,
 389         .remove = altera_cvp_remove,
 390 };
 391
 392 static int altera_cvp_probe(struct pci_dev *pdev,
 393                             const struct pci_device_id *dev_id)
 394 {
 395         struct altera_cvp_conf *conf;
 396         struct fpga_manager *mgr;
 397         u16 cmd, val;
 398         u32 regval;
 399         int ret;
 400
 401         /*
 402          * First check if this is the expected FPGA device. PCI config
 403          * space access works without enabling the PCI device, memory
 404          * space access is enabled further down.
 405          */
 406         pci_read_config_word(pdev, VSE_PCIE_EXT_CAP_ID, &val);
 407         if (val != VSE_PCIE_EXT_CAP_ID_VAL) {
 408                 dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val);
 409                 return -ENODEV;
 410         }
 411
 412         pci_read_config_dword(pdev, VSE_CVP_STATUS, &regval);
 413         if (!(regval & VSE_CVP_STATUS_CVP_EN)) {
 414                 dev_err(&pdev->dev,
 415                         "CVP is disabled for this device: CVP_STATUS Reg 0x%x\n",
 416                         regval);
 417                 return -ENODEV;
 418         }
 419
 420         conf = devm_kzalloc(&pdev->dev, sizeof(*conf), GFP_KERNEL);
 421         if (!conf)
 422                 return -ENOMEM;
 423
 424         /*
 425          * Enable memory BAR access. We cannot use pci_enable_device() here
 426          * because it will make the driver unusable with FPGA devices that
 427          * have additional big IOMEM resources (e.g. 4GiB BARs) on 32-bit
 428          * platform. Such BARs will not have an assigned address range and
 429          * pci_enable_device() will fail, complaining about not claimed BAR,
 430          * even if the concerned BAR is not needed for FPGA configuration
 431          * at all. Thus, enable the device via PCI config space command.
 432          */
 433         pci_read_config_word(pdev, PCI_COMMAND, &cmd);
 434         if (!(cmd & PCI_COMMAND_MEMORY)) {
 435                 cmd |= PCI_COMMAND_MEMORY;
 436                 pci_write_config_word(pdev, PCI_COMMAND, cmd);
 437         }
 438
 439         ret = pci_request_region(pdev, CVP_BAR, "CVP");
 440         if (ret) {
 441                 dev_err(&pdev->dev, "Requesting CVP BAR region failed\n");
 442                 goto err_disable;
 443         }
 444
 445         conf->pci_dev = pdev;
 446         conf->write_data = altera_cvp_write_data_iomem;
 447
 448         conf->map = pci_iomap(pdev, CVP_BAR, 0);
 449         if (!conf->map) {
 450                 dev_warn(&pdev->dev, "Mapping CVP BAR failed\n");
 451                 conf->write_data = altera_cvp_write_data_config;
 452         }
 453
 454         snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s @%s",
 455                  ALTERA_CVP_MGR_NAME, pci_name(pdev));
 456
 457         mgr = devm_fpga_mgr_create(&pdev->dev, conf->mgr_name,
 458                                    &altera_cvp_ops, conf);
 459         if (!mgr) {
 460                 ret = -ENOMEM;
 461                 goto err_unmap;
 462         }
 463
 464         pci_set_drvdata(pdev, mgr);
 465
 466         ret = fpga_mgr_register(mgr);
 467         if (ret)
 468                 goto err_unmap;
 469
 470         return 0;
 471
 472 err_unmap:
 473         if (conf->map)
 474                 pci_iounmap(pdev, conf->map);
 475         pci_release_region(pdev, CVP_BAR);
 476 err_disable:
 477         cmd &= ~PCI_COMMAND_MEMORY;
 478         pci_write_config_word(pdev, PCI_COMMAND, cmd);
 479         return ret;
 480 }
 481
 482 static void altera_cvp_remove(struct pci_dev *pdev)
 483 {
 484         struct fpga_manager *mgr = pci_get_drvdata(pdev);
 485         struct altera_cvp_conf *conf = mgr->priv;
 486         u16 cmd;
 487
 488         fpga_mgr_unregister(mgr);
 489         if (conf->map)
 490                 pci_iounmap(pdev, conf->map);
 491         pci_release_region(pdev, CVP_BAR);
 492         pci_read_config_word(pdev, PCI_COMMAND, &cmd);
 493         cmd &= ~PCI_COMMAND_MEMORY;
 494         pci_write_config_word(pdev, PCI_COMMAND, cmd);
 495 }
 496
 497 static int __init altera_cvp_init(void)
 498 {
 499         int ret;
 500
 501         ret = pci_register_driver(&altera_cvp_driver);
 502         if (ret)
 503                 return ret;
 504
 505         ret = driver_create_file(&altera_cvp_driver.driver,
 506                                  &driver_attr_chkcfg);
 507         if (ret)
 508                 pr_warn("Can't create sysfs chkcfg file\n");
 509
 510         return 0;
 511 }
 512
 513 static void __exit altera_cvp_exit(void)
 514 {
 515         driver_remove_file(&altera_cvp_driver.driver, &driver_attr_chkcfg);
 516         pci_unregister_driver(&altera_cvp_driver);
 517 }
 518
 519 module_init(altera_cvp_init);
 520 module_exit(altera_cvp_exit);
 521
 522 MODULE_LICENSE("GPL v2");
 523 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
 524 MODULE_DESCRIPTION("Module to load Altera FPGA over CvP");