?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
spi: sprd: adi: Add a reset reason for watchdog mode
[linux/fpc-iii.git] / drivers / pci / controller / pcie-mediatek.c
blob80601e1b939eba94f29daa8b5437e54f77b19947
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2017 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * Honghui Zhang <honghui.zhang@mediatek.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/msi.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/of_platform.h>
22 #include <linux/pci.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/reset.h>
27
28 #include "../pci.h"
29
30 /* PCIe shared registers */
31 #define PCIE_SYS_CFG 0x00
32 #define PCIE_INT_ENABLE 0x0c
33 #define PCIE_CFG_ADDR 0x20
34 #define PCIE_CFG_DATA 0x24
35
36 /* PCIe per port registers */
37 #define PCIE_BAR0_SETUP 0x10
38 #define PCIE_CLASS 0x34
39 #define PCIE_LINK_STATUS 0x50
40
41 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
42 #define PCIE_PORT_PERST(x) BIT(1 + (x))
43 #define PCIE_PORT_LINKUP BIT(0)
44 #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
45
46 #define PCIE_BAR_ENABLE BIT(0)
47 #define PCIE_REVISION_ID BIT(0)
48 #define PCIE_CLASS_CODE (0x60400 << 8)
49 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
50 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
51 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
52 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
53 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
54 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \
55 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
56 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
57
58 /* MediaTek specific configuration registers */
59 #define PCIE_FTS_NUM 0x70c
60 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
61 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
62
63 #define PCIE_FC_CREDIT 0x73c
64 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
65 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
66
67 /* PCIe V2 share registers */
68 #define PCIE_SYS_CFG_V2 0x0
69 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
70 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
71
72 /* PCIe V2 per-port registers */
73 #define PCIE_MSI_VECTOR 0x0c0
74
75 #define PCIE_CONF_VEND_ID 0x100
76 #define PCIE_CONF_CLASS_ID 0x106
77
78 #define PCIE_INT_MASK 0x420
79 #define INTX_MASK GENMASK(19, 16)
80 #define INTX_SHIFT 16
81 #define PCIE_INT_STATUS 0x424
82 #define MSI_STATUS BIT(23)
83 #define PCIE_IMSI_STATUS 0x42c
84 #define PCIE_IMSI_ADDR 0x430
85 #define MSI_MASK BIT(23)
86 #define MTK_MSI_IRQS_NUM 32
87
88 #define PCIE_AHB_TRANS_BASE0_L 0x438
89 #define PCIE_AHB_TRANS_BASE0_H 0x43c
90 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
91 #define PCIE_AXI_WINDOW0 0x448
92 #define WIN_ENABLE BIT(7)
93 /*
94 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
95 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
96 * start from 0x40000000).
97 */
98 #define PCIE2AHB_SIZE 0x21
99
100 /* PCIe V2 configuration transaction header */
101 #define PCIE_CFG_HEADER0 0x460
102 #define PCIE_CFG_HEADER1 0x464
103 #define PCIE_CFG_HEADER2 0x468
104 #define PCIE_CFG_WDATA 0x470
105 #define PCIE_APP_TLP_REQ 0x488
106 #define PCIE_CFG_RDATA 0x48c
107 #define APP_CFG_REQ BIT(0)
108 #define APP_CPL_STATUS GENMASK(7, 5)
109
110 #define CFG_WRRD_TYPE_0 4
111 #define CFG_WR_FMT 2
112 #define CFG_RD_FMT 0
113
114 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
115 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
116 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
117 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
118 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
119 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
120 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
121 #define CFG_HEADER_DW0(type, fmt) \
122 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
123 #define CFG_HEADER_DW1(where, size) \
124 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
125 #define CFG_HEADER_DW2(regn, fun, dev, bus) \
126 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
127 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
128
129 #define PCIE_RST_CTRL 0x510
130 #define PCIE_PHY_RSTB BIT(0)
131 #define PCIE_PIPE_SRSTB BIT(1)
132 #define PCIE_MAC_SRSTB BIT(2)
133 #define PCIE_CRSTB BIT(3)
134 #define PCIE_PERSTB BIT(8)
135 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
136 #define PCIE_LINK_STATUS_V2 0x804
137 #define PCIE_PORT_LINKUP_V2 BIT(10)
138
139 struct mtk_pcie_port;
140
141 /**
142 * struct mtk_pcie_soc - differentiate between host generations
143 * @need_fix_class_id: whether this host's class ID needed to be fixed or not
144 * @ops: pointer to configuration access functions
145 * @startup: pointer to controller setting functions
146 * @setup_irq: pointer to initialize IRQ functions
147 */
148 struct mtk_pcie_soc {
149 bool need_fix_class_id;
150 struct pci_ops *ops;
151 int (*startup)(struct mtk_pcie_port *port);
152 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
153 };
154
155 /**
156 * struct mtk_pcie_port - PCIe port information
157 * @base: IO mapped register base
158 * @list: port list
159 * @pcie: pointer to PCIe host info
160 * @reset: pointer to port reset control
161 * @sys_ck: pointer to transaction/data link layer clock
162 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
163 * and RC initiated MMIO access
164 * @axi_ck: pointer to application layer MMIO channel operating clock
165 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
166 * when pcie_mac_ck/pcie_pipe_ck is turned off
167 * @obff_ck: pointer to OBFF functional block operating clock
168 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
169 * @phy: pointer to PHY control block
170 * @slot: port slot
171 * @irq: GIC irq
172 * @irq_domain: legacy INTx IRQ domain
173 * @inner_domain: inner IRQ domain
174 * @msi_domain: MSI IRQ domain
175 * @lock: protect the msi_irq_in_use bitmap
176 * @msi_irq_in_use: bit map for assigned MSI IRQ
177 */
178 struct mtk_pcie_port {
179 void __iomem *base;
180 struct list_head list;
181 struct mtk_pcie *pcie;
182 struct reset_control *reset;
183 struct clk *sys_ck;
184 struct clk *ahb_ck;
185 struct clk *axi_ck;
186 struct clk *aux_ck;
187 struct clk *obff_ck;
188 struct clk *pipe_ck;
189 struct phy *phy;
190 u32 slot;
191 int irq;
192 struct irq_domain *irq_domain;
193 struct irq_domain *inner_domain;
194 struct irq_domain *msi_domain;
195 struct mutex lock;
196 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
197 };
198
199 /**
200 * struct mtk_pcie - PCIe host information
201 * @dev: pointer to PCIe device
202 * @base: IO mapped register base
203 * @free_ck: free-run reference clock
204 * @mem: non-prefetchable memory resource
205 * @ports: pointer to PCIe port information
206 * @soc: pointer to SoC-dependent operations
207 * @busnr: root bus number
208 */
209 struct mtk_pcie {
210 struct device *dev;
211 void __iomem *base;
212 struct clk *free_ck;
213
214 struct resource mem;
215 struct list_head ports;
216 const struct mtk_pcie_soc *soc;
217 unsigned int busnr;
218 };
219
220 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
221 {
222 struct device *dev = pcie->dev;
223
224 clk_disable_unprepare(pcie->free_ck);
225
226 pm_runtime_put_sync(dev);
227 pm_runtime_disable(dev);
228 }
229
230 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
231 {
232 struct mtk_pcie *pcie = port->pcie;
233 struct device *dev = pcie->dev;
234
235 devm_iounmap(dev, port->base);
236 list_del(&port->list);
237 devm_kfree(dev, port);
238 }
239
240 static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
241 {
242 struct mtk_pcie_port *port, *tmp;
243
244 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
245 phy_power_off(port->phy);
246 phy_exit(port->phy);
247 clk_disable_unprepare(port->pipe_ck);
248 clk_disable_unprepare(port->obff_ck);
249 clk_disable_unprepare(port->axi_ck);
250 clk_disable_unprepare(port->aux_ck);
251 clk_disable_unprepare(port->ahb_ck);
252 clk_disable_unprepare(port->sys_ck);
253 mtk_pcie_port_free(port);
254 }
255
256 mtk_pcie_subsys_powerdown(pcie);
257 }
258
259 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
260 {
261 u32 val;
262 int err;
263
264 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
265 !(val & APP_CFG_REQ), 10,
266 100 * USEC_PER_MSEC);
267 if (err)
268 return PCIBIOS_SET_FAILED;
269
270 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
271 return PCIBIOS_SET_FAILED;
272
273 return PCIBIOS_SUCCESSFUL;
274 }
275
276 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
277 int where, int size, u32 *val)
278 {
279 u32 tmp;
280
281 /* Write PCIe configuration transaction header for Cfgrd */
282 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
283 port->base + PCIE_CFG_HEADER0);
284 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
285 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
286 port->base + PCIE_CFG_HEADER2);
287
288 /* Trigger h/w to transmit Cfgrd TLP */
289 tmp = readl(port->base + PCIE_APP_TLP_REQ);
290 tmp |= APP_CFG_REQ;
291 writel(tmp, port->base + PCIE_APP_TLP_REQ);
292
293 /* Check completion status */
294 if (mtk_pcie_check_cfg_cpld(port))
295 return PCIBIOS_SET_FAILED;
296
297 /* Read cpld payload of Cfgrd */
298 *val = readl(port->base + PCIE_CFG_RDATA);
299
300 if (size == 1)
301 *val = (*val >> (8 * (where & 3))) & 0xff;
302 else if (size == 2)
303 *val = (*val >> (8 * (where & 3))) & 0xffff;
304
305 return PCIBIOS_SUCCESSFUL;
306 }
307
308 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
309 int where, int size, u32 val)
310 {
311 /* Write PCIe configuration transaction header for Cfgwr */
312 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
313 port->base + PCIE_CFG_HEADER0);
314 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
315 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
316 port->base + PCIE_CFG_HEADER2);
317
318 /* Write Cfgwr data */
319 val = val << 8 * (where & 3);
320 writel(val, port->base + PCIE_CFG_WDATA);
321
322 /* Trigger h/w to transmit Cfgwr TLP */
323 val = readl(port->base + PCIE_APP_TLP_REQ);
324 val |= APP_CFG_REQ;
325 writel(val, port->base + PCIE_APP_TLP_REQ);
326
327 /* Check completion status */
328 return mtk_pcie_check_cfg_cpld(port);
329 }
330
331 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
332 unsigned int devfn)
333 {
334 struct mtk_pcie *pcie = bus->sysdata;
335 struct mtk_pcie_port *port;
336 struct pci_dev *dev = NULL;
337
338 /*
339 * Walk the bus hierarchy to get the devfn value
340 * of the port in the root bus.
341 */
342 while (bus && bus->number) {
343 dev = bus->self;
344 bus = dev->bus;
345 devfn = dev->devfn;
346 }
347
348 list_for_each_entry(port, &pcie->ports, list)
349 if (port->slot == PCI_SLOT(devfn))
350 return port;
351
352 return NULL;
353 }
354
355 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
356 int where, int size, u32 *val)
357 {
358 struct mtk_pcie_port *port;
359 u32 bn = bus->number;
360 int ret;
361
362 port = mtk_pcie_find_port(bus, devfn);
363 if (!port) {
364 *val = ~0;
365 return PCIBIOS_DEVICE_NOT_FOUND;
366 }
367
368 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
369 if (ret)
370 *val = ~0;
371
372 return ret;
373 }
374
375 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
376 int where, int size, u32 val)
377 {
378 struct mtk_pcie_port *port;
379 u32 bn = bus->number;
380
381 port = mtk_pcie_find_port(bus, devfn);
382 if (!port)
383 return PCIBIOS_DEVICE_NOT_FOUND;
384
385 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
386 }
387
388 static struct pci_ops mtk_pcie_ops_v2 = {
389 .read = mtk_pcie_config_read,
390 .write = mtk_pcie_config_write,
391 };
392
393 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
394 {
395 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
396 phys_addr_t addr;
397
398 /* MT2712/MT7622 only support 32-bit MSI addresses */
399 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
400 msg->address_hi = 0;
401 msg->address_lo = lower_32_bits(addr);
402
403 msg->data = data->hwirq;
404
405 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
406 (int)data->hwirq, msg->address_hi, msg->address_lo);
407 }
408
409 static int mtk_msi_set_affinity(struct irq_data *irq_data,
410 const struct cpumask *mask, bool force)
411 {
412 return -EINVAL;
413 }
414
415 static void mtk_msi_ack_irq(struct irq_data *data)
416 {
417 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
418 u32 hwirq = data->hwirq;
419
420 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
421 }
422
423 static struct irq_chip mtk_msi_bottom_irq_chip = {
424 .name = "MTK MSI",
425 .irq_compose_msi_msg = mtk_compose_msi_msg,
426 .irq_set_affinity = mtk_msi_set_affinity,
427 .irq_ack = mtk_msi_ack_irq,
428 };
429
430 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
431 unsigned int nr_irqs, void *args)
432 {
433 struct mtk_pcie_port *port = domain->host_data;
434 unsigned long bit;
435
436 WARN_ON(nr_irqs != 1);
437 mutex_lock(&port->lock);
438
439 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
440 if (bit >= MTK_MSI_IRQS_NUM) {
441 mutex_unlock(&port->lock);
442 return -ENOSPC;
443 }
444
445 __set_bit(bit, port->msi_irq_in_use);
446
447 mutex_unlock(&port->lock);
448
449 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
450 domain->host_data, handle_edge_irq,
451 NULL, NULL);
452
453 return 0;
454 }
455
456 static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
457 unsigned int virq, unsigned int nr_irqs)
458 {
459 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
460 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
461
462 mutex_lock(&port->lock);
463
464 if (!test_bit(d->hwirq, port->msi_irq_in_use))
465 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
466 d->hwirq);
467 else
468 __clear_bit(d->hwirq, port->msi_irq_in_use);
469
470 mutex_unlock(&port->lock);
471
472 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
473 }
474
475 static const struct irq_domain_ops msi_domain_ops = {
476 .alloc = mtk_pcie_irq_domain_alloc,
477 .free = mtk_pcie_irq_domain_free,
478 };
479
480 static struct irq_chip mtk_msi_irq_chip = {
481 .name = "MTK PCIe MSI",
482 .irq_ack = irq_chip_ack_parent,
483 .irq_mask = pci_msi_mask_irq,
484 .irq_unmask = pci_msi_unmask_irq,
485 };
486
487 static struct msi_domain_info mtk_msi_domain_info = {
488 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
489 MSI_FLAG_PCI_MSIX),
490 .chip = &mtk_msi_irq_chip,
491 };
492
493 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
494 {
495 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
496
497 mutex_init(&port->lock);
498
499 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
500 &msi_domain_ops, port);
501 if (!port->inner_domain) {
502 dev_err(port->pcie->dev, "failed to create IRQ domain\n");
503 return -ENOMEM;
504 }
505
506 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
507 port->inner_domain);
508 if (!port->msi_domain) {
509 dev_err(port->pcie->dev, "failed to create MSI domain\n");
510 irq_domain_remove(port->inner_domain);
511 return -ENOMEM;
512 }
513
514 return 0;
515 }
516
517 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
518 {
519 u32 val;
520 phys_addr_t msg_addr;
521
522 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
523 val = lower_32_bits(msg_addr);
524 writel(val, port->base + PCIE_IMSI_ADDR);
525
526 val = readl(port->base + PCIE_INT_MASK);
527 val &= ~MSI_MASK;
528 writel(val, port->base + PCIE_INT_MASK);
529 }
530
531 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
532 {
533 struct mtk_pcie_port *port, *tmp;
534
535 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
536 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
537
538 if (port->irq_domain)
539 irq_domain_remove(port->irq_domain);
540
541 if (IS_ENABLED(CONFIG_PCI_MSI)) {
542 if (port->msi_domain)
543 irq_domain_remove(port->msi_domain);
544 if (port->inner_domain)
545 irq_domain_remove(port->inner_domain);
546 }
547
548 irq_dispose_mapping(port->irq);
549 }
550 }
551
552 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
553 irq_hw_number_t hwirq)
554 {
555 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
556 irq_set_chip_data(irq, domain->host_data);
557
558 return 0;
559 }
560
561 static const struct irq_domain_ops intx_domain_ops = {
562 .map = mtk_pcie_intx_map,
563 };
564
565 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
566 struct device_node *node)
567 {
568 struct device *dev = port->pcie->dev;
569 struct device_node *pcie_intc_node;
570 int ret;
571
572 /* Setup INTx */
573 pcie_intc_node = of_get_next_child(node, NULL);
574 if (!pcie_intc_node) {
575 dev_err(dev, "no PCIe Intc node found\n");
576 return -ENODEV;
577 }
578
579 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
580 &intx_domain_ops, port);
581 of_node_put(pcie_intc_node);
582 if (!port->irq_domain) {
583 dev_err(dev, "failed to get INTx IRQ domain\n");
584 return -ENODEV;
585 }
586
587 if (IS_ENABLED(CONFIG_PCI_MSI)) {
588 ret = mtk_pcie_allocate_msi_domains(port);
589 if (ret)
590 return ret;
591 }
592
593 return 0;
594 }
595
596 static void mtk_pcie_intr_handler(struct irq_desc *desc)
597 {
598 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
599 struct irq_chip *irqchip = irq_desc_get_chip(desc);
600 unsigned long status;
601 u32 virq;
602 u32 bit = INTX_SHIFT;
603
604 chained_irq_enter(irqchip, desc);
605
606 status = readl(port->base + PCIE_INT_STATUS);
607 if (status & INTX_MASK) {
608 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
609 /* Clear the INTx */
610 writel(1 << bit, port->base + PCIE_INT_STATUS);
611 virq = irq_find_mapping(port->irq_domain,
612 bit - INTX_SHIFT);
613 generic_handle_irq(virq);
614 }
615 }
616
617 if (IS_ENABLED(CONFIG_PCI_MSI)) {
618 if (status & MSI_STATUS){
619 unsigned long imsi_status;
620
621 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
622 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
623 virq = irq_find_mapping(port->inner_domain, bit);
624 generic_handle_irq(virq);
625 }
626 }
627 /* Clear MSI interrupt status */
628 writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
629 }
630 }
631
632 chained_irq_exit(irqchip, desc);
633
634 return;
635 }
636
637 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
638 struct device_node *node)
639 {
640 struct mtk_pcie *pcie = port->pcie;
641 struct device *dev = pcie->dev;
642 struct platform_device *pdev = to_platform_device(dev);
643 int err;
644
645 err = mtk_pcie_init_irq_domain(port, node);
646 if (err) {
647 dev_err(dev, "failed to init PCIe IRQ domain\n");
648 return err;
649 }
650
651 port->irq = platform_get_irq(pdev, port->slot);
652 irq_set_chained_handler_and_data(port->irq,
653 mtk_pcie_intr_handler, port);
654
655 return 0;
656 }
657
658 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
659 {
660 struct mtk_pcie *pcie = port->pcie;
661 struct resource *mem = &pcie->mem;
662 const struct mtk_pcie_soc *soc = port->pcie->soc;
663 u32 val;
664 int err;
665
666 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
667 if (pcie->base) {
668 val = readl(pcie->base + PCIE_SYS_CFG_V2);
669 val |= PCIE_CSR_LTSSM_EN(port->slot) |
670 PCIE_CSR_ASPM_L1_EN(port->slot);
671 writel(val, pcie->base + PCIE_SYS_CFG_V2);
672 }
673
674 /* Assert all reset signals */
675 writel(0, port->base + PCIE_RST_CTRL);
676
677 /*
678 * Enable PCIe link down reset, if link status changed from link up to
679 * link down, this will reset MAC control registers and configuration
680 * space.
681 */
682 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
683
684 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
685 val = readl(port->base + PCIE_RST_CTRL);
686 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
687 PCIE_MAC_SRSTB | PCIE_CRSTB;
688 writel(val, port->base + PCIE_RST_CTRL);
689
690 /* Set up vendor ID and class code */
691 if (soc->need_fix_class_id) {
692 val = PCI_VENDOR_ID_MEDIATEK;
693 writew(val, port->base + PCIE_CONF_VEND_ID);
694
695 val = PCI_CLASS_BRIDGE_PCI;
696 writew(val, port->base + PCIE_CONF_CLASS_ID);
697 }
698
699 /* 100ms timeout value should be enough for Gen1/2 training */
700 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
701 !!(val & PCIE_PORT_LINKUP_V2), 20,
702 100 * USEC_PER_MSEC);
703 if (err)
704 return -ETIMEDOUT;
705
706 /* Set INTx mask */
707 val = readl(port->base + PCIE_INT_MASK);
708 val &= ~INTX_MASK;
709 writel(val, port->base + PCIE_INT_MASK);
710
711 if (IS_ENABLED(CONFIG_PCI_MSI))
712 mtk_pcie_enable_msi(port);
713
714 /* Set AHB to PCIe translation windows */
715 val = lower_32_bits(mem->start) |
716 AHB2PCIE_SIZE(fls(resource_size(mem)));
717 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
718
719 val = upper_32_bits(mem->start);
720 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
721
722 /* Set PCIe to AXI translation memory space.*/
723 val = PCIE2AHB_SIZE | WIN_ENABLE;
724 writel(val, port->base + PCIE_AXI_WINDOW0);
725
726 return 0;
727 }
728
729 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
730 unsigned int devfn, int where)
731 {
732 struct mtk_pcie *pcie = bus->sysdata;
733
734 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
735 bus->number), pcie->base + PCIE_CFG_ADDR);
736
737 return pcie->base + PCIE_CFG_DATA + (where & 3);
738 }
739
740 static struct pci_ops mtk_pcie_ops = {
741 .map_bus = mtk_pcie_map_bus,
742 .read = pci_generic_config_read,
743 .write = pci_generic_config_write,
744 };
745
746 static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
747 {
748 struct mtk_pcie *pcie = port->pcie;
749 u32 func = PCI_FUNC(port->slot << 3);
750 u32 slot = PCI_SLOT(port->slot << 3);
751 u32 val;
752 int err;
753
754 /* assert port PERST_N */
755 val = readl(pcie->base + PCIE_SYS_CFG);
756 val |= PCIE_PORT_PERST(port->slot);
757 writel(val, pcie->base + PCIE_SYS_CFG);
758
759 /* de-assert port PERST_N */
760 val = readl(pcie->base + PCIE_SYS_CFG);
761 val &= ~PCIE_PORT_PERST(port->slot);
762 writel(val, pcie->base + PCIE_SYS_CFG);
763
764 /* 100ms timeout value should be enough for Gen1/2 training */
765 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
766 !!(val & PCIE_PORT_LINKUP), 20,
767 100 * USEC_PER_MSEC);
768 if (err)
769 return -ETIMEDOUT;
770
771 /* enable interrupt */
772 val = readl(pcie->base + PCIE_INT_ENABLE);
773 val |= PCIE_PORT_INT_EN(port->slot);
774 writel(val, pcie->base + PCIE_INT_ENABLE);
775
776 /* map to all DDR region. We need to set it before cfg operation. */
777 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
778 port->base + PCIE_BAR0_SETUP);
779
780 /* configure class code and revision ID */
781 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
782
783 /* configure FC credit */
784 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
785 pcie->base + PCIE_CFG_ADDR);
786 val = readl(pcie->base + PCIE_CFG_DATA);
787 val &= ~PCIE_FC_CREDIT_MASK;
788 val |= PCIE_FC_CREDIT_VAL(0x806c);
789 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
790 pcie->base + PCIE_CFG_ADDR);
791 writel(val, pcie->base + PCIE_CFG_DATA);
792
793 /* configure RC FTS number to 250 when it leaves L0s */
794 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
795 pcie->base + PCIE_CFG_ADDR);
796 val = readl(pcie->base + PCIE_CFG_DATA);
797 val &= ~PCIE_FTS_NUM_MASK;
798 val |= PCIE_FTS_NUM_L0(0x50);
799 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
800 pcie->base + PCIE_CFG_ADDR);
801 writel(val, pcie->base + PCIE_CFG_DATA);
802
803 return 0;
804 }
805
806 static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
807 {
808 struct mtk_pcie *pcie = port->pcie;
809 struct device *dev = pcie->dev;
810 int err;
811
812 err = clk_prepare_enable(port->sys_ck);
813 if (err) {
814 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
815 goto err_sys_clk;
816 }
817
818 err = clk_prepare_enable(port->ahb_ck);
819 if (err) {
820 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
821 goto err_ahb_clk;
822 }
823
824 err = clk_prepare_enable(port->aux_ck);
825 if (err) {
826 dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
827 goto err_aux_clk;
828 }
829
830 err = clk_prepare_enable(port->axi_ck);
831 if (err) {
832 dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
833 goto err_axi_clk;
834 }
835
836 err = clk_prepare_enable(port->obff_ck);
837 if (err) {
838 dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
839 goto err_obff_clk;
840 }
841
842 err = clk_prepare_enable(port->pipe_ck);
843 if (err) {
844 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
845 goto err_pipe_clk;
846 }
847
848 reset_control_assert(port->reset);
849 reset_control_deassert(port->reset);
850
851 err = phy_init(port->phy);
852 if (err) {
853 dev_err(dev, "failed to initialize port%d phy\n", port->slot);
854 goto err_phy_init;
855 }
856
857 err = phy_power_on(port->phy);
858 if (err) {
859 dev_err(dev, "failed to power on port%d phy\n", port->slot);
860 goto err_phy_on;
861 }
862
863 if (!pcie->soc->startup(port))
864 return;
865
866 dev_info(dev, "Port%d link down\n", port->slot);
867
868 phy_power_off(port->phy);
869 err_phy_on:
870 phy_exit(port->phy);
871 err_phy_init:
872 clk_disable_unprepare(port->pipe_ck);
873 err_pipe_clk:
874 clk_disable_unprepare(port->obff_ck);
875 err_obff_clk:
876 clk_disable_unprepare(port->axi_ck);
877 err_axi_clk:
878 clk_disable_unprepare(port->aux_ck);
879 err_aux_clk:
880 clk_disable_unprepare(port->ahb_ck);
881 err_ahb_clk:
882 clk_disable_unprepare(port->sys_ck);
883 err_sys_clk:
884 mtk_pcie_port_free(port);
885 }
886
887 static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
888 struct device_node *node,
889 int slot)
890 {
891 struct mtk_pcie_port *port;
892 struct resource *regs;
893 struct device *dev = pcie->dev;
894 struct platform_device *pdev = to_platform_device(dev);
895 char name[10];
896 int err;
897
898 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
899 if (!port)
900 return -ENOMEM;
901
902 snprintf(name, sizeof(name), "port%d", slot);
903 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
904 port->base = devm_ioremap_resource(dev, regs);
905 if (IS_ERR(port->base)) {
906 dev_err(dev, "failed to map port%d base\n", slot);
907 return PTR_ERR(port->base);
908 }
909
910 snprintf(name, sizeof(name), "sys_ck%d", slot);
911 port->sys_ck = devm_clk_get(dev, name);
912 if (IS_ERR(port->sys_ck)) {
913 dev_err(dev, "failed to get sys_ck%d clock\n", slot);
914 return PTR_ERR(port->sys_ck);
915 }
916
917 /* sys_ck might be divided into the following parts in some chips */
918 snprintf(name, sizeof(name), "ahb_ck%d", slot);
919 port->ahb_ck = devm_clk_get_optional(dev, name);
920 if (IS_ERR(port->ahb_ck))
921 return PTR_ERR(port->ahb_ck);
922
923 snprintf(name, sizeof(name), "axi_ck%d", slot);
924 port->axi_ck = devm_clk_get_optional(dev, name);
925 if (IS_ERR(port->axi_ck))
926 return PTR_ERR(port->axi_ck);
927
928 snprintf(name, sizeof(name), "aux_ck%d", slot);
929 port->aux_ck = devm_clk_get_optional(dev, name);
930 if (IS_ERR(port->aux_ck))
931 return PTR_ERR(port->aux_ck);
932
933 snprintf(name, sizeof(name), "obff_ck%d", slot);
934 port->obff_ck = devm_clk_get_optional(dev, name);
935 if (IS_ERR(port->obff_ck))
936 return PTR_ERR(port->obff_ck);
937
938 snprintf(name, sizeof(name), "pipe_ck%d", slot);
939 port->pipe_ck = devm_clk_get_optional(dev, name);
940 if (IS_ERR(port->pipe_ck))
941 return PTR_ERR(port->pipe_ck);
942
943 snprintf(name, sizeof(name), "pcie-rst%d", slot);
944 port->reset = devm_reset_control_get_optional_exclusive(dev, name);
945 if (PTR_ERR(port->reset) == -EPROBE_DEFER)
946 return PTR_ERR(port->reset);
947
948 /* some platforms may use default PHY setting */
949 snprintf(name, sizeof(name), "pcie-phy%d", slot);
950 port->phy = devm_phy_optional_get(dev, name);
951 if (IS_ERR(port->phy))
952 return PTR_ERR(port->phy);
953
954 port->slot = slot;
955 port->pcie = pcie;
956
957 if (pcie->soc->setup_irq) {
958 err = pcie->soc->setup_irq(port, node);
959 if (err)
960 return err;
961 }
962
963 INIT_LIST_HEAD(&port->list);
964 list_add_tail(&port->list, &pcie->ports);
965
966 return 0;
967 }
968
969 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
970 {
971 struct device *dev = pcie->dev;
972 struct platform_device *pdev = to_platform_device(dev);
973 struct resource *regs;
974 int err;
975
976 /* get shared registers, which are optional */
977 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
978 if (regs) {
979 pcie->base = devm_ioremap_resource(dev, regs);
980 if (IS_ERR(pcie->base)) {
981 dev_err(dev, "failed to map shared register\n");
982 return PTR_ERR(pcie->base);
983 }
984 }
985
986 pcie->free_ck = devm_clk_get(dev, "free_ck");
987 if (IS_ERR(pcie->free_ck)) {
988 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
989 return -EPROBE_DEFER;
990
991 pcie->free_ck = NULL;
992 }
993
994 pm_runtime_enable(dev);
995 pm_runtime_get_sync(dev);
996
997 /* enable top level clock */
998 err = clk_prepare_enable(pcie->free_ck);
999 if (err) {
1000 dev_err(dev, "failed to enable free_ck\n");
1001 goto err_free_ck;
1002 }
1003
1004 return 0;
1005
1006 err_free_ck:
1007 pm_runtime_put_sync(dev);
1008 pm_runtime_disable(dev);
1009
1010 return err;
1011 }
1012
1013 static int mtk_pcie_setup(struct mtk_pcie *pcie)
1014 {
1015 struct device *dev = pcie->dev;
1016 struct device_node *node = dev->of_node, *child;
1017 struct mtk_pcie_port *port, *tmp;
1018 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1019 struct list_head *windows = &host->windows;
1020 struct resource_entry *win, *tmp_win;
1021 resource_size_t io_base;
1022 int err;
1023
1024 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
1025 windows, &io_base);
1026 if (err)
1027 return err;
1028
1029 err = devm_request_pci_bus_resources(dev, windows);
1030 if (err < 0)
1031 return err;
1032
1033 /* Get the I/O and memory ranges from DT */
1034 resource_list_for_each_entry_safe(win, tmp_win, windows) {
1035 switch (resource_type(win->res)) {
1036 case IORESOURCE_IO:
1037 err = devm_pci_remap_iospace(dev, win->res, io_base);
1038 if (err) {
1039 dev_warn(dev, "error %d: failed to map resource %pR\n",
1040 err, win->res);
1041 resource_list_destroy_entry(win);
1042 }
1043 break;
1044 case IORESOURCE_MEM:
1045 memcpy(&pcie->mem, win->res, sizeof(*win->res));
1046 pcie->mem.name = "non-prefetchable";
1047 break;
1048 case IORESOURCE_BUS:
1049 pcie->busnr = win->res->start;
1050 break;
1051 }
1052 }
1053
1054 for_each_available_child_of_node(node, child) {
1055 int slot;
1056
1057 err = of_pci_get_devfn(child);
1058 if (err < 0) {
1059 dev_err(dev, "failed to parse devfn: %d\n", err);
1060 return err;
1061 }
1062
1063 slot = PCI_SLOT(err);
1064
1065 err = mtk_pcie_parse_port(pcie, child, slot);
1066 if (err)
1067 return err;
1068 }
1069
1070 err = mtk_pcie_subsys_powerup(pcie);
1071 if (err)
1072 return err;
1073
1074 /* enable each port, and then check link status */
1075 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1076 mtk_pcie_enable_port(port);
1077
1078 /* power down PCIe subsys if slots are all empty (link down) */
1079 if (list_empty(&pcie->ports))
1080 mtk_pcie_subsys_powerdown(pcie);
1081
1082 return 0;
1083 }
1084
1085 static int mtk_pcie_probe(struct platform_device *pdev)
1086 {
1087 struct device *dev = &pdev->dev;
1088 struct mtk_pcie *pcie;
1089 struct pci_host_bridge *host;
1090 int err;
1091
1092 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1093 if (!host)
1094 return -ENOMEM;
1095
1096 pcie = pci_host_bridge_priv(host);
1097
1098 pcie->dev = dev;
1099 pcie->soc = of_device_get_match_data(dev);
1100 platform_set_drvdata(pdev, pcie);
1101 INIT_LIST_HEAD(&pcie->ports);
1102
1103 err = mtk_pcie_setup(pcie);
1104 if (err)
1105 return err;
1106
1107 host->busnr = pcie->busnr;
1108 host->dev.parent = pcie->dev;
1109 host->ops = pcie->soc->ops;
1110 host->map_irq = of_irq_parse_and_map_pci;
1111 host->swizzle_irq = pci_common_swizzle;
1112 host->sysdata = pcie;
1113
1114 err = pci_host_probe(host);
1115 if (err)
1116 goto put_resources;
1117
1118 return 0;
1119
1120 put_resources:
1121 if (!list_empty(&pcie->ports))
1122 mtk_pcie_put_resources(pcie);
1123
1124 return err;
1125 }
1126
1127
1128 static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
1129 {
1130 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1131 struct list_head *windows = &host->windows;
1132
1133 pci_free_resource_list(windows);
1134 }
1135
1136 static int mtk_pcie_remove(struct platform_device *pdev)
1137 {
1138 struct mtk_pcie *pcie = platform_get_drvdata(pdev);
1139 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1140
1141 pci_stop_root_bus(host->bus);
1142 pci_remove_root_bus(host->bus);
1143 mtk_pcie_free_resources(pcie);
1144
1145 mtk_pcie_irq_teardown(pcie);
1146
1147 mtk_pcie_put_resources(pcie);
1148
1149 return 0;
1150 }
1151
1152 static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
1153 {
1154 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1155 struct mtk_pcie_port *port;
1156
1157 if (list_empty(&pcie->ports))
1158 return 0;
1159
1160 list_for_each_entry(port, &pcie->ports, list) {
1161 clk_disable_unprepare(port->pipe_ck);
1162 clk_disable_unprepare(port->obff_ck);
1163 clk_disable_unprepare(port->axi_ck);
1164 clk_disable_unprepare(port->aux_ck);
1165 clk_disable_unprepare(port->ahb_ck);
1166 clk_disable_unprepare(port->sys_ck);
1167 phy_power_off(port->phy);
1168 phy_exit(port->phy);
1169 }
1170
1171 clk_disable_unprepare(pcie->free_ck);
1172
1173 return 0;
1174 }
1175
1176 static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
1177 {
1178 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1179 struct mtk_pcie_port *port, *tmp;
1180
1181 if (list_empty(&pcie->ports))
1182 return 0;
1183
1184 clk_prepare_enable(pcie->free_ck);
1185
1186 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1187 mtk_pcie_enable_port(port);
1188
1189 /* In case of EP was removed while system suspend. */
1190 if (list_empty(&pcie->ports))
1191 clk_disable_unprepare(pcie->free_ck);
1192
1193 return 0;
1194 }
1195
1196 static const struct dev_pm_ops mtk_pcie_pm_ops = {
1197 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1198 mtk_pcie_resume_noirq)
1199 };
1200
1201 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1202 .ops = &mtk_pcie_ops,
1203 .startup = mtk_pcie_startup_port,
1204 };
1205
1206 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
1207 .ops = &mtk_pcie_ops_v2,
1208 .startup = mtk_pcie_startup_port_v2,
1209 .setup_irq = mtk_pcie_setup_irq,
1210 };
1211
1212 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1213 .need_fix_class_id = true,
1214 .ops = &mtk_pcie_ops_v2,
1215 .startup = mtk_pcie_startup_port_v2,
1216 .setup_irq = mtk_pcie_setup_irq,
1217 };
1218
1219 static const struct of_device_id mtk_pcie_ids[] = {
1220 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1221 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1222 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1223 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1224 {},
1225 };
1226
1227 static struct platform_driver mtk_pcie_driver = {
1228 .probe = mtk_pcie_probe,
1229 .remove = mtk_pcie_remove,
1230 .driver = {
1231 .name = "mtk-pcie",
1232 .of_match_table = mtk_pcie_ids,
1233 .suppress_bind_attrs = true,
1234 .pm = &mtk_pcie_pm_ops,
1235 },
1236 };
1237 module_platform_driver(mtk_pcie_driver);
1238 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support