drivers/spi/spi-sprd-adi.c

   1 /*
   2  * Copyright (C) 2017 Spreadtrum Communications Inc.
   3  *
   4  * SPDX-License-Identifier: GPL-2.0
   5  */
   6
   7 #include <linux/delay.h>
   8 #include <linux/hwspinlock.h>
   9 #include <linux/init.h>
  10 #include <linux/io.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/reboot.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/sizes.h>
  19
  20 /* Registers definitions for ADI controller */
  21 #define REG_ADI_CTRL0                   0x4
  22 #define REG_ADI_CHN_PRIL                0x8
  23 #define REG_ADI_CHN_PRIH                0xc
  24 #define REG_ADI_INT_EN                  0x10
  25 #define REG_ADI_INT_RAW                 0x14
  26 #define REG_ADI_INT_MASK                0x18
  27 #define REG_ADI_INT_CLR                 0x1c
  28 #define REG_ADI_GSSI_CFG0               0x20
  29 #define REG_ADI_GSSI_CFG1               0x24
  30 #define REG_ADI_RD_CMD                  0x28
  31 #define REG_ADI_RD_DATA                 0x2c
  32 #define REG_ADI_ARM_FIFO_STS            0x30
  33 #define REG_ADI_STS                     0x34
  34 #define REG_ADI_EVT_FIFO_STS            0x38
  35 #define REG_ADI_ARM_CMD_STS             0x3c
  36 #define REG_ADI_CHN_EN                  0x40
  37 #define REG_ADI_CHN_ADDR(id)            (0x44 + (id - 2) * 4)
  38 #define REG_ADI_CHN_EN1                 0x20c
  39
  40 /* Bits definitions for register REG_ADI_GSSI_CFG0 */
  41 #define BIT_CLK_ALL_ON                  BIT(30)
  42
  43 /* Bits definitions for register REG_ADI_RD_DATA */
  44 #define BIT_RD_CMD_BUSY                 BIT(31)
  45 #define RD_ADDR_SHIFT                   16
  46 #define RD_VALUE_MASK                   GENMASK(15, 0)
  47 #define RD_ADDR_MASK                    GENMASK(30, 16)
  48
  49 /* Bits definitions for register REG_ADI_ARM_FIFO_STS */
  50 #define BIT_FIFO_FULL                   BIT(11)
  51 #define BIT_FIFO_EMPTY                  BIT(10)
  52
  53 /*
  54  * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
  55  * The slave devices address offset is always 0x8000 and size is 4K.
  56  */
  57 #define ADI_SLAVE_ADDR_SIZE             SZ_4K
  58 #define ADI_SLAVE_OFFSET                0x8000
  59
  60 /* Timeout (ms) for the trylock of hardware spinlocks */
  61 #define ADI_HWSPINLOCK_TIMEOUT          5000
  62 /*
  63  * ADI controller has 50 channels including 2 software channels
  64  * and 48 hardware channels.
  65  */
  66 #define ADI_HW_CHNS                     50
  67
  68 #define ADI_FIFO_DRAIN_TIMEOUT          1000
  69 #define ADI_READ_TIMEOUT                2000
  70 #define REG_ADDR_LOW_MASK               GENMASK(11, 0)
  71
  72 /* Registers definitions for PMIC watchdog controller */
  73 #define REG_WDG_LOAD_LOW                0x80
  74 #define REG_WDG_LOAD_HIGH               0x84
  75 #define REG_WDG_CTRL                    0x88
  76 #define REG_WDG_LOCK                    0xa0
  77
  78 /* Bits definitions for register REG_WDG_CTRL */
  79 #define BIT_WDG_RUN                     BIT(1)
  80 #define BIT_WDG_RST                     BIT(3)
  81
  82 /* Registers definitions for PMIC */
  83 #define PMIC_RST_STATUS                 0xee8
  84 #define PMIC_MODULE_EN                  0xc08
  85 #define PMIC_CLK_EN                     0xc18
  86 #define BIT_WDG_EN                      BIT(2)
  87
  88 /* Definition of PMIC reset status register */
  89 #define HWRST_STATUS_SECURITY           0x02
  90 #define HWRST_STATUS_RECOVERY           0x20
  91 #define HWRST_STATUS_NORMAL             0x40
  92 #define HWRST_STATUS_ALARM              0x50
  93 #define HWRST_STATUS_SLEEP              0x60
  94 #define HWRST_STATUS_FASTBOOT           0x30
  95 #define HWRST_STATUS_SPECIAL            0x70
  96 #define HWRST_STATUS_PANIC              0x80
  97 #define HWRST_STATUS_CFTREBOOT          0x90
  98 #define HWRST_STATUS_AUTODLOADER        0xa0
  99 #define HWRST_STATUS_IQMODE             0xb0
 100 #define HWRST_STATUS_SPRDISK            0xc0
 101 #define HWRST_STATUS_FACTORYTEST        0xe0
 102 #define HWRST_STATUS_WATCHDOG           0xf0
 103
 104 /* Use default timeout 50 ms that converts to watchdog values */
 105 #define WDG_LOAD_VAL                    ((50 * 1000) / 32768)
 106 #define WDG_LOAD_MASK                   GENMASK(15, 0)
 107 #define WDG_UNLOCK_KEY                  0xe551
 108
 109 struct sprd_adi {
 110         struct spi_controller   *ctlr;
 111         struct device           *dev;
 112         void __iomem            *base;
 113         struct hwspinlock       *hwlock;
 114         unsigned long           slave_vbase;
 115         unsigned long           slave_pbase;
 116         struct notifier_block   restart_handler;
 117 };
 118
 119 static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
 120 {
 121         if (paddr < sadi->slave_pbase || paddr >
 122             (sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
 123                 dev_err(sadi->dev,
 124                         "slave physical address is incorrect, addr = 0x%x\n",
 125                         paddr);
 126                 return -EINVAL;
 127         }
 128
 129         return 0;
 130 }
 131
 132 static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
 133 {
 134         return (paddr - sadi->slave_pbase + sadi->slave_vbase);
 135 }
 136
 137 static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
 138 {
 139         u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
 140         u32 sts;
 141
 142         do {
 143                 sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
 144                 if (sts & BIT_FIFO_EMPTY)
 145                         break;
 146
 147                 cpu_relax();
 148         } while (--timeout);
 149
 150         if (timeout == 0) {
 151                 dev_err(sadi->dev, "drain write fifo timeout\n");
 152                 return -EBUSY;
 153         }
 154
 155         return 0;
 156 }
 157
 158 static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
 159 {
 160         return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
 161 }
 162
 163 static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
 164 {
 165         int read_timeout = ADI_READ_TIMEOUT;
 166         unsigned long flags;
 167         u32 val, rd_addr;
 168         int ret;
 169
 170         ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
 171                                           ADI_HWSPINLOCK_TIMEOUT,
 172                                           &flags);
 173         if (ret) {
 174                 dev_err(sadi->dev, "get the hw lock failed\n");
 175                 return ret;
 176         }
 177
 178         /*
 179          * Set the physical register address need to read into RD_CMD register,
 180          * then ADI controller will start to transfer automatically.
 181          */
 182         writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);
 183
 184         /*
 185          * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
 186          * simultaneously when writing read command to register, and the
 187          * BIT_RD_CMD_BUSY will be cleared after the read operation is
 188          * completed.
 189          */
 190         do {
 191                 val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
 192                 if (!(val & BIT_RD_CMD_BUSY))
 193                         break;
 194
 195                 cpu_relax();
 196         } while (--read_timeout);
 197
 198         if (read_timeout == 0) {
 199                 dev_err(sadi->dev, "ADI read timeout\n");
 200                 ret = -EBUSY;
 201                 goto out;
 202         }
 203
 204         /*
 205          * The return value includes data and read register address, from bit 0
 206          * to bit 15 are data, and from bit 16 to bit 30 are read register
 207          * address. Then we can check the returned register address to validate
 208          * data.
 209          */
 210         rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;
 211
 212         if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
 213                 dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
 214                         reg_paddr, val);
 215                 ret = -EIO;
 216                 goto out;
 217         }
 218
 219         *read_val = val & RD_VALUE_MASK;
 220
 221 out:
 222         hwspin_unlock_irqrestore(sadi->hwlock, &flags);
 223         return ret;
 224 }
 225
 226 static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
 227 {
 228         unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr);
 229         u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
 230         unsigned long flags;
 231         int ret;
 232
 233         ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
 234                                           ADI_HWSPINLOCK_TIMEOUT,
 235                                           &flags);
 236         if (ret) {
 237                 dev_err(sadi->dev, "get the hw lock failed\n");
 238                 return ret;
 239         }
 240
 241         ret = sprd_adi_drain_fifo(sadi);
 242         if (ret < 0)
 243                 goto out;
 244
 245         /*
 246          * we should wait for write fifo is empty before writing data to PMIC
 247          * registers.
 248          */
 249         do {
 250                 if (!sprd_adi_fifo_is_full(sadi)) {
 251                         writel_relaxed(val, (void __iomem *)reg);
 252                         break;
 253                 }
 254
 255                 cpu_relax();
 256         } while (--timeout);
 257
 258         if (timeout == 0) {
 259                 dev_err(sadi->dev, "write fifo is full\n");
 260                 ret = -EBUSY;
 261         }
 262
 263 out:
 264         hwspin_unlock_irqrestore(sadi->hwlock, &flags);
 265         return ret;
 266 }
 267
 268 static int sprd_adi_transfer_one(struct spi_controller *ctlr,
 269                                  struct spi_device *spi_dev,
 270                                  struct spi_transfer *t)
 271 {
 272         struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
 273         u32 phy_reg, val;
 274         int ret;
 275
 276         if (t->rx_buf) {
 277                 phy_reg = *(u32 *)t->rx_buf + sadi->slave_pbase;
 278
 279                 ret = sprd_adi_check_paddr(sadi, phy_reg);
 280                 if (ret)
 281                         return ret;
 282
 283                 ret = sprd_adi_read(sadi, phy_reg, &val);
 284                 if (ret)
 285                         return ret;
 286
 287                 *(u32 *)t->rx_buf = val;
 288         } else if (t->tx_buf) {
 289                 u32 *p = (u32 *)t->tx_buf;
 290
 291                 /*
 292                  * Get the physical register address need to write and convert
 293                  * the physical address to virtual address. Since we need
 294                  * virtual register address to write.
 295                  */
 296                 phy_reg = *p++ + sadi->slave_pbase;
 297                 ret = sprd_adi_check_paddr(sadi, phy_reg);
 298                 if (ret)
 299                         return ret;
 300
 301                 val = *p;
 302                 ret = sprd_adi_write(sadi, phy_reg, val);
 303                 if (ret)
 304                         return ret;
 305         } else {
 306                 dev_err(sadi->dev, "no buffer for transfer\n");
 307                 return -EINVAL;
 308         }
 309
 310         return 0;
 311 }
 312
 313 static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi)
 314 {
 315 #ifdef CONFIG_SPRD_WATCHDOG
 316         u32 val;
 317
 318         /* Set default watchdog reboot mode */
 319         sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
 320         val |= HWRST_STATUS_WATCHDOG;
 321         sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
 322 #endif
 323 }
 324
 325 static int sprd_adi_restart_handler(struct notifier_block *this,
 326                                     unsigned long mode, void *cmd)
 327 {
 328         struct sprd_adi *sadi = container_of(this, struct sprd_adi,
 329                                              restart_handler);
 330         u32 val, reboot_mode = 0;
 331
 332         if (!cmd)
 333                 reboot_mode = HWRST_STATUS_NORMAL;
 334         else if (!strncmp(cmd, "recovery", 8))
 335                 reboot_mode = HWRST_STATUS_RECOVERY;
 336         else if (!strncmp(cmd, "alarm", 5))
 337                 reboot_mode = HWRST_STATUS_ALARM;
 338         else if (!strncmp(cmd, "fastsleep", 9))
 339                 reboot_mode = HWRST_STATUS_SLEEP;
 340         else if (!strncmp(cmd, "bootloader", 10))
 341                 reboot_mode = HWRST_STATUS_FASTBOOT;
 342         else if (!strncmp(cmd, "panic", 5))
 343                 reboot_mode = HWRST_STATUS_PANIC;
 344         else if (!strncmp(cmd, "special", 7))
 345                 reboot_mode = HWRST_STATUS_SPECIAL;
 346         else if (!strncmp(cmd, "cftreboot", 9))
 347                 reboot_mode = HWRST_STATUS_CFTREBOOT;
 348         else if (!strncmp(cmd, "autodloader", 11))
 349                 reboot_mode = HWRST_STATUS_AUTODLOADER;
 350         else if (!strncmp(cmd, "iqmode", 6))
 351                 reboot_mode = HWRST_STATUS_IQMODE;
 352         else if (!strncmp(cmd, "sprdisk", 7))
 353                 reboot_mode = HWRST_STATUS_SPRDISK;
 354         else if (!strncmp(cmd, "tospanic", 8))
 355                 reboot_mode = HWRST_STATUS_SECURITY;
 356         else if (!strncmp(cmd, "factorytest", 11))
 357                 reboot_mode = HWRST_STATUS_FACTORYTEST;
 358         else
 359                 reboot_mode = HWRST_STATUS_NORMAL;
 360
 361         /* Record the reboot mode */
 362         sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
 363         val &= ~HWRST_STATUS_WATCHDOG;
 364         val |= reboot_mode;
 365         sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
 366
 367         /* Enable the interface clock of the watchdog */
 368         sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val);
 369         val |= BIT_WDG_EN;
 370         sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val);
 371
 372         /* Enable the work clock of the watchdog */
 373         sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val);
 374         val |= BIT_WDG_EN;
 375         sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val);
 376
 377         /* Unlock the watchdog */
 378         sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY);
 379
 380         /* Load the watchdog timeout value, 50ms is always enough. */
 381         sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
 382                        WDG_LOAD_VAL & WDG_LOAD_MASK);
 383         sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
 384
 385         /* Start the watchdog to reset system */
 386         sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
 387         val |= BIT_WDG_RUN | BIT_WDG_RST;
 388         sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
 389
 390         mdelay(1000);
 391
 392         dev_emerg(sadi->dev, "Unable to restart system\n");
 393         return NOTIFY_DONE;
 394 }
 395
 396 static void sprd_adi_hw_init(struct sprd_adi *sadi)
 397 {
 398         struct device_node *np = sadi->dev->of_node;
 399         int i, size, chn_cnt;
 400         const __be32 *list;
 401         u32 tmp;
 402
 403         /* Set all channels as default priority */
 404         writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
 405         writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
 406
 407         /* Set clock auto gate mode */
 408         tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
 409         tmp &= ~BIT_CLK_ALL_ON;
 410         writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
 411
 412         /* Set hardware channels setting */
 413         list = of_get_property(np, "sprd,hw-channels", &size);
 414         if (!list || !size) {
 415                 dev_info(sadi->dev, "no hw channels setting in node\n");
 416                 return;
 417         }
 418
 419         chn_cnt = size / 8;
 420         for (i = 0; i < chn_cnt; i++) {
 421                 u32 value;
 422                 u32 chn_id = be32_to_cpu(*list++);
 423                 u32 chn_config = be32_to_cpu(*list++);
 424
 425                 /* Channel 0 and 1 are software channels */
 426                 if (chn_id < 2)
 427                         continue;
 428
 429                 writel_relaxed(chn_config, sadi->base +
 430                                REG_ADI_CHN_ADDR(chn_id));
 431
 432                 if (chn_id < 32) {
 433                         value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
 434                         value |= BIT(chn_id);
 435                         writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
 436                 } else if (chn_id < ADI_HW_CHNS) {
 437                         value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
 438                         value |= BIT(chn_id - 32);
 439                         writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
 440                 }
 441         }
 442 }
 443
 444 static int sprd_adi_probe(struct platform_device *pdev)
 445 {
 446         struct device_node *np = pdev->dev.of_node;
 447         struct spi_controller *ctlr;
 448         struct sprd_adi *sadi;
 449         struct resource *res;
 450         u32 num_chipselect;
 451         int ret;
 452
 453         if (!np) {
 454                 dev_err(&pdev->dev, "can not find the adi bus node\n");
 455                 return -ENODEV;
 456         }
 457
 458         pdev->id = of_alias_get_id(np, "spi");
 459         num_chipselect = of_get_child_count(np);
 460
 461         ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
 462         if (!ctlr)
 463                 return -ENOMEM;
 464
 465         dev_set_drvdata(&pdev->dev, ctlr);
 466         sadi = spi_controller_get_devdata(ctlr);
 467
 468         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 469         sadi->base = devm_ioremap_resource(&pdev->dev, res);
 470         if (IS_ERR(sadi->base)) {
 471                 ret = PTR_ERR(sadi->base);
 472                 goto put_ctlr;
 473         }
 474
 475         sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
 476         sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
 477         sadi->ctlr = ctlr;
 478         sadi->dev = &pdev->dev;
 479         ret = of_hwspin_lock_get_id_byname(np, "adi");
 480         if (ret < 0) {
 481                 dev_err(&pdev->dev, "can not get the hardware spinlock\n");
 482                 goto put_ctlr;
 483         }
 484
 485         sadi->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret);
 486         if (!sadi->hwlock) {
 487                 ret = -ENXIO;
 488                 goto put_ctlr;
 489         }
 490
 491         sprd_adi_hw_init(sadi);
 492         sprd_adi_set_wdt_rst_mode(sadi);
 493
 494         ctlr->dev.of_node = pdev->dev.of_node;
 495         ctlr->bus_num = pdev->id;
 496         ctlr->num_chipselect = num_chipselect;
 497         ctlr->flags = SPI_MASTER_HALF_DUPLEX;
 498         ctlr->bits_per_word_mask = 0;
 499         ctlr->transfer_one = sprd_adi_transfer_one;
 500
 501         ret = devm_spi_register_controller(&pdev->dev, ctlr);
 502         if (ret) {
 503                 dev_err(&pdev->dev, "failed to register SPI controller\n");
 504                 goto put_ctlr;
 505         }
 506
 507         sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
 508         sadi->restart_handler.priority = 128;
 509         ret = register_restart_handler(&sadi->restart_handler);
 510         if (ret) {
 511                 dev_err(&pdev->dev, "can not register restart handler\n");
 512                 goto put_ctlr;
 513         }
 514
 515         return 0;
 516
 517 put_ctlr:
 518         spi_controller_put(ctlr);
 519         return ret;
 520 }
 521
 522 static int sprd_adi_remove(struct platform_device *pdev)
 523 {
 524         struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
 525         struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
 526
 527         unregister_restart_handler(&sadi->restart_handler);
 528         return 0;
 529 }
 530
 531 static const struct of_device_id sprd_adi_of_match[] = {
 532         {
 533                 .compatible = "sprd,sc9860-adi",
 534         },
 535         { },
 536 };
 537 MODULE_DEVICE_TABLE(of, sprd_adi_of_match);
 538
 539 static struct platform_driver sprd_adi_driver = {
 540         .driver = {
 541                 .name = "sprd-adi",
 542                 .of_match_table = sprd_adi_of_match,
 543         },
 544         .probe = sprd_adi_probe,
 545         .remove = sprd_adi_remove,
 546 };
 547 module_platform_driver(sprd_adi_driver);
 548
 549 MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
 550 MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
 551 MODULE_LICENSE("GPL v2");