drivers/watchdog/qcom-wdt.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
   3  */
   4 #include <linux/clk.h>
   5 #include <linux/delay.h>
   6 #include <linux/io.h>
   7 #include <linux/kernel.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/watchdog.h>
  12 #include <linux/of_device.h>
  13
  14 enum wdt_reg {
  15         WDT_RST,
  16         WDT_EN,
  17         WDT_STS,
  18         WDT_BARK_TIME,
  19         WDT_BITE_TIME,
  20 };
  21
  22 static const u32 reg_offset_data_apcs_tmr[] = {
  23         [WDT_RST] = 0x38,
  24         [WDT_EN] = 0x40,
  25         [WDT_STS] = 0x44,
  26         [WDT_BARK_TIME] = 0x4C,
  27         [WDT_BITE_TIME] = 0x5C,
  28 };
  29
  30 static const u32 reg_offset_data_kpss[] = {
  31         [WDT_RST] = 0x4,
  32         [WDT_EN] = 0x8,
  33         [WDT_STS] = 0xC,
  34         [WDT_BARK_TIME] = 0x10,
  35         [WDT_BITE_TIME] = 0x14,
  36 };
  37
  38 struct qcom_wdt {
  39         struct watchdog_device  wdd;
  40         struct clk              *clk;
  41         unsigned long           rate;
  42         void __iomem            *base;
  43         const u32               *layout;
  44 };
  45
  46 static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
  47 {
  48         return wdt->base + wdt->layout[reg];
  49 }
  50
  51 static inline
  52 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
  53 {
  54         return container_of(wdd, struct qcom_wdt, wdd);
  55 }
  56
  57 static int qcom_wdt_start(struct watchdog_device *wdd)
  58 {
  59         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
  60
  61         writel(0, wdt_addr(wdt, WDT_EN));
  62         writel(1, wdt_addr(wdt, WDT_RST));
  63         writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
  64         writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
  65         writel(1, wdt_addr(wdt, WDT_EN));
  66         return 0;
  67 }
  68
  69 static int qcom_wdt_stop(struct watchdog_device *wdd)
  70 {
  71         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
  72
  73         writel(0, wdt_addr(wdt, WDT_EN));
  74         return 0;
  75 }
  76
  77 static int qcom_wdt_ping(struct watchdog_device *wdd)
  78 {
  79         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
  80
  81         writel(1, wdt_addr(wdt, WDT_RST));
  82         return 0;
  83 }
  84
  85 static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
  86                                 unsigned int timeout)
  87 {
  88         wdd->timeout = timeout;
  89         return qcom_wdt_start(wdd);
  90 }
  91
  92 static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
  93                             void *data)
  94 {
  95         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
  96         u32 timeout;
  97
  98         /*
  99          * Trigger watchdog bite:
 100          *    Setup BITE_TIME to be 128ms, and enable WDT.
 101          */
 102         timeout = 128 * wdt->rate / 1000;
 103
 104         writel(0, wdt_addr(wdt, WDT_EN));
 105         writel(1, wdt_addr(wdt, WDT_RST));
 106         writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
 107         writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
 108         writel(1, wdt_addr(wdt, WDT_EN));
 109
 110         /*
 111          * Actually make sure the above sequence hits hardware before sleeping.
 112          */
 113         wmb();
 114
 115         msleep(150);
 116         return 0;
 117 }
 118
 119 static const struct watchdog_ops qcom_wdt_ops = {
 120         .start          = qcom_wdt_start,
 121         .stop           = qcom_wdt_stop,
 122         .ping           = qcom_wdt_ping,
 123         .set_timeout    = qcom_wdt_set_timeout,
 124         .restart        = qcom_wdt_restart,
 125         .owner          = THIS_MODULE,
 126 };
 127
 128 static const struct watchdog_info qcom_wdt_info = {
 129         .options        = WDIOF_KEEPALIVEPING
 130                         | WDIOF_MAGICCLOSE
 131                         | WDIOF_SETTIMEOUT
 132                         | WDIOF_CARDRESET,
 133         .identity       = KBUILD_MODNAME,
 134 };
 135
 136 static void qcom_clk_disable_unprepare(void *data)
 137 {
 138         clk_disable_unprepare(data);
 139 }
 140
 141 static int qcom_wdt_probe(struct platform_device *pdev)
 142 {
 143         struct device *dev = &pdev->dev;
 144         struct qcom_wdt *wdt;
 145         struct resource *res;
 146         struct device_node *np = dev->of_node;
 147         const u32 *regs;
 148         u32 percpu_offset;
 149         int ret;
 150
 151         regs = of_device_get_match_data(dev);
 152         if (!regs) {
 153                 dev_err(dev, "Unsupported QCOM WDT module\n");
 154                 return -ENODEV;
 155         }
 156
 157         wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
 158         if (!wdt)
 159                 return -ENOMEM;
 160
 161         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 162         if (!res)
 163                 return -ENOMEM;
 164
 165         /* We use CPU0's DGT for the watchdog */
 166         if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
 167                 percpu_offset = 0;
 168
 169         res->start += percpu_offset;
 170         res->end += percpu_offset;
 171
 172         wdt->base = devm_ioremap_resource(dev, res);
 173         if (IS_ERR(wdt->base))
 174                 return PTR_ERR(wdt->base);
 175
 176         wdt->clk = devm_clk_get(dev, NULL);
 177         if (IS_ERR(wdt->clk)) {
 178                 dev_err(dev, "failed to get input clock\n");
 179                 return PTR_ERR(wdt->clk);
 180         }
 181
 182         ret = clk_prepare_enable(wdt->clk);
 183         if (ret) {
 184                 dev_err(dev, "failed to setup clock\n");
 185                 return ret;
 186         }
 187         ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare,
 188                                        wdt->clk);
 189         if (ret)
 190                 return ret;
 191
 192         /*
 193          * We use the clock rate to calculate the max timeout, so ensure it's
 194          * not zero to avoid a divide-by-zero exception.
 195          *
 196          * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
 197          * that it would bite before a second elapses it's usefulness is
 198          * limited.  Bail if this is the case.
 199          */
 200         wdt->rate = clk_get_rate(wdt->clk);
 201         if (wdt->rate == 0 ||
 202             wdt->rate > 0x10000000U) {
 203                 dev_err(dev, "invalid clock rate\n");
 204                 return -EINVAL;
 205         }
 206
 207         wdt->wdd.info = &qcom_wdt_info;
 208         wdt->wdd.ops = &qcom_wdt_ops;
 209         wdt->wdd.min_timeout = 1;
 210         wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
 211         wdt->wdd.parent = dev;
 212         wdt->layout = regs;
 213
 214         if (readl(wdt_addr(wdt, WDT_STS)) & 1)
 215                 wdt->wdd.bootstatus = WDIOF_CARDRESET;
 216
 217         /*
 218          * If 'timeout-sec' unspecified in devicetree, assume a 30 second
 219          * default, unless the max timeout is less than 30 seconds, then use
 220          * the max instead.
 221          */
 222         wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
 223         watchdog_init_timeout(&wdt->wdd, 0, dev);
 224
 225         ret = devm_watchdog_register_device(dev, &wdt->wdd);
 226         if (ret)
 227                 return ret;
 228
 229         platform_set_drvdata(pdev, wdt);
 230         return 0;
 231 }
 232
 233 static int __maybe_unused qcom_wdt_suspend(struct device *dev)
 234 {
 235         struct qcom_wdt *wdt = dev_get_drvdata(dev);
 236
 237         if (watchdog_active(&wdt->wdd))
 238                 qcom_wdt_stop(&wdt->wdd);
 239
 240         return 0;
 241 }
 242
 243 static int __maybe_unused qcom_wdt_resume(struct device *dev)
 244 {
 245         struct qcom_wdt *wdt = dev_get_drvdata(dev);
 246
 247         if (watchdog_active(&wdt->wdd))
 248                 qcom_wdt_start(&wdt->wdd);
 249
 250         return 0;
 251 }
 252
 253 static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
 254
 255 static const struct of_device_id qcom_wdt_of_table[] = {
 256         { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
 257         { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
 258         { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
 259         { },
 260 };
 261 MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
 262
 263 static struct platform_driver qcom_watchdog_driver = {
 264         .probe  = qcom_wdt_probe,
 265         .driver = {
 266                 .name           = KBUILD_MODNAME,
 267                 .of_match_table = qcom_wdt_of_table,
 268                 .pm             = &qcom_wdt_pm_ops,
 269         },
 270 };
 271 module_platform_driver(qcom_watchdog_driver);
 272
 273 MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
 274 MODULE_LICENSE("GPL v2");