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scsi: qla2xxx: Reinstate module parameter ql2xenablemsix
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_os.c
blob84874e6b36def3569cf6b0b00ef7b8a3715a3f0e
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <linux/blk-mq-pci.h>
17 #include <scsi/scsi_tcq.h>
18 #include <scsi/scsicam.h>
19 #include <scsi/scsi_transport.h>
20 #include <scsi/scsi_transport_fc.h>
21
22 #include "qla_target.h"
23
24 /*
25 * Driver version
26 */
27 char qla2x00_version_str[40];
28
29 static int apidev_major;
30
31 /*
32 * SRB allocation cache
33 */
34 struct kmem_cache *srb_cachep;
35
36 /*
37 * CT6 CTX allocation cache
38 */
39 static struct kmem_cache *ctx_cachep;
40 /*
41 * error level for logging
42 */
43 int ql_errlev = ql_log_all;
44
45 static int ql2xenableclass2;
46 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47 MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
51
52 int ql2xlogintimeout = 20;
53 module_param(ql2xlogintimeout, int, S_IRUGO);
54 MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
57 int qlport_down_retry;
58 module_param(qlport_down_retry, int, S_IRUGO);
59 MODULE_PARM_DESC(qlport_down_retry,
60 "Maximum number of command retries to a port that returns "
61 "a PORT-DOWN status.");
62
63 int ql2xplogiabsentdevice;
64 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65 MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
67 "a Fabric scan. This is needed for several broken switches. "
68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
70 int ql2xloginretrycount = 0;
71 module_param(ql2xloginretrycount, int, S_IRUGO);
72 MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
75 int ql2xallocfwdump = 1;
76 module_param(ql2xallocfwdump, int, S_IRUGO);
77 MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
82 int ql2xextended_error_logging;
83 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
84 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
85 MODULE_PARM_DESC(ql2xextended_error_logging,
86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
101 "\t\tDo LOGICAL OR of the value to enable more than one level");
102
103 int ql2xshiftctondsd = 6;
104 module_param(ql2xshiftctondsd, int, S_IRUGO);
105 MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
109 int ql2xfdmienable=1;
110 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
111 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
112 MODULE_PARM_DESC(ql2xfdmienable,
113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
115
116 #define MAX_Q_DEPTH 64
117 static int ql2xmaxqdepth = MAX_Q_DEPTH;
118 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119 MODULE_PARM_DESC(ql2xmaxqdepth,
120 "Maximum queue depth to set for each LUN. "
121 "Default is 64.");
122
123 #if (IS_ENABLED(CONFIG_NVME_FC))
124 int ql2xenabledif;
125 #else
126 int ql2xenabledif = 2;
127 #endif
128 module_param(ql2xenabledif, int, S_IRUGO);
129 MODULE_PARM_DESC(ql2xenabledif,
130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
135
136 #if (IS_ENABLED(CONFIG_NVME_FC))
137 int ql2xnvmeenable = 1;
138 #else
139 int ql2xnvmeenable;
140 #endif
141 module_param(ql2xnvmeenable, int, 0644);
142 MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
146 int ql2xenablehba_err_chk = 2;
147 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148 MODULE_PARM_DESC(ql2xenablehba_err_chk,
149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
150 " Default is 2.\n"
151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
154
155 int ql2xiidmaenable=1;
156 module_param(ql2xiidmaenable, int, S_IRUGO);
157 MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
161 int ql2xmqsupport = 1;
162 module_param(ql2xmqsupport, int, S_IRUGO);
163 MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
167
168 int ql2xfwloadbin;
169 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
170 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
171 MODULE_PARM_DESC(ql2xfwloadbin,
172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
178 int ql2xetsenable;
179 module_param(ql2xetsenable, int, S_IRUGO);
180 MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
184 int ql2xdbwr = 1;
185 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
186 MODULE_PARM_DESC(ql2xdbwr,
187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
190
191 int ql2xtargetreset = 1;
192 module_param(ql2xtargetreset, int, S_IRUGO);
193 MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
197 int ql2xgffidenable;
198 module_param(ql2xgffidenable, int, S_IRUGO);
199 MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
202
203 int ql2xasynctmfenable = 1;
204 module_param(ql2xasynctmfenable, int, S_IRUGO);
205 MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
208
209 int ql2xdontresethba;
210 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
211 MODULE_PARM_DESC(ql2xdontresethba,
212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
215
216 uint64_t ql2xmaxlun = MAX_LUNS;
217 module_param(ql2xmaxlun, ullong, S_IRUGO);
218 MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
222 int ql2xmdcapmask = 0x1F;
223 module_param(ql2xmdcapmask, int, S_IRUGO);
224 MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
227
228 int ql2xmdenable = 1;
229 module_param(ql2xmdenable, int, S_IRUGO);
230 MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
234
235 int ql2xexlogins = 0;
236 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237 MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
241 int ql2xexchoffld = 1024;
242 module_param(ql2xexchoffld, uint, 0644);
243 MODULE_PARM_DESC(ql2xexchoffld,
244 "Number of target exchanges.");
245
246 int ql2xiniexchg = 1024;
247 module_param(ql2xiniexchg, uint, 0644);
248 MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
250
251 int ql2xfwholdabts = 0;
252 module_param(ql2xfwholdabts, int, S_IRUGO);
253 MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
258 int ql2xmvasynctoatio = 1;
259 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260 MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
265 int ql2xautodetectsfp = 1;
266 module_param(ql2xautodetectsfp, int, 0444);
267 MODULE_PARM_DESC(ql2xautodetectsfp,
268 "Detect SFP range and set appropriate distance.\n"
269 "1 (Default): Enable\n");
270
271 int ql2xenablemsix = 1;
272 module_param(ql2xenablemsix, int, 0444);
273 MODULE_PARM_DESC(ql2xenablemsix,
274 "Set to enable MSI or MSI-X interrupt mechanism.\n"
275 " Default is 1, enable MSI-X interrupt mechanism.\n"
276 " 0 -- enable traditional pin-based mechanism.\n"
277 " 1 -- enable MSI-X interrupt mechanism.\n"
278 " 2 -- enable MSI interrupt mechanism.\n");
279
280 /*
281 * SCSI host template entry points
282 */
283 static int qla2xxx_slave_configure(struct scsi_device * device);
284 static int qla2xxx_slave_alloc(struct scsi_device *);
285 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
286 static void qla2xxx_scan_start(struct Scsi_Host *);
287 static void qla2xxx_slave_destroy(struct scsi_device *);
288 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
289 static int qla2xxx_eh_abort(struct scsi_cmnd *);
290 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
291 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
292 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
293 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
294
295 static void qla2x00_clear_drv_active(struct qla_hw_data *);
296 static void qla2x00_free_device(scsi_qla_host_t *);
297 static void qla83xx_disable_laser(scsi_qla_host_t *vha);
298 static int qla2xxx_map_queues(struct Scsi_Host *shost);
299 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
300
301 struct scsi_host_template qla2xxx_driver_template = {
302 .module = THIS_MODULE,
303 .name = QLA2XXX_DRIVER_NAME,
304 .queuecommand = qla2xxx_queuecommand,
305
306 .eh_timed_out = fc_eh_timed_out,
307 .eh_abort_handler = qla2xxx_eh_abort,
308 .eh_device_reset_handler = qla2xxx_eh_device_reset,
309 .eh_target_reset_handler = qla2xxx_eh_target_reset,
310 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
311 .eh_host_reset_handler = qla2xxx_eh_host_reset,
312
313 .slave_configure = qla2xxx_slave_configure,
314
315 .slave_alloc = qla2xxx_slave_alloc,
316 .slave_destroy = qla2xxx_slave_destroy,
317 .scan_finished = qla2xxx_scan_finished,
318 .scan_start = qla2xxx_scan_start,
319 .change_queue_depth = scsi_change_queue_depth,
320 .map_queues = qla2xxx_map_queues,
321 .this_id = -1,
322 .cmd_per_lun = 3,
323 .use_clustering = ENABLE_CLUSTERING,
324 .sg_tablesize = SG_ALL,
325
326 .max_sectors = 0xFFFF,
327 .shost_attrs = qla2x00_host_attrs,
328
329 .supported_mode = MODE_INITIATOR,
330 .track_queue_depth = 1,
331 };
332
333 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
334 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
335
336 /* TODO Convert to inlines
337 *
338 * Timer routines
339 */
340
341 __inline__ void
342 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
343 {
344 init_timer(&vha->timer);
345 vha->timer.expires = jiffies + interval * HZ;
346 vha->timer.data = (unsigned long)vha;
347 vha->timer.function = (void (*)(unsigned long))func;
348 add_timer(&vha->timer);
349 vha->timer_active = 1;
350 }
351
352 static inline void
353 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
354 {
355 /* Currently used for 82XX only. */
356 if (vha->device_flags & DFLG_DEV_FAILED) {
357 ql_dbg(ql_dbg_timer, vha, 0x600d,
358 "Device in a failed state, returning.\n");
359 return;
360 }
361
362 mod_timer(&vha->timer, jiffies + interval * HZ);
363 }
364
365 static __inline__ void
366 qla2x00_stop_timer(scsi_qla_host_t *vha)
367 {
368 del_timer_sync(&vha->timer);
369 vha->timer_active = 0;
370 }
371
372 static int qla2x00_do_dpc(void *data);
373
374 static void qla2x00_rst_aen(scsi_qla_host_t *);
375
376 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
377 struct req_que **, struct rsp_que **);
378 static void qla2x00_free_fw_dump(struct qla_hw_data *);
379 static void qla2x00_mem_free(struct qla_hw_data *);
380 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
381 struct qla_qpair *qpair);
382
383 /* -------------------------------------------------------------------------- */
384 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
385 struct rsp_que *rsp)
386 {
387 struct qla_hw_data *ha = vha->hw;
388 rsp->qpair = ha->base_qpair;
389 rsp->req = req;
390 ha->base_qpair->req = req;
391 ha->base_qpair->rsp = rsp;
392 ha->base_qpair->vha = vha;
393 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
394 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
395 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
396 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
397 INIT_LIST_HEAD(&ha->base_qpair->nvme_done_list);
398 ha->base_qpair->enable_class_2 = ql2xenableclass2;
399 /* init qpair to this cpu. Will adjust at run time. */
400 qla_cpu_update(rsp->qpair, smp_processor_id());
401 ha->base_qpair->pdev = ha->pdev;
402
403 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
404 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
405 }
406
407 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
408 struct rsp_que *rsp)
409 {
410 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
411 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
412 GFP_KERNEL);
413 if (!ha->req_q_map) {
414 ql_log(ql_log_fatal, vha, 0x003b,
415 "Unable to allocate memory for request queue ptrs.\n");
416 goto fail_req_map;
417 }
418
419 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
420 GFP_KERNEL);
421 if (!ha->rsp_q_map) {
422 ql_log(ql_log_fatal, vha, 0x003c,
423 "Unable to allocate memory for response queue ptrs.\n");
424 goto fail_rsp_map;
425 }
426
427 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
428 if (ha->base_qpair == NULL) {
429 ql_log(ql_log_warn, vha, 0x00e0,
430 "Failed to allocate base queue pair memory.\n");
431 goto fail_base_qpair;
432 }
433
434 qla_init_base_qpair(vha, req, rsp);
435
436 if (ql2xmqsupport && ha->max_qpairs) {
437 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
438 GFP_KERNEL);
439 if (!ha->queue_pair_map) {
440 ql_log(ql_log_fatal, vha, 0x0180,
441 "Unable to allocate memory for queue pair ptrs.\n");
442 goto fail_qpair_map;
443 }
444 }
445
446 /*
447 * Make sure we record at least the request and response queue zero in
448 * case we need to free them if part of the probe fails.
449 */
450 ha->rsp_q_map[0] = rsp;
451 ha->req_q_map[0] = req;
452 set_bit(0, ha->rsp_qid_map);
453 set_bit(0, ha->req_qid_map);
454 return 1;
455
456 fail_qpair_map:
457 kfree(ha->base_qpair);
458 ha->base_qpair = NULL;
459 fail_base_qpair:
460 kfree(ha->rsp_q_map);
461 ha->rsp_q_map = NULL;
462 fail_rsp_map:
463 kfree(ha->req_q_map);
464 ha->req_q_map = NULL;
465 fail_req_map:
466 return -ENOMEM;
467 }
468
469 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
470 {
471 if (IS_QLAFX00(ha)) {
472 if (req && req->ring_fx00)
473 dma_free_coherent(&ha->pdev->dev,
474 (req->length_fx00 + 1) * sizeof(request_t),
475 req->ring_fx00, req->dma_fx00);
476 } else if (req && req->ring)
477 dma_free_coherent(&ha->pdev->dev,
478 (req->length + 1) * sizeof(request_t),
479 req->ring, req->dma);
480
481 if (req)
482 kfree(req->outstanding_cmds);
483
484 kfree(req);
485 }
486
487 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
488 {
489 if (IS_QLAFX00(ha)) {
490 if (rsp && rsp->ring)
491 dma_free_coherent(&ha->pdev->dev,
492 (rsp->length_fx00 + 1) * sizeof(request_t),
493 rsp->ring_fx00, rsp->dma_fx00);
494 } else if (rsp && rsp->ring) {
495 dma_free_coherent(&ha->pdev->dev,
496 (rsp->length + 1) * sizeof(response_t),
497 rsp->ring, rsp->dma);
498 }
499 kfree(rsp);
500 }
501
502 static void qla2x00_free_queues(struct qla_hw_data *ha)
503 {
504 struct req_que *req;
505 struct rsp_que *rsp;
506 int cnt;
507 unsigned long flags;
508
509 if (ha->queue_pair_map) {
510 kfree(ha->queue_pair_map);
511 ha->queue_pair_map = NULL;
512 }
513 if (ha->base_qpair) {
514 kfree(ha->base_qpair);
515 ha->base_qpair = NULL;
516 }
517
518 spin_lock_irqsave(&ha->hardware_lock, flags);
519 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
520 if (!test_bit(cnt, ha->req_qid_map))
521 continue;
522
523 req = ha->req_q_map[cnt];
524 clear_bit(cnt, ha->req_qid_map);
525 ha->req_q_map[cnt] = NULL;
526
527 spin_unlock_irqrestore(&ha->hardware_lock, flags);
528 qla2x00_free_req_que(ha, req);
529 spin_lock_irqsave(&ha->hardware_lock, flags);
530 }
531 spin_unlock_irqrestore(&ha->hardware_lock, flags);
532
533 kfree(ha->req_q_map);
534 ha->req_q_map = NULL;
535
536
537 spin_lock_irqsave(&ha->hardware_lock, flags);
538 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
539 if (!test_bit(cnt, ha->rsp_qid_map))
540 continue;
541
542 rsp = ha->rsp_q_map[cnt];
543 clear_bit(cnt, ha->rsp_qid_map);
544 ha->rsp_q_map[cnt] = NULL;
545 spin_unlock_irqrestore(&ha->hardware_lock, flags);
546 qla2x00_free_rsp_que(ha, rsp);
547 spin_lock_irqsave(&ha->hardware_lock, flags);
548 }
549 spin_unlock_irqrestore(&ha->hardware_lock, flags);
550
551 kfree(ha->rsp_q_map);
552 ha->rsp_q_map = NULL;
553 }
554
555 static char *
556 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
557 {
558 struct qla_hw_data *ha = vha->hw;
559 static char *pci_bus_modes[] = {
560 "33", "66", "100", "133",
561 };
562 uint16_t pci_bus;
563
564 strcpy(str, "PCI");
565 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
566 if (pci_bus) {
567 strcat(str, "-X (");
568 strcat(str, pci_bus_modes[pci_bus]);
569 } else {
570 pci_bus = (ha->pci_attr & BIT_8) >> 8;
571 strcat(str, " (");
572 strcat(str, pci_bus_modes[pci_bus]);
573 }
574 strcat(str, " MHz)");
575
576 return (str);
577 }
578
579 static char *
580 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
581 {
582 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
583 struct qla_hw_data *ha = vha->hw;
584 uint32_t pci_bus;
585
586 if (pci_is_pcie(ha->pdev)) {
587 char lwstr[6];
588 uint32_t lstat, lspeed, lwidth;
589
590 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
591 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
592 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
593
594 strcpy(str, "PCIe (");
595 switch (lspeed) {
596 case 1:
597 strcat(str, "2.5GT/s ");
598 break;
599 case 2:
600 strcat(str, "5.0GT/s ");
601 break;
602 case 3:
603 strcat(str, "8.0GT/s ");
604 break;
605 default:
606 strcat(str, "<unknown> ");
607 break;
608 }
609 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
610 strcat(str, lwstr);
611
612 return str;
613 }
614
615 strcpy(str, "PCI");
616 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
617 if (pci_bus == 0 || pci_bus == 8) {
618 strcat(str, " (");
619 strcat(str, pci_bus_modes[pci_bus >> 3]);
620 } else {
621 strcat(str, "-X ");
622 if (pci_bus & BIT_2)
623 strcat(str, "Mode 2");
624 else
625 strcat(str, "Mode 1");
626 strcat(str, " (");
627 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
628 }
629 strcat(str, " MHz)");
630
631 return str;
632 }
633
634 static char *
635 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
636 {
637 char un_str[10];
638 struct qla_hw_data *ha = vha->hw;
639
640 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
641 ha->fw_minor_version, ha->fw_subminor_version);
642
643 if (ha->fw_attributes & BIT_9) {
644 strcat(str, "FLX");
645 return (str);
646 }
647
648 switch (ha->fw_attributes & 0xFF) {
649 case 0x7:
650 strcat(str, "EF");
651 break;
652 case 0x17:
653 strcat(str, "TP");
654 break;
655 case 0x37:
656 strcat(str, "IP");
657 break;
658 case 0x77:
659 strcat(str, "VI");
660 break;
661 default:
662 sprintf(un_str, "(%x)", ha->fw_attributes);
663 strcat(str, un_str);
664 break;
665 }
666 if (ha->fw_attributes & 0x100)
667 strcat(str, "X");
668
669 return (str);
670 }
671
672 static char *
673 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
674 {
675 struct qla_hw_data *ha = vha->hw;
676
677 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
678 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
679 return str;
680 }
681
682 void
683 qla2x00_sp_free_dma(void *ptr)
684 {
685 srb_t *sp = ptr;
686 struct qla_hw_data *ha = sp->vha->hw;
687 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
688 void *ctx = GET_CMD_CTX_SP(sp);
689
690 if (sp->flags & SRB_DMA_VALID) {
691 scsi_dma_unmap(cmd);
692 sp->flags &= ~SRB_DMA_VALID;
693 }
694
695 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
696 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
697 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
698 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
699 }
700
701 if (!ctx)
702 goto end;
703
704 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
705 /* List assured to be having elements */
706 qla2x00_clean_dsd_pool(ha, ctx);
707 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
708 }
709
710 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
711 struct crc_context *ctx0 = ctx;
712
713 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
714 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
715 }
716
717 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
718 struct ct6_dsd *ctx1 = ctx;
719
720 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
721 ctx1->fcp_cmnd_dma);
722 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
723 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
724 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
725 mempool_free(ctx1, ha->ctx_mempool);
726 }
727
728 end:
729 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
730 CMD_SP(cmd) = NULL;
731 qla2x00_rel_sp(sp);
732 }
733 }
734
735 void
736 qla2x00_sp_compl(void *ptr, int res)
737 {
738 srb_t *sp = ptr;
739 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
740
741 cmd->result = res;
742
743 if (atomic_read(&sp->ref_count) == 0) {
744 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
745 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
746 sp, GET_CMD_SP(sp));
747 if (ql2xextended_error_logging & ql_dbg_io)
748 WARN_ON(atomic_read(&sp->ref_count) == 0);
749 return;
750 }
751 if (!atomic_dec_and_test(&sp->ref_count))
752 return;
753
754 sp->free(sp);
755 cmd->scsi_done(cmd);
756 }
757
758 void
759 qla2xxx_qpair_sp_free_dma(void *ptr)
760 {
761 srb_t *sp = (srb_t *)ptr;
762 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
763 struct qla_hw_data *ha = sp->fcport->vha->hw;
764 void *ctx = GET_CMD_CTX_SP(sp);
765
766 if (sp->flags & SRB_DMA_VALID) {
767 scsi_dma_unmap(cmd);
768 sp->flags &= ~SRB_DMA_VALID;
769 }
770
771 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
772 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
773 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
774 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
775 }
776
777 if (!ctx)
778 goto end;
779
780 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
781 /* List assured to be having elements */
782 qla2x00_clean_dsd_pool(ha, ctx);
783 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
784 }
785
786 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
787 struct crc_context *ctx0 = ctx;
788
789 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
790 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
791 }
792
793 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
794 struct ct6_dsd *ctx1 = ctx;
795 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
796 ctx1->fcp_cmnd_dma);
797 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
798 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
799 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
800 mempool_free(ctx1, ha->ctx_mempool);
801 }
802 end:
803 CMD_SP(cmd) = NULL;
804 qla2xxx_rel_qpair_sp(sp->qpair, sp);
805 }
806
807 void
808 qla2xxx_qpair_sp_compl(void *ptr, int res)
809 {
810 srb_t *sp = ptr;
811 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
812
813 cmd->result = res;
814
815 if (atomic_read(&sp->ref_count) == 0) {
816 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
817 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
818 sp, GET_CMD_SP(sp));
819 if (ql2xextended_error_logging & ql_dbg_io)
820 WARN_ON(atomic_read(&sp->ref_count) == 0);
821 return;
822 }
823 if (!atomic_dec_and_test(&sp->ref_count))
824 return;
825
826 sp->free(sp);
827 cmd->scsi_done(cmd);
828 }
829
830 /* If we are SP1 here, we need to still take and release the host_lock as SP1
831 * does not have the changes necessary to avoid taking host->host_lock.
832 */
833 static int
834 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
835 {
836 scsi_qla_host_t *vha = shost_priv(host);
837 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
838 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
839 struct qla_hw_data *ha = vha->hw;
840 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
841 srb_t *sp;
842 int rval;
843 struct qla_qpair *qpair = NULL;
844 uint32_t tag;
845 uint16_t hwq;
846
847 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
848 cmd->result = DID_NO_CONNECT << 16;
849 goto qc24_fail_command;
850 }
851
852 if (ha->mqenable) {
853 if (shost_use_blk_mq(vha->host)) {
854 tag = blk_mq_unique_tag(cmd->request);
855 hwq = blk_mq_unique_tag_to_hwq(tag);
856 qpair = ha->queue_pair_map[hwq];
857 } else if (vha->vp_idx && vha->qpair) {
858 qpair = vha->qpair;
859 }
860
861 if (qpair)
862 return qla2xxx_mqueuecommand(host, cmd, qpair);
863 }
864
865 if (ha->flags.eeh_busy) {
866 if (ha->flags.pci_channel_io_perm_failure) {
867 ql_dbg(ql_dbg_aer, vha, 0x9010,
868 "PCI Channel IO permanent failure, exiting "
869 "cmd=%p.\n", cmd);
870 cmd->result = DID_NO_CONNECT << 16;
871 } else {
872 ql_dbg(ql_dbg_aer, vha, 0x9011,
873 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
874 cmd->result = DID_REQUEUE << 16;
875 }
876 goto qc24_fail_command;
877 }
878
879 rval = fc_remote_port_chkready(rport);
880 if (rval) {
881 cmd->result = rval;
882 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
883 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
884 cmd, rval);
885 goto qc24_fail_command;
886 }
887
888 if (!vha->flags.difdix_supported &&
889 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
890 ql_dbg(ql_dbg_io, vha, 0x3004,
891 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
892 cmd);
893 cmd->result = DID_NO_CONNECT << 16;
894 goto qc24_fail_command;
895 }
896
897 if (!fcport) {
898 cmd->result = DID_NO_CONNECT << 16;
899 goto qc24_fail_command;
900 }
901
902 if (atomic_read(&fcport->state) != FCS_ONLINE) {
903 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
904 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
905 ql_dbg(ql_dbg_io, vha, 0x3005,
906 "Returning DNC, fcport_state=%d loop_state=%d.\n",
907 atomic_read(&fcport->state),
908 atomic_read(&base_vha->loop_state));
909 cmd->result = DID_NO_CONNECT << 16;
910 goto qc24_fail_command;
911 }
912 goto qc24_target_busy;
913 }
914
915 /*
916 * Return target busy if we've received a non-zero retry_delay_timer
917 * in a FCP_RSP.
918 */
919 if (fcport->retry_delay_timestamp == 0) {
920 /* retry delay not set */
921 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
922 fcport->retry_delay_timestamp = 0;
923 else
924 goto qc24_target_busy;
925
926 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
927 if (!sp)
928 goto qc24_host_busy;
929
930 sp->u.scmd.cmd = cmd;
931 sp->type = SRB_SCSI_CMD;
932 atomic_set(&sp->ref_count, 1);
933 CMD_SP(cmd) = (void *)sp;
934 sp->free = qla2x00_sp_free_dma;
935 sp->done = qla2x00_sp_compl;
936
937 rval = ha->isp_ops->start_scsi(sp);
938 if (rval != QLA_SUCCESS) {
939 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
940 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
941 goto qc24_host_busy_free_sp;
942 }
943
944 return 0;
945
946 qc24_host_busy_free_sp:
947 sp->free(sp);
948
949 qc24_host_busy:
950 return SCSI_MLQUEUE_HOST_BUSY;
951
952 qc24_target_busy:
953 return SCSI_MLQUEUE_TARGET_BUSY;
954
955 qc24_fail_command:
956 cmd->scsi_done(cmd);
957
958 return 0;
959 }
960
961 /* For MQ supported I/O */
962 int
963 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
964 struct qla_qpair *qpair)
965 {
966 scsi_qla_host_t *vha = shost_priv(host);
967 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
968 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
969 struct qla_hw_data *ha = vha->hw;
970 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
971 srb_t *sp;
972 int rval;
973
974 rval = fc_remote_port_chkready(rport);
975 if (rval) {
976 cmd->result = rval;
977 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
978 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
979 cmd, rval);
980 goto qc24_fail_command;
981 }
982
983 if (!fcport) {
984 cmd->result = DID_NO_CONNECT << 16;
985 goto qc24_fail_command;
986 }
987
988 if (atomic_read(&fcport->state) != FCS_ONLINE) {
989 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
990 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
991 ql_dbg(ql_dbg_io, vha, 0x3077,
992 "Returning DNC, fcport_state=%d loop_state=%d.\n",
993 atomic_read(&fcport->state),
994 atomic_read(&base_vha->loop_state));
995 cmd->result = DID_NO_CONNECT << 16;
996 goto qc24_fail_command;
997 }
998 goto qc24_target_busy;
999 }
1000
1001 /*
1002 * Return target busy if we've received a non-zero retry_delay_timer
1003 * in a FCP_RSP.
1004 */
1005 if (fcport->retry_delay_timestamp == 0) {
1006 /* retry delay not set */
1007 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1008 fcport->retry_delay_timestamp = 0;
1009 else
1010 goto qc24_target_busy;
1011
1012 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
1013 if (!sp)
1014 goto qc24_host_busy;
1015
1016 sp->u.scmd.cmd = cmd;
1017 sp->type = SRB_SCSI_CMD;
1018 atomic_set(&sp->ref_count, 1);
1019 CMD_SP(cmd) = (void *)sp;
1020 sp->free = qla2xxx_qpair_sp_free_dma;
1021 sp->done = qla2xxx_qpair_sp_compl;
1022 sp->qpair = qpair;
1023
1024 rval = ha->isp_ops->start_scsi_mq(sp);
1025 if (rval != QLA_SUCCESS) {
1026 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1027 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1028 if (rval == QLA_INTERFACE_ERROR)
1029 goto qc24_fail_command;
1030 goto qc24_host_busy_free_sp;
1031 }
1032
1033 return 0;
1034
1035 qc24_host_busy_free_sp:
1036 sp->free(sp);
1037
1038 qc24_host_busy:
1039 return SCSI_MLQUEUE_HOST_BUSY;
1040
1041 qc24_target_busy:
1042 return SCSI_MLQUEUE_TARGET_BUSY;
1043
1044 qc24_fail_command:
1045 cmd->scsi_done(cmd);
1046
1047 return 0;
1048 }
1049
1050 /*
1051 * qla2x00_eh_wait_on_command
1052 * Waits for the command to be returned by the Firmware for some
1053 * max time.
1054 *
1055 * Input:
1056 * cmd = Scsi Command to wait on.
1057 *
1058 * Return:
1059 * Not Found : 0
1060 * Found : 1
1061 */
1062 static int
1063 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1064 {
1065 #define ABORT_POLLING_PERIOD 1000
1066 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1067 unsigned long wait_iter = ABORT_WAIT_ITER;
1068 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1069 struct qla_hw_data *ha = vha->hw;
1070 int ret = QLA_SUCCESS;
1071
1072 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
1073 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1074 "Return:eh_wait.\n");
1075 return ret;
1076 }
1077
1078 while (CMD_SP(cmd) && wait_iter--) {
1079 msleep(ABORT_POLLING_PERIOD);
1080 }
1081 if (CMD_SP(cmd))
1082 ret = QLA_FUNCTION_FAILED;
1083
1084 return ret;
1085 }
1086
1087 /*
1088 * qla2x00_wait_for_hba_online
1089 * Wait till the HBA is online after going through
1090 * <= MAX_RETRIES_OF_ISP_ABORT or
1091 * finally HBA is disabled ie marked offline
1092 *
1093 * Input:
1094 * ha - pointer to host adapter structure
1095 *
1096 * Note:
1097 * Does context switching-Release SPIN_LOCK
1098 * (if any) before calling this routine.
1099 *
1100 * Return:
1101 * Success (Adapter is online) : 0
1102 * Failed (Adapter is offline/disabled) : 1
1103 */
1104 int
1105 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1106 {
1107 int return_status;
1108 unsigned long wait_online;
1109 struct qla_hw_data *ha = vha->hw;
1110 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1111
1112 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1113 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1114 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1115 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1116 ha->dpc_active) && time_before(jiffies, wait_online)) {
1117
1118 msleep(1000);
1119 }
1120 if (base_vha->flags.online)
1121 return_status = QLA_SUCCESS;
1122 else
1123 return_status = QLA_FUNCTION_FAILED;
1124
1125 return (return_status);
1126 }
1127
1128 static inline int test_fcport_count(scsi_qla_host_t *vha)
1129 {
1130 struct qla_hw_data *ha = vha->hw;
1131 unsigned long flags;
1132 int res;
1133
1134 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1135 ql_dbg(ql_dbg_init, vha, 0x00ec,
1136 "tgt %p, fcport_count=%d\n",
1137 vha, vha->fcport_count);
1138 res = (vha->fcport_count == 0);
1139 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1140
1141 return res;
1142 }
1143
1144 /*
1145 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1146 * it has dependency on UNLOADING flag to stop device discovery
1147 */
1148 static void
1149 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1150 {
1151 qla2x00_mark_all_devices_lost(vha, 0);
1152
1153 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
1154 }
1155
1156 /*
1157 * qla2x00_wait_for_hba_ready
1158 * Wait till the HBA is ready before doing driver unload
1159 *
1160 * Input:
1161 * ha - pointer to host adapter structure
1162 *
1163 * Note:
1164 * Does context switching-Release SPIN_LOCK
1165 * (if any) before calling this routine.
1166 *
1167 */
1168 static void
1169 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1170 {
1171 struct qla_hw_data *ha = vha->hw;
1172 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1173
1174 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1175 ha->flags.mbox_busy) ||
1176 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1177 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1178 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1179 break;
1180 msleep(1000);
1181 }
1182 }
1183
1184 int
1185 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1186 {
1187 int return_status;
1188 unsigned long wait_reset;
1189 struct qla_hw_data *ha = vha->hw;
1190 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1191
1192 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1193 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1194 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1195 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1196 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1197
1198 msleep(1000);
1199
1200 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1201 ha->flags.chip_reset_done)
1202 break;
1203 }
1204 if (ha->flags.chip_reset_done)
1205 return_status = QLA_SUCCESS;
1206 else
1207 return_status = QLA_FUNCTION_FAILED;
1208
1209 return return_status;
1210 }
1211
1212 static void
1213 sp_get(struct srb *sp)
1214 {
1215 atomic_inc(&sp->ref_count);
1216 }
1217
1218 #define ISP_REG_DISCONNECT 0xffffffffU
1219 /**************************************************************************
1220 * qla2x00_isp_reg_stat
1221 *
1222 * Description:
1223 * Read the host status register of ISP before aborting the command.
1224 *
1225 * Input:
1226 * ha = pointer to host adapter structure.
1227 *
1228 *
1229 * Returns:
1230 * Either true or false.
1231 *
1232 * Note: Return true if there is register disconnect.
1233 **************************************************************************/
1234 static inline
1235 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1236 {
1237 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1238 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
1239
1240 if (IS_P3P_TYPE(ha))
1241 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1242 else
1243 return ((RD_REG_DWORD(&reg->host_status)) ==
1244 ISP_REG_DISCONNECT);
1245 }
1246
1247 /**************************************************************************
1248 * qla2xxx_eh_abort
1249 *
1250 * Description:
1251 * The abort function will abort the specified command.
1252 *
1253 * Input:
1254 * cmd = Linux SCSI command packet to be aborted.
1255 *
1256 * Returns:
1257 * Either SUCCESS or FAILED.
1258 *
1259 * Note:
1260 * Only return FAILED if command not returned by firmware.
1261 **************************************************************************/
1262 static int
1263 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1264 {
1265 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1266 srb_t *sp;
1267 int ret;
1268 unsigned int id;
1269 uint64_t lun;
1270 unsigned long flags;
1271 int rval, wait = 0;
1272 struct qla_hw_data *ha = vha->hw;
1273
1274 if (qla2x00_isp_reg_stat(ha)) {
1275 ql_log(ql_log_info, vha, 0x8042,
1276 "PCI/Register disconnect, exiting.\n");
1277 return FAILED;
1278 }
1279 if (!CMD_SP(cmd))
1280 return SUCCESS;
1281
1282 ret = fc_block_scsi_eh(cmd);
1283 if (ret != 0)
1284 return ret;
1285 ret = SUCCESS;
1286
1287 id = cmd->device->id;
1288 lun = cmd->device->lun;
1289
1290 spin_lock_irqsave(&ha->hardware_lock, flags);
1291 sp = (srb_t *) CMD_SP(cmd);
1292 if (!sp) {
1293 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1294 return SUCCESS;
1295 }
1296
1297 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1298 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1299 vha->host_no, id, lun, sp, cmd, sp->handle);
1300
1301 /* Get a reference to the sp and drop the lock.*/
1302 sp_get(sp);
1303
1304 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1305 rval = ha->isp_ops->abort_command(sp);
1306 if (rval) {
1307 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
1308 ret = SUCCESS;
1309 else
1310 ret = FAILED;
1311
1312 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1313 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
1314 } else {
1315 ql_dbg(ql_dbg_taskm, vha, 0x8004,
1316 "Abort command mbx success cmd=%p.\n", cmd);
1317 wait = 1;
1318 }
1319
1320 spin_lock_irqsave(&ha->hardware_lock, flags);
1321 sp->done(sp, 0);
1322 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1323
1324 /* Did the command return during mailbox execution? */
1325 if (ret == FAILED && !CMD_SP(cmd))
1326 ret = SUCCESS;
1327
1328 /* Wait for the command to be returned. */
1329 if (wait) {
1330 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
1331 ql_log(ql_log_warn, vha, 0x8006,
1332 "Abort handler timed out cmd=%p.\n", cmd);
1333 ret = FAILED;
1334 }
1335 }
1336
1337 ql_log(ql_log_info, vha, 0x801c,
1338 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
1339 vha->host_no, id, lun, wait, ret);
1340
1341 return ret;
1342 }
1343
1344 int
1345 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1346 uint64_t l, enum nexus_wait_type type)
1347 {
1348 int cnt, match, status;
1349 unsigned long flags;
1350 struct qla_hw_data *ha = vha->hw;
1351 struct req_que *req;
1352 srb_t *sp;
1353 struct scsi_cmnd *cmd;
1354
1355 status = QLA_SUCCESS;
1356
1357 spin_lock_irqsave(&ha->hardware_lock, flags);
1358 req = vha->req;
1359 for (cnt = 1; status == QLA_SUCCESS &&
1360 cnt < req->num_outstanding_cmds; cnt++) {
1361 sp = req->outstanding_cmds[cnt];
1362 if (!sp)
1363 continue;
1364 if (sp->type != SRB_SCSI_CMD)
1365 continue;
1366 if (vha->vp_idx != sp->vha->vp_idx)
1367 continue;
1368 match = 0;
1369 cmd = GET_CMD_SP(sp);
1370 switch (type) {
1371 case WAIT_HOST:
1372 match = 1;
1373 break;
1374 case WAIT_TARGET:
1375 match = cmd->device->id == t;
1376 break;
1377 case WAIT_LUN:
1378 match = (cmd->device->id == t &&
1379 cmd->device->lun == l);
1380 break;
1381 }
1382 if (!match)
1383 continue;
1384
1385 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1386 status = qla2x00_eh_wait_on_command(cmd);
1387 spin_lock_irqsave(&ha->hardware_lock, flags);
1388 }
1389 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1390
1391 return status;
1392 }
1393
1394 static char *reset_errors[] = {
1395 "HBA not online",
1396 "HBA not ready",
1397 "Task management failed",
1398 "Waiting for command completions",
1399 };
1400
1401 static int
1402 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1403 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1404 {
1405 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1406 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1407 int err;
1408
1409 if (!fcport) {
1410 return FAILED;
1411 }
1412
1413 err = fc_block_scsi_eh(cmd);
1414 if (err != 0)
1415 return err;
1416
1417 ql_log(ql_log_info, vha, 0x8009,
1418 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1419 cmd->device->id, cmd->device->lun, cmd);
1420
1421 err = 0;
1422 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1423 ql_log(ql_log_warn, vha, 0x800a,
1424 "Wait for hba online failed for cmd=%p.\n", cmd);
1425 goto eh_reset_failed;
1426 }
1427 err = 2;
1428 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1429 != QLA_SUCCESS) {
1430 ql_log(ql_log_warn, vha, 0x800c,
1431 "do_reset failed for cmd=%p.\n", cmd);
1432 goto eh_reset_failed;
1433 }
1434 err = 3;
1435 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1436 cmd->device->lun, type) != QLA_SUCCESS) {
1437 ql_log(ql_log_warn, vha, 0x800d,
1438 "wait for pending cmds failed for cmd=%p.\n", cmd);
1439 goto eh_reset_failed;
1440 }
1441
1442 ql_log(ql_log_info, vha, 0x800e,
1443 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1444 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1445
1446 return SUCCESS;
1447
1448 eh_reset_failed:
1449 ql_log(ql_log_info, vha, 0x800f,
1450 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1451 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1452 cmd);
1453 return FAILED;
1454 }
1455
1456 static int
1457 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1458 {
1459 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1460 struct qla_hw_data *ha = vha->hw;
1461
1462 if (qla2x00_isp_reg_stat(ha)) {
1463 ql_log(ql_log_info, vha, 0x803e,
1464 "PCI/Register disconnect, exiting.\n");
1465 return FAILED;
1466 }
1467
1468 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1469 ha->isp_ops->lun_reset);
1470 }
1471
1472 static int
1473 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1474 {
1475 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1476 struct qla_hw_data *ha = vha->hw;
1477
1478 if (qla2x00_isp_reg_stat(ha)) {
1479 ql_log(ql_log_info, vha, 0x803f,
1480 "PCI/Register disconnect, exiting.\n");
1481 return FAILED;
1482 }
1483
1484 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1485 ha->isp_ops->target_reset);
1486 }
1487
1488 /**************************************************************************
1489 * qla2xxx_eh_bus_reset
1490 *
1491 * Description:
1492 * The bus reset function will reset the bus and abort any executing
1493 * commands.
1494 *
1495 * Input:
1496 * cmd = Linux SCSI command packet of the command that cause the
1497 * bus reset.
1498 *
1499 * Returns:
1500 * SUCCESS/FAILURE (defined as macro in scsi.h).
1501 *
1502 **************************************************************************/
1503 static int
1504 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1505 {
1506 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1507 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1508 int ret = FAILED;
1509 unsigned int id;
1510 uint64_t lun;
1511 struct qla_hw_data *ha = vha->hw;
1512
1513 if (qla2x00_isp_reg_stat(ha)) {
1514 ql_log(ql_log_info, vha, 0x8040,
1515 "PCI/Register disconnect, exiting.\n");
1516 return FAILED;
1517 }
1518
1519 id = cmd->device->id;
1520 lun = cmd->device->lun;
1521
1522 if (!fcport) {
1523 return ret;
1524 }
1525
1526 ret = fc_block_scsi_eh(cmd);
1527 if (ret != 0)
1528 return ret;
1529 ret = FAILED;
1530
1531 ql_log(ql_log_info, vha, 0x8012,
1532 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1533
1534 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1535 ql_log(ql_log_fatal, vha, 0x8013,
1536 "Wait for hba online failed board disabled.\n");
1537 goto eh_bus_reset_done;
1538 }
1539
1540 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1541 ret = SUCCESS;
1542
1543 if (ret == FAILED)
1544 goto eh_bus_reset_done;
1545
1546 /* Flush outstanding commands. */
1547 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1548 QLA_SUCCESS) {
1549 ql_log(ql_log_warn, vha, 0x8014,
1550 "Wait for pending commands failed.\n");
1551 ret = FAILED;
1552 }
1553
1554 eh_bus_reset_done:
1555 ql_log(ql_log_warn, vha, 0x802b,
1556 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1557 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1558
1559 return ret;
1560 }
1561
1562 /**************************************************************************
1563 * qla2xxx_eh_host_reset
1564 *
1565 * Description:
1566 * The reset function will reset the Adapter.
1567 *
1568 * Input:
1569 * cmd = Linux SCSI command packet of the command that cause the
1570 * adapter reset.
1571 *
1572 * Returns:
1573 * Either SUCCESS or FAILED.
1574 *
1575 * Note:
1576 **************************************************************************/
1577 static int
1578 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1579 {
1580 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1581 struct qla_hw_data *ha = vha->hw;
1582 int ret = FAILED;
1583 unsigned int id;
1584 uint64_t lun;
1585 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1586
1587 if (qla2x00_isp_reg_stat(ha)) {
1588 ql_log(ql_log_info, vha, 0x8041,
1589 "PCI/Register disconnect, exiting.\n");
1590 schedule_work(&ha->board_disable);
1591 return SUCCESS;
1592 }
1593
1594 id = cmd->device->id;
1595 lun = cmd->device->lun;
1596
1597 ql_log(ql_log_info, vha, 0x8018,
1598 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1599
1600 /*
1601 * No point in issuing another reset if one is active. Also do not
1602 * attempt a reset if we are updating flash.
1603 */
1604 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1605 goto eh_host_reset_lock;
1606
1607 if (vha != base_vha) {
1608 if (qla2x00_vp_abort_isp(vha))
1609 goto eh_host_reset_lock;
1610 } else {
1611 if (IS_P3P_TYPE(vha->hw)) {
1612 if (!qla82xx_fcoe_ctx_reset(vha)) {
1613 /* Ctx reset success */
1614 ret = SUCCESS;
1615 goto eh_host_reset_lock;
1616 }
1617 /* fall thru if ctx reset failed */
1618 }
1619 if (ha->wq)
1620 flush_workqueue(ha->wq);
1621
1622 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1623 if (ha->isp_ops->abort_isp(base_vha)) {
1624 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1625 /* failed. schedule dpc to try */
1626 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1627
1628 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1629 ql_log(ql_log_warn, vha, 0x802a,
1630 "wait for hba online failed.\n");
1631 goto eh_host_reset_lock;
1632 }
1633 }
1634 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1635 }
1636
1637 /* Waiting for command to be returned to OS.*/
1638 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1639 QLA_SUCCESS)
1640 ret = SUCCESS;
1641
1642 eh_host_reset_lock:
1643 ql_log(ql_log_info, vha, 0x8017,
1644 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1645 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1646
1647 return ret;
1648 }
1649
1650 /*
1651 * qla2x00_loop_reset
1652 * Issue loop reset.
1653 *
1654 * Input:
1655 * ha = adapter block pointer.
1656 *
1657 * Returns:
1658 * 0 = success
1659 */
1660 int
1661 qla2x00_loop_reset(scsi_qla_host_t *vha)
1662 {
1663 int ret;
1664 struct fc_port *fcport;
1665 struct qla_hw_data *ha = vha->hw;
1666
1667 if (IS_QLAFX00(ha)) {
1668 return qlafx00_loop_reset(vha);
1669 }
1670
1671 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1672 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1673 if (fcport->port_type != FCT_TARGET)
1674 continue;
1675
1676 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1677 if (ret != QLA_SUCCESS) {
1678 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1679 "Bus Reset failed: Reset=%d "
1680 "d_id=%x.\n", ret, fcport->d_id.b24);
1681 }
1682 }
1683 }
1684
1685
1686 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1687 atomic_set(&vha->loop_state, LOOP_DOWN);
1688 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1689 qla2x00_mark_all_devices_lost(vha, 0);
1690 ret = qla2x00_full_login_lip(vha);
1691 if (ret != QLA_SUCCESS) {
1692 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1693 "full_login_lip=%d.\n", ret);
1694 }
1695 }
1696
1697 if (ha->flags.enable_lip_reset) {
1698 ret = qla2x00_lip_reset(vha);
1699 if (ret != QLA_SUCCESS)
1700 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1701 "lip_reset failed (%d).\n", ret);
1702 }
1703
1704 /* Issue marker command only when we are going to start the I/O */
1705 vha->marker_needed = 1;
1706
1707 return QLA_SUCCESS;
1708 }
1709
1710 void
1711 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1712 {
1713 int que, cnt, status;
1714 unsigned long flags;
1715 srb_t *sp;
1716 struct qla_hw_data *ha = vha->hw;
1717 struct req_que *req;
1718 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1719 struct qla_tgt_cmd *cmd;
1720 uint8_t trace = 0;
1721
1722 spin_lock_irqsave(&ha->hardware_lock, flags);
1723 for (que = 0; que < ha->max_req_queues; que++) {
1724 req = ha->req_q_map[que];
1725 if (!req)
1726 continue;
1727 if (!req->outstanding_cmds)
1728 continue;
1729 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1730 sp = req->outstanding_cmds[cnt];
1731 if (sp) {
1732 req->outstanding_cmds[cnt] = NULL;
1733 if (sp->cmd_type == TYPE_SRB) {
1734 if (sp->type == SRB_NVME_CMD ||
1735 sp->type == SRB_NVME_LS) {
1736 sp_get(sp);
1737 spin_unlock_irqrestore(
1738 &ha->hardware_lock, flags);
1739 qla_nvme_abort(ha, sp);
1740 spin_lock_irqsave(
1741 &ha->hardware_lock, flags);
1742 } else if (GET_CMD_SP(sp) &&
1743 !ha->flags.eeh_busy &&
1744 (!test_bit(ABORT_ISP_ACTIVE,
1745 &vha->dpc_flags)) &&
1746 (sp->type == SRB_SCSI_CMD)) {
1747 /*
1748 * Don't abort commands in
1749 * adapter during EEH
1750 * recovery as it's not
1751 * accessible/responding.
1752 *
1753 * Get a reference to the sp
1754 * and drop the lock. The
1755 * reference ensures this
1756 * sp->done() call and not the
1757 * call in qla2xxx_eh_abort()
1758 * ends the SCSI command (with
1759 * result 'res').
1760 */
1761 sp_get(sp);
1762 spin_unlock_irqrestore(
1763 &ha->hardware_lock, flags);
1764 status = qla2xxx_eh_abort(
1765 GET_CMD_SP(sp));
1766 spin_lock_irqsave(
1767 &ha->hardware_lock, flags);
1768 /*
1769 * Get rid of extra reference
1770 * if immediate exit from
1771 * ql2xxx_eh_abort
1772 */
1773 if (status == FAILED &&
1774 (qla2x00_isp_reg_stat(ha)))
1775 atomic_dec(
1776 &sp->ref_count);
1777 }
1778 sp->done(sp, res);
1779 } else {
1780 if (!vha->hw->tgt.tgt_ops || !tgt ||
1781 qla_ini_mode_enabled(vha)) {
1782 if (!trace)
1783 ql_dbg(ql_dbg_tgt_mgt,
1784 vha, 0xf003,
1785 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1786 vha->dpc_flags);
1787 continue;
1788 }
1789 cmd = (struct qla_tgt_cmd *)sp;
1790 qlt_abort_cmd_on_host_reset(cmd->vha,
1791 cmd);
1792 }
1793 }
1794 }
1795 }
1796 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1797 }
1798
1799 static int
1800 qla2xxx_slave_alloc(struct scsi_device *sdev)
1801 {
1802 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1803
1804 if (!rport || fc_remote_port_chkready(rport))
1805 return -ENXIO;
1806
1807 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1808
1809 return 0;
1810 }
1811
1812 static int
1813 qla2xxx_slave_configure(struct scsi_device *sdev)
1814 {
1815 scsi_qla_host_t *vha = shost_priv(sdev->host);
1816 struct req_que *req = vha->req;
1817
1818 if (IS_T10_PI_CAPABLE(vha->hw))
1819 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1820
1821 scsi_change_queue_depth(sdev, req->max_q_depth);
1822 return 0;
1823 }
1824
1825 static void
1826 qla2xxx_slave_destroy(struct scsi_device *sdev)
1827 {
1828 sdev->hostdata = NULL;
1829 }
1830
1831 /**
1832 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1833 * @ha: HA context
1834 *
1835 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1836 * supported addressing method.
1837 */
1838 static void
1839 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1840 {
1841 /* Assume a 32bit DMA mask. */
1842 ha->flags.enable_64bit_addressing = 0;
1843
1844 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1845 /* Any upper-dword bits set? */
1846 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1847 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1848 /* Ok, a 64bit DMA mask is applicable. */
1849 ha->flags.enable_64bit_addressing = 1;
1850 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1851 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1852 return;
1853 }
1854 }
1855
1856 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1857 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1858 }
1859
1860 static void
1861 qla2x00_enable_intrs(struct qla_hw_data *ha)
1862 {
1863 unsigned long flags = 0;
1864 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1865
1866 spin_lock_irqsave(&ha->hardware_lock, flags);
1867 ha->interrupts_on = 1;
1868 /* enable risc and host interrupts */
1869 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1870 RD_REG_WORD(&reg->ictrl);
1871 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1872
1873 }
1874
1875 static void
1876 qla2x00_disable_intrs(struct qla_hw_data *ha)
1877 {
1878 unsigned long flags = 0;
1879 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1880
1881 spin_lock_irqsave(&ha->hardware_lock, flags);
1882 ha->interrupts_on = 0;
1883 /* disable risc and host interrupts */
1884 WRT_REG_WORD(&reg->ictrl, 0);
1885 RD_REG_WORD(&reg->ictrl);
1886 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1887 }
1888
1889 static void
1890 qla24xx_enable_intrs(struct qla_hw_data *ha)
1891 {
1892 unsigned long flags = 0;
1893 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1894
1895 spin_lock_irqsave(&ha->hardware_lock, flags);
1896 ha->interrupts_on = 1;
1897 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1898 RD_REG_DWORD(&reg->ictrl);
1899 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1900 }
1901
1902 static void
1903 qla24xx_disable_intrs(struct qla_hw_data *ha)
1904 {
1905 unsigned long flags = 0;
1906 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1907
1908 if (IS_NOPOLLING_TYPE(ha))
1909 return;
1910 spin_lock_irqsave(&ha->hardware_lock, flags);
1911 ha->interrupts_on = 0;
1912 WRT_REG_DWORD(&reg->ictrl, 0);
1913 RD_REG_DWORD(&reg->ictrl);
1914 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1915 }
1916
1917 static int
1918 qla2x00_iospace_config(struct qla_hw_data *ha)
1919 {
1920 resource_size_t pio;
1921 uint16_t msix;
1922
1923 if (pci_request_selected_regions(ha->pdev, ha->bars,
1924 QLA2XXX_DRIVER_NAME)) {
1925 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1926 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1927 pci_name(ha->pdev));
1928 goto iospace_error_exit;
1929 }
1930 if (!(ha->bars & 1))
1931 goto skip_pio;
1932
1933 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1934 pio = pci_resource_start(ha->pdev, 0);
1935 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1936 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1937 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1938 "Invalid pci I/O region size (%s).\n",
1939 pci_name(ha->pdev));
1940 pio = 0;
1941 }
1942 } else {
1943 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1944 "Region #0 no a PIO resource (%s).\n",
1945 pci_name(ha->pdev));
1946 pio = 0;
1947 }
1948 ha->pio_address = pio;
1949 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1950 "PIO address=%llu.\n",
1951 (unsigned long long)ha->pio_address);
1952
1953 skip_pio:
1954 /* Use MMIO operations for all accesses. */
1955 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1956 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1957 "Region #1 not an MMIO resource (%s), aborting.\n",
1958 pci_name(ha->pdev));
1959 goto iospace_error_exit;
1960 }
1961 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1962 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1963 "Invalid PCI mem region size (%s), aborting.\n",
1964 pci_name(ha->pdev));
1965 goto iospace_error_exit;
1966 }
1967
1968 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1969 if (!ha->iobase) {
1970 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1971 "Cannot remap MMIO (%s), aborting.\n",
1972 pci_name(ha->pdev));
1973 goto iospace_error_exit;
1974 }
1975
1976 /* Determine queue resources */
1977 ha->max_req_queues = ha->max_rsp_queues = 1;
1978 ha->msix_count = QLA_BASE_VECTORS;
1979 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1980 goto mqiobase_exit;
1981
1982 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1983 pci_resource_len(ha->pdev, 3));
1984 if (ha->mqiobase) {
1985 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1986 "MQIO Base=%p.\n", ha->mqiobase);
1987 /* Read MSIX vector size of the board */
1988 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1989 ha->msix_count = msix + 1;
1990 /* Max queues are bounded by available msix vectors */
1991 /* MB interrupt uses 1 vector */
1992 ha->max_req_queues = ha->msix_count - 1;
1993 ha->max_rsp_queues = ha->max_req_queues;
1994 /* Queue pairs is the max value minus the base queue pair */
1995 ha->max_qpairs = ha->max_rsp_queues - 1;
1996 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1997 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1998
1999 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2000 "MSI-X vector count: %d.\n", ha->msix_count);
2001 } else
2002 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2003 "BAR 3 not enabled.\n");
2004
2005 mqiobase_exit:
2006 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2007 "MSIX Count: %d.\n", ha->msix_count);
2008 return (0);
2009
2010 iospace_error_exit:
2011 return (-ENOMEM);
2012 }
2013
2014
2015 static int
2016 qla83xx_iospace_config(struct qla_hw_data *ha)
2017 {
2018 uint16_t msix;
2019
2020 if (pci_request_selected_regions(ha->pdev, ha->bars,
2021 QLA2XXX_DRIVER_NAME)) {
2022 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2023 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2024 pci_name(ha->pdev));
2025
2026 goto iospace_error_exit;
2027 }
2028
2029 /* Use MMIO operations for all accesses. */
2030 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2031 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2032 "Invalid pci I/O region size (%s).\n",
2033 pci_name(ha->pdev));
2034 goto iospace_error_exit;
2035 }
2036 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2037 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2038 "Invalid PCI mem region size (%s), aborting\n",
2039 pci_name(ha->pdev));
2040 goto iospace_error_exit;
2041 }
2042
2043 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2044 if (!ha->iobase) {
2045 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2046 "Cannot remap MMIO (%s), aborting.\n",
2047 pci_name(ha->pdev));
2048 goto iospace_error_exit;
2049 }
2050
2051 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2052 /* 83XX 26XX always use MQ type access for queues
2053 * - mbar 2, a.k.a region 4 */
2054 ha->max_req_queues = ha->max_rsp_queues = 1;
2055 ha->msix_count = QLA_BASE_VECTORS;
2056 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2057 pci_resource_len(ha->pdev, 4));
2058
2059 if (!ha->mqiobase) {
2060 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2061 "BAR2/region4 not enabled\n");
2062 goto mqiobase_exit;
2063 }
2064
2065 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2066 pci_resource_len(ha->pdev, 2));
2067 if (ha->msixbase) {
2068 /* Read MSIX vector size of the board */
2069 pci_read_config_word(ha->pdev,
2070 QLA_83XX_PCI_MSIX_CONTROL, &msix);
2071 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2072 /*
2073 * By default, driver uses at least two msix vectors
2074 * (default & rspq)
2075 */
2076 if (ql2xmqsupport) {
2077 /* MB interrupt uses 1 vector */
2078 ha->max_req_queues = ha->msix_count - 1;
2079
2080 /* ATIOQ needs 1 vector. That's 1 less QPair */
2081 if (QLA_TGT_MODE_ENABLED())
2082 ha->max_req_queues--;
2083
2084 ha->max_rsp_queues = ha->max_req_queues;
2085
2086 /* Queue pairs is the max value minus
2087 * the base queue pair */
2088 ha->max_qpairs = ha->max_req_queues - 1;
2089 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2090 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2091 }
2092 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2093 "MSI-X vector count: %d.\n", ha->msix_count);
2094 } else
2095 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2096 "BAR 1 not enabled.\n");
2097
2098 mqiobase_exit:
2099 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2100 "MSIX Count: %d.\n", ha->msix_count);
2101 return 0;
2102
2103 iospace_error_exit:
2104 return -ENOMEM;
2105 }
2106
2107 static struct isp_operations qla2100_isp_ops = {
2108 .pci_config = qla2100_pci_config,
2109 .reset_chip = qla2x00_reset_chip,
2110 .chip_diag = qla2x00_chip_diag,
2111 .config_rings = qla2x00_config_rings,
2112 .reset_adapter = qla2x00_reset_adapter,
2113 .nvram_config = qla2x00_nvram_config,
2114 .update_fw_options = qla2x00_update_fw_options,
2115 .load_risc = qla2x00_load_risc,
2116 .pci_info_str = qla2x00_pci_info_str,
2117 .fw_version_str = qla2x00_fw_version_str,
2118 .intr_handler = qla2100_intr_handler,
2119 .enable_intrs = qla2x00_enable_intrs,
2120 .disable_intrs = qla2x00_disable_intrs,
2121 .abort_command = qla2x00_abort_command,
2122 .target_reset = qla2x00_abort_target,
2123 .lun_reset = qla2x00_lun_reset,
2124 .fabric_login = qla2x00_login_fabric,
2125 .fabric_logout = qla2x00_fabric_logout,
2126 .calc_req_entries = qla2x00_calc_iocbs_32,
2127 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2128 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2129 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2130 .read_nvram = qla2x00_read_nvram_data,
2131 .write_nvram = qla2x00_write_nvram_data,
2132 .fw_dump = qla2100_fw_dump,
2133 .beacon_on = NULL,
2134 .beacon_off = NULL,
2135 .beacon_blink = NULL,
2136 .read_optrom = qla2x00_read_optrom_data,
2137 .write_optrom = qla2x00_write_optrom_data,
2138 .get_flash_version = qla2x00_get_flash_version,
2139 .start_scsi = qla2x00_start_scsi,
2140 .start_scsi_mq = NULL,
2141 .abort_isp = qla2x00_abort_isp,
2142 .iospace_config = qla2x00_iospace_config,
2143 .initialize_adapter = qla2x00_initialize_adapter,
2144 };
2145
2146 static struct isp_operations qla2300_isp_ops = {
2147 .pci_config = qla2300_pci_config,
2148 .reset_chip = qla2x00_reset_chip,
2149 .chip_diag = qla2x00_chip_diag,
2150 .config_rings = qla2x00_config_rings,
2151 .reset_adapter = qla2x00_reset_adapter,
2152 .nvram_config = qla2x00_nvram_config,
2153 .update_fw_options = qla2x00_update_fw_options,
2154 .load_risc = qla2x00_load_risc,
2155 .pci_info_str = qla2x00_pci_info_str,
2156 .fw_version_str = qla2x00_fw_version_str,
2157 .intr_handler = qla2300_intr_handler,
2158 .enable_intrs = qla2x00_enable_intrs,
2159 .disable_intrs = qla2x00_disable_intrs,
2160 .abort_command = qla2x00_abort_command,
2161 .target_reset = qla2x00_abort_target,
2162 .lun_reset = qla2x00_lun_reset,
2163 .fabric_login = qla2x00_login_fabric,
2164 .fabric_logout = qla2x00_fabric_logout,
2165 .calc_req_entries = qla2x00_calc_iocbs_32,
2166 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2167 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2168 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2169 .read_nvram = qla2x00_read_nvram_data,
2170 .write_nvram = qla2x00_write_nvram_data,
2171 .fw_dump = qla2300_fw_dump,
2172 .beacon_on = qla2x00_beacon_on,
2173 .beacon_off = qla2x00_beacon_off,
2174 .beacon_blink = qla2x00_beacon_blink,
2175 .read_optrom = qla2x00_read_optrom_data,
2176 .write_optrom = qla2x00_write_optrom_data,
2177 .get_flash_version = qla2x00_get_flash_version,
2178 .start_scsi = qla2x00_start_scsi,
2179 .start_scsi_mq = NULL,
2180 .abort_isp = qla2x00_abort_isp,
2181 .iospace_config = qla2x00_iospace_config,
2182 .initialize_adapter = qla2x00_initialize_adapter,
2183 };
2184
2185 static struct isp_operations qla24xx_isp_ops = {
2186 .pci_config = qla24xx_pci_config,
2187 .reset_chip = qla24xx_reset_chip,
2188 .chip_diag = qla24xx_chip_diag,
2189 .config_rings = qla24xx_config_rings,
2190 .reset_adapter = qla24xx_reset_adapter,
2191 .nvram_config = qla24xx_nvram_config,
2192 .update_fw_options = qla24xx_update_fw_options,
2193 .load_risc = qla24xx_load_risc,
2194 .pci_info_str = qla24xx_pci_info_str,
2195 .fw_version_str = qla24xx_fw_version_str,
2196 .intr_handler = qla24xx_intr_handler,
2197 .enable_intrs = qla24xx_enable_intrs,
2198 .disable_intrs = qla24xx_disable_intrs,
2199 .abort_command = qla24xx_abort_command,
2200 .target_reset = qla24xx_abort_target,
2201 .lun_reset = qla24xx_lun_reset,
2202 .fabric_login = qla24xx_login_fabric,
2203 .fabric_logout = qla24xx_fabric_logout,
2204 .calc_req_entries = NULL,
2205 .build_iocbs = NULL,
2206 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2207 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2208 .read_nvram = qla24xx_read_nvram_data,
2209 .write_nvram = qla24xx_write_nvram_data,
2210 .fw_dump = qla24xx_fw_dump,
2211 .beacon_on = qla24xx_beacon_on,
2212 .beacon_off = qla24xx_beacon_off,
2213 .beacon_blink = qla24xx_beacon_blink,
2214 .read_optrom = qla24xx_read_optrom_data,
2215 .write_optrom = qla24xx_write_optrom_data,
2216 .get_flash_version = qla24xx_get_flash_version,
2217 .start_scsi = qla24xx_start_scsi,
2218 .start_scsi_mq = NULL,
2219 .abort_isp = qla2x00_abort_isp,
2220 .iospace_config = qla2x00_iospace_config,
2221 .initialize_adapter = qla2x00_initialize_adapter,
2222 };
2223
2224 static struct isp_operations qla25xx_isp_ops = {
2225 .pci_config = qla25xx_pci_config,
2226 .reset_chip = qla24xx_reset_chip,
2227 .chip_diag = qla24xx_chip_diag,
2228 .config_rings = qla24xx_config_rings,
2229 .reset_adapter = qla24xx_reset_adapter,
2230 .nvram_config = qla24xx_nvram_config,
2231 .update_fw_options = qla24xx_update_fw_options,
2232 .load_risc = qla24xx_load_risc,
2233 .pci_info_str = qla24xx_pci_info_str,
2234 .fw_version_str = qla24xx_fw_version_str,
2235 .intr_handler = qla24xx_intr_handler,
2236 .enable_intrs = qla24xx_enable_intrs,
2237 .disable_intrs = qla24xx_disable_intrs,
2238 .abort_command = qla24xx_abort_command,
2239 .target_reset = qla24xx_abort_target,
2240 .lun_reset = qla24xx_lun_reset,
2241 .fabric_login = qla24xx_login_fabric,
2242 .fabric_logout = qla24xx_fabric_logout,
2243 .calc_req_entries = NULL,
2244 .build_iocbs = NULL,
2245 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2246 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2247 .read_nvram = qla25xx_read_nvram_data,
2248 .write_nvram = qla25xx_write_nvram_data,
2249 .fw_dump = qla25xx_fw_dump,
2250 .beacon_on = qla24xx_beacon_on,
2251 .beacon_off = qla24xx_beacon_off,
2252 .beacon_blink = qla24xx_beacon_blink,
2253 .read_optrom = qla25xx_read_optrom_data,
2254 .write_optrom = qla24xx_write_optrom_data,
2255 .get_flash_version = qla24xx_get_flash_version,
2256 .start_scsi = qla24xx_dif_start_scsi,
2257 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2258 .abort_isp = qla2x00_abort_isp,
2259 .iospace_config = qla2x00_iospace_config,
2260 .initialize_adapter = qla2x00_initialize_adapter,
2261 };
2262
2263 static struct isp_operations qla81xx_isp_ops = {
2264 .pci_config = qla25xx_pci_config,
2265 .reset_chip = qla24xx_reset_chip,
2266 .chip_diag = qla24xx_chip_diag,
2267 .config_rings = qla24xx_config_rings,
2268 .reset_adapter = qla24xx_reset_adapter,
2269 .nvram_config = qla81xx_nvram_config,
2270 .update_fw_options = qla81xx_update_fw_options,
2271 .load_risc = qla81xx_load_risc,
2272 .pci_info_str = qla24xx_pci_info_str,
2273 .fw_version_str = qla24xx_fw_version_str,
2274 .intr_handler = qla24xx_intr_handler,
2275 .enable_intrs = qla24xx_enable_intrs,
2276 .disable_intrs = qla24xx_disable_intrs,
2277 .abort_command = qla24xx_abort_command,
2278 .target_reset = qla24xx_abort_target,
2279 .lun_reset = qla24xx_lun_reset,
2280 .fabric_login = qla24xx_login_fabric,
2281 .fabric_logout = qla24xx_fabric_logout,
2282 .calc_req_entries = NULL,
2283 .build_iocbs = NULL,
2284 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2285 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2286 .read_nvram = NULL,
2287 .write_nvram = NULL,
2288 .fw_dump = qla81xx_fw_dump,
2289 .beacon_on = qla24xx_beacon_on,
2290 .beacon_off = qla24xx_beacon_off,
2291 .beacon_blink = qla83xx_beacon_blink,
2292 .read_optrom = qla25xx_read_optrom_data,
2293 .write_optrom = qla24xx_write_optrom_data,
2294 .get_flash_version = qla24xx_get_flash_version,
2295 .start_scsi = qla24xx_dif_start_scsi,
2296 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2297 .abort_isp = qla2x00_abort_isp,
2298 .iospace_config = qla2x00_iospace_config,
2299 .initialize_adapter = qla2x00_initialize_adapter,
2300 };
2301
2302 static struct isp_operations qla82xx_isp_ops = {
2303 .pci_config = qla82xx_pci_config,
2304 .reset_chip = qla82xx_reset_chip,
2305 .chip_diag = qla24xx_chip_diag,
2306 .config_rings = qla82xx_config_rings,
2307 .reset_adapter = qla24xx_reset_adapter,
2308 .nvram_config = qla81xx_nvram_config,
2309 .update_fw_options = qla24xx_update_fw_options,
2310 .load_risc = qla82xx_load_risc,
2311 .pci_info_str = qla24xx_pci_info_str,
2312 .fw_version_str = qla24xx_fw_version_str,
2313 .intr_handler = qla82xx_intr_handler,
2314 .enable_intrs = qla82xx_enable_intrs,
2315 .disable_intrs = qla82xx_disable_intrs,
2316 .abort_command = qla24xx_abort_command,
2317 .target_reset = qla24xx_abort_target,
2318 .lun_reset = qla24xx_lun_reset,
2319 .fabric_login = qla24xx_login_fabric,
2320 .fabric_logout = qla24xx_fabric_logout,
2321 .calc_req_entries = NULL,
2322 .build_iocbs = NULL,
2323 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2324 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2325 .read_nvram = qla24xx_read_nvram_data,
2326 .write_nvram = qla24xx_write_nvram_data,
2327 .fw_dump = qla82xx_fw_dump,
2328 .beacon_on = qla82xx_beacon_on,
2329 .beacon_off = qla82xx_beacon_off,
2330 .beacon_blink = NULL,
2331 .read_optrom = qla82xx_read_optrom_data,
2332 .write_optrom = qla82xx_write_optrom_data,
2333 .get_flash_version = qla82xx_get_flash_version,
2334 .start_scsi = qla82xx_start_scsi,
2335 .start_scsi_mq = NULL,
2336 .abort_isp = qla82xx_abort_isp,
2337 .iospace_config = qla82xx_iospace_config,
2338 .initialize_adapter = qla2x00_initialize_adapter,
2339 };
2340
2341 static struct isp_operations qla8044_isp_ops = {
2342 .pci_config = qla82xx_pci_config,
2343 .reset_chip = qla82xx_reset_chip,
2344 .chip_diag = qla24xx_chip_diag,
2345 .config_rings = qla82xx_config_rings,
2346 .reset_adapter = qla24xx_reset_adapter,
2347 .nvram_config = qla81xx_nvram_config,
2348 .update_fw_options = qla24xx_update_fw_options,
2349 .load_risc = qla82xx_load_risc,
2350 .pci_info_str = qla24xx_pci_info_str,
2351 .fw_version_str = qla24xx_fw_version_str,
2352 .intr_handler = qla8044_intr_handler,
2353 .enable_intrs = qla82xx_enable_intrs,
2354 .disable_intrs = qla82xx_disable_intrs,
2355 .abort_command = qla24xx_abort_command,
2356 .target_reset = qla24xx_abort_target,
2357 .lun_reset = qla24xx_lun_reset,
2358 .fabric_login = qla24xx_login_fabric,
2359 .fabric_logout = qla24xx_fabric_logout,
2360 .calc_req_entries = NULL,
2361 .build_iocbs = NULL,
2362 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2363 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2364 .read_nvram = NULL,
2365 .write_nvram = NULL,
2366 .fw_dump = qla8044_fw_dump,
2367 .beacon_on = qla82xx_beacon_on,
2368 .beacon_off = qla82xx_beacon_off,
2369 .beacon_blink = NULL,
2370 .read_optrom = qla8044_read_optrom_data,
2371 .write_optrom = qla8044_write_optrom_data,
2372 .get_flash_version = qla82xx_get_flash_version,
2373 .start_scsi = qla82xx_start_scsi,
2374 .start_scsi_mq = NULL,
2375 .abort_isp = qla8044_abort_isp,
2376 .iospace_config = qla82xx_iospace_config,
2377 .initialize_adapter = qla2x00_initialize_adapter,
2378 };
2379
2380 static struct isp_operations qla83xx_isp_ops = {
2381 .pci_config = qla25xx_pci_config,
2382 .reset_chip = qla24xx_reset_chip,
2383 .chip_diag = qla24xx_chip_diag,
2384 .config_rings = qla24xx_config_rings,
2385 .reset_adapter = qla24xx_reset_adapter,
2386 .nvram_config = qla81xx_nvram_config,
2387 .update_fw_options = qla81xx_update_fw_options,
2388 .load_risc = qla81xx_load_risc,
2389 .pci_info_str = qla24xx_pci_info_str,
2390 .fw_version_str = qla24xx_fw_version_str,
2391 .intr_handler = qla24xx_intr_handler,
2392 .enable_intrs = qla24xx_enable_intrs,
2393 .disable_intrs = qla24xx_disable_intrs,
2394 .abort_command = qla24xx_abort_command,
2395 .target_reset = qla24xx_abort_target,
2396 .lun_reset = qla24xx_lun_reset,
2397 .fabric_login = qla24xx_login_fabric,
2398 .fabric_logout = qla24xx_fabric_logout,
2399 .calc_req_entries = NULL,
2400 .build_iocbs = NULL,
2401 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2402 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2403 .read_nvram = NULL,
2404 .write_nvram = NULL,
2405 .fw_dump = qla83xx_fw_dump,
2406 .beacon_on = qla24xx_beacon_on,
2407 .beacon_off = qla24xx_beacon_off,
2408 .beacon_blink = qla83xx_beacon_blink,
2409 .read_optrom = qla25xx_read_optrom_data,
2410 .write_optrom = qla24xx_write_optrom_data,
2411 .get_flash_version = qla24xx_get_flash_version,
2412 .start_scsi = qla24xx_dif_start_scsi,
2413 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2414 .abort_isp = qla2x00_abort_isp,
2415 .iospace_config = qla83xx_iospace_config,
2416 .initialize_adapter = qla2x00_initialize_adapter,
2417 };
2418
2419 static struct isp_operations qlafx00_isp_ops = {
2420 .pci_config = qlafx00_pci_config,
2421 .reset_chip = qlafx00_soft_reset,
2422 .chip_diag = qlafx00_chip_diag,
2423 .config_rings = qlafx00_config_rings,
2424 .reset_adapter = qlafx00_soft_reset,
2425 .nvram_config = NULL,
2426 .update_fw_options = NULL,
2427 .load_risc = NULL,
2428 .pci_info_str = qlafx00_pci_info_str,
2429 .fw_version_str = qlafx00_fw_version_str,
2430 .intr_handler = qlafx00_intr_handler,
2431 .enable_intrs = qlafx00_enable_intrs,
2432 .disable_intrs = qlafx00_disable_intrs,
2433 .abort_command = qla24xx_async_abort_command,
2434 .target_reset = qlafx00_abort_target,
2435 .lun_reset = qlafx00_lun_reset,
2436 .fabric_login = NULL,
2437 .fabric_logout = NULL,
2438 .calc_req_entries = NULL,
2439 .build_iocbs = NULL,
2440 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2441 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2442 .read_nvram = qla24xx_read_nvram_data,
2443 .write_nvram = qla24xx_write_nvram_data,
2444 .fw_dump = NULL,
2445 .beacon_on = qla24xx_beacon_on,
2446 .beacon_off = qla24xx_beacon_off,
2447 .beacon_blink = NULL,
2448 .read_optrom = qla24xx_read_optrom_data,
2449 .write_optrom = qla24xx_write_optrom_data,
2450 .get_flash_version = qla24xx_get_flash_version,
2451 .start_scsi = qlafx00_start_scsi,
2452 .start_scsi_mq = NULL,
2453 .abort_isp = qlafx00_abort_isp,
2454 .iospace_config = qlafx00_iospace_config,
2455 .initialize_adapter = qlafx00_initialize_adapter,
2456 };
2457
2458 static struct isp_operations qla27xx_isp_ops = {
2459 .pci_config = qla25xx_pci_config,
2460 .reset_chip = qla24xx_reset_chip,
2461 .chip_diag = qla24xx_chip_diag,
2462 .config_rings = qla24xx_config_rings,
2463 .reset_adapter = qla24xx_reset_adapter,
2464 .nvram_config = qla81xx_nvram_config,
2465 .update_fw_options = qla81xx_update_fw_options,
2466 .load_risc = qla81xx_load_risc,
2467 .pci_info_str = qla24xx_pci_info_str,
2468 .fw_version_str = qla24xx_fw_version_str,
2469 .intr_handler = qla24xx_intr_handler,
2470 .enable_intrs = qla24xx_enable_intrs,
2471 .disable_intrs = qla24xx_disable_intrs,
2472 .abort_command = qla24xx_abort_command,
2473 .target_reset = qla24xx_abort_target,
2474 .lun_reset = qla24xx_lun_reset,
2475 .fabric_login = qla24xx_login_fabric,
2476 .fabric_logout = qla24xx_fabric_logout,
2477 .calc_req_entries = NULL,
2478 .build_iocbs = NULL,
2479 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2480 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2481 .read_nvram = NULL,
2482 .write_nvram = NULL,
2483 .fw_dump = qla27xx_fwdump,
2484 .beacon_on = qla24xx_beacon_on,
2485 .beacon_off = qla24xx_beacon_off,
2486 .beacon_blink = qla83xx_beacon_blink,
2487 .read_optrom = qla25xx_read_optrom_data,
2488 .write_optrom = qla24xx_write_optrom_data,
2489 .get_flash_version = qla24xx_get_flash_version,
2490 .start_scsi = qla24xx_dif_start_scsi,
2491 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2492 .abort_isp = qla2x00_abort_isp,
2493 .iospace_config = qla83xx_iospace_config,
2494 .initialize_adapter = qla2x00_initialize_adapter,
2495 };
2496
2497 static inline void
2498 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2499 {
2500 ha->device_type = DT_EXTENDED_IDS;
2501 switch (ha->pdev->device) {
2502 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2503 ha->isp_type |= DT_ISP2100;
2504 ha->device_type &= ~DT_EXTENDED_IDS;
2505 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2506 break;
2507 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2508 ha->isp_type |= DT_ISP2200;
2509 ha->device_type &= ~DT_EXTENDED_IDS;
2510 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2511 break;
2512 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2513 ha->isp_type |= DT_ISP2300;
2514 ha->device_type |= DT_ZIO_SUPPORTED;
2515 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2516 break;
2517 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2518 ha->isp_type |= DT_ISP2312;
2519 ha->device_type |= DT_ZIO_SUPPORTED;
2520 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2521 break;
2522 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2523 ha->isp_type |= DT_ISP2322;
2524 ha->device_type |= DT_ZIO_SUPPORTED;
2525 if (ha->pdev->subsystem_vendor == 0x1028 &&
2526 ha->pdev->subsystem_device == 0x0170)
2527 ha->device_type |= DT_OEM_001;
2528 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2529 break;
2530 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2531 ha->isp_type |= DT_ISP6312;
2532 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2533 break;
2534 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2535 ha->isp_type |= DT_ISP6322;
2536 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2537 break;
2538 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2539 ha->isp_type |= DT_ISP2422;
2540 ha->device_type |= DT_ZIO_SUPPORTED;
2541 ha->device_type |= DT_FWI2;
2542 ha->device_type |= DT_IIDMA;
2543 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2544 break;
2545 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2546 ha->isp_type |= DT_ISP2432;
2547 ha->device_type |= DT_ZIO_SUPPORTED;
2548 ha->device_type |= DT_FWI2;
2549 ha->device_type |= DT_IIDMA;
2550 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2551 break;
2552 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2553 ha->isp_type |= DT_ISP8432;
2554 ha->device_type |= DT_ZIO_SUPPORTED;
2555 ha->device_type |= DT_FWI2;
2556 ha->device_type |= DT_IIDMA;
2557 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2558 break;
2559 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2560 ha->isp_type |= DT_ISP5422;
2561 ha->device_type |= DT_FWI2;
2562 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2563 break;
2564 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2565 ha->isp_type |= DT_ISP5432;
2566 ha->device_type |= DT_FWI2;
2567 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2568 break;
2569 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2570 ha->isp_type |= DT_ISP2532;
2571 ha->device_type |= DT_ZIO_SUPPORTED;
2572 ha->device_type |= DT_FWI2;
2573 ha->device_type |= DT_IIDMA;
2574 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2575 break;
2576 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2577 ha->isp_type |= DT_ISP8001;
2578 ha->device_type |= DT_ZIO_SUPPORTED;
2579 ha->device_type |= DT_FWI2;
2580 ha->device_type |= DT_IIDMA;
2581 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2582 break;
2583 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2584 ha->isp_type |= DT_ISP8021;
2585 ha->device_type |= DT_ZIO_SUPPORTED;
2586 ha->device_type |= DT_FWI2;
2587 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2588 /* Initialize 82XX ISP flags */
2589 qla82xx_init_flags(ha);
2590 break;
2591 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2592 ha->isp_type |= DT_ISP8044;
2593 ha->device_type |= DT_ZIO_SUPPORTED;
2594 ha->device_type |= DT_FWI2;
2595 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2596 /* Initialize 82XX ISP flags */
2597 qla82xx_init_flags(ha);
2598 break;
2599 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2600 ha->isp_type |= DT_ISP2031;
2601 ha->device_type |= DT_ZIO_SUPPORTED;
2602 ha->device_type |= DT_FWI2;
2603 ha->device_type |= DT_IIDMA;
2604 ha->device_type |= DT_T10_PI;
2605 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2606 break;
2607 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2608 ha->isp_type |= DT_ISP8031;
2609 ha->device_type |= DT_ZIO_SUPPORTED;
2610 ha->device_type |= DT_FWI2;
2611 ha->device_type |= DT_IIDMA;
2612 ha->device_type |= DT_T10_PI;
2613 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2614 break;
2615 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2616 ha->isp_type |= DT_ISPFX00;
2617 break;
2618 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2619 ha->isp_type |= DT_ISP2071;
2620 ha->device_type |= DT_ZIO_SUPPORTED;
2621 ha->device_type |= DT_FWI2;
2622 ha->device_type |= DT_IIDMA;
2623 ha->device_type |= DT_T10_PI;
2624 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2625 break;
2626 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2627 ha->isp_type |= DT_ISP2271;
2628 ha->device_type |= DT_ZIO_SUPPORTED;
2629 ha->device_type |= DT_FWI2;
2630 ha->device_type |= DT_IIDMA;
2631 ha->device_type |= DT_T10_PI;
2632 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2633 break;
2634 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2635 ha->isp_type |= DT_ISP2261;
2636 ha->device_type |= DT_ZIO_SUPPORTED;
2637 ha->device_type |= DT_FWI2;
2638 ha->device_type |= DT_IIDMA;
2639 ha->device_type |= DT_T10_PI;
2640 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2641 break;
2642 }
2643
2644 if (IS_QLA82XX(ha))
2645 ha->port_no = ha->portnum & 1;
2646 else {
2647 /* Get adapter physical port no from interrupt pin register. */
2648 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2649 if (IS_QLA27XX(ha))
2650 ha->port_no--;
2651 else
2652 ha->port_no = !(ha->port_no & 1);
2653 }
2654
2655 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2656 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2657 ha->device_type, ha->port_no, ha->fw_srisc_address);
2658 }
2659
2660 static void
2661 qla2xxx_scan_start(struct Scsi_Host *shost)
2662 {
2663 scsi_qla_host_t *vha = shost_priv(shost);
2664
2665 if (vha->hw->flags.running_gold_fw)
2666 return;
2667
2668 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2669 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2670 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2671 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2672 }
2673
2674 static int
2675 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2676 {
2677 scsi_qla_host_t *vha = shost_priv(shost);
2678
2679 if (test_bit(UNLOADING, &vha->dpc_flags))
2680 return 1;
2681 if (!vha->host)
2682 return 1;
2683 if (time > vha->hw->loop_reset_delay * HZ)
2684 return 1;
2685
2686 return atomic_read(&vha->loop_state) == LOOP_READY;
2687 }
2688
2689 static void qla2x00_iocb_work_fn(struct work_struct *work)
2690 {
2691 struct scsi_qla_host *vha = container_of(work,
2692 struct scsi_qla_host, iocb_work);
2693 int cnt = 0;
2694
2695 while (!list_empty(&vha->work_list)) {
2696 qla2x00_do_work(vha);
2697 cnt++;
2698 if (cnt > 10)
2699 break;
2700 }
2701 }
2702
2703 /*
2704 * PCI driver interface
2705 */
2706 static int
2707 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2708 {
2709 int ret = -ENODEV;
2710 struct Scsi_Host *host;
2711 scsi_qla_host_t *base_vha = NULL;
2712 struct qla_hw_data *ha;
2713 char pci_info[30];
2714 char fw_str[30], wq_name[30];
2715 struct scsi_host_template *sht;
2716 int bars, mem_only = 0;
2717 uint16_t req_length = 0, rsp_length = 0;
2718 struct req_que *req = NULL;
2719 struct rsp_que *rsp = NULL;
2720 int i;
2721
2722 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2723 sht = &qla2xxx_driver_template;
2724 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2725 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2726 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2727 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2728 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2729 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2730 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2731 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2732 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2733 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2734 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2735 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2736 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2737 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2738 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
2739 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2740 mem_only = 1;
2741 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2742 "Mem only adapter.\n");
2743 }
2744 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2745 "Bars=%d.\n", bars);
2746
2747 if (mem_only) {
2748 if (pci_enable_device_mem(pdev))
2749 return ret;
2750 } else {
2751 if (pci_enable_device(pdev))
2752 return ret;
2753 }
2754
2755 /* This may fail but that's ok */
2756 pci_enable_pcie_error_reporting(pdev);
2757
2758 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2759 if (!ha) {
2760 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2761 "Unable to allocate memory for ha.\n");
2762 goto disable_device;
2763 }
2764 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2765 "Memory allocated for ha=%p.\n", ha);
2766 ha->pdev = pdev;
2767 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2768 spin_lock_init(&ha->tgt.q_full_lock);
2769 spin_lock_init(&ha->tgt.sess_lock);
2770 spin_lock_init(&ha->tgt.atio_lock);
2771
2772 atomic_set(&ha->nvme_active_aen_cnt, 0);
2773
2774 /* Clear our data area */
2775 ha->bars = bars;
2776 ha->mem_only = mem_only;
2777 spin_lock_init(&ha->hardware_lock);
2778 spin_lock_init(&ha->vport_slock);
2779 mutex_init(&ha->selflogin_lock);
2780 mutex_init(&ha->optrom_mutex);
2781
2782 /* Set ISP-type information. */
2783 qla2x00_set_isp_flags(ha);
2784
2785 /* Set EEH reset type to fundamental if required by hba */
2786 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2787 IS_QLA83XX(ha) || IS_QLA27XX(ha))
2788 pdev->needs_freset = 1;
2789
2790 ha->prev_topology = 0;
2791 ha->init_cb_size = sizeof(init_cb_t);
2792 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2793 ha->optrom_size = OPTROM_SIZE_2300;
2794
2795 /* Assign ISP specific operations. */
2796 if (IS_QLA2100(ha)) {
2797 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2798 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2799 req_length = REQUEST_ENTRY_CNT_2100;
2800 rsp_length = RESPONSE_ENTRY_CNT_2100;
2801 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2802 ha->gid_list_info_size = 4;
2803 ha->flash_conf_off = ~0;
2804 ha->flash_data_off = ~0;
2805 ha->nvram_conf_off = ~0;
2806 ha->nvram_data_off = ~0;
2807 ha->isp_ops = &qla2100_isp_ops;
2808 } else if (IS_QLA2200(ha)) {
2809 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2810 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2811 req_length = REQUEST_ENTRY_CNT_2200;
2812 rsp_length = RESPONSE_ENTRY_CNT_2100;
2813 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2814 ha->gid_list_info_size = 4;
2815 ha->flash_conf_off = ~0;
2816 ha->flash_data_off = ~0;
2817 ha->nvram_conf_off = ~0;
2818 ha->nvram_data_off = ~0;
2819 ha->isp_ops = &qla2100_isp_ops;
2820 } else if (IS_QLA23XX(ha)) {
2821 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2822 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2823 req_length = REQUEST_ENTRY_CNT_2200;
2824 rsp_length = RESPONSE_ENTRY_CNT_2300;
2825 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2826 ha->gid_list_info_size = 6;
2827 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2828 ha->optrom_size = OPTROM_SIZE_2322;
2829 ha->flash_conf_off = ~0;
2830 ha->flash_data_off = ~0;
2831 ha->nvram_conf_off = ~0;
2832 ha->nvram_data_off = ~0;
2833 ha->isp_ops = &qla2300_isp_ops;
2834 } else if (IS_QLA24XX_TYPE(ha)) {
2835 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2836 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2837 req_length = REQUEST_ENTRY_CNT_24XX;
2838 rsp_length = RESPONSE_ENTRY_CNT_2300;
2839 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2840 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2841 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2842 ha->gid_list_info_size = 8;
2843 ha->optrom_size = OPTROM_SIZE_24XX;
2844 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2845 ha->isp_ops = &qla24xx_isp_ops;
2846 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2847 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2848 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2849 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2850 } else if (IS_QLA25XX(ha)) {
2851 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2852 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2853 req_length = REQUEST_ENTRY_CNT_24XX;
2854 rsp_length = RESPONSE_ENTRY_CNT_2300;
2855 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2856 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2857 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2858 ha->gid_list_info_size = 8;
2859 ha->optrom_size = OPTROM_SIZE_25XX;
2860 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2861 ha->isp_ops = &qla25xx_isp_ops;
2862 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2863 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2864 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2865 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2866 } else if (IS_QLA81XX(ha)) {
2867 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2868 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2869 req_length = REQUEST_ENTRY_CNT_24XX;
2870 rsp_length = RESPONSE_ENTRY_CNT_2300;
2871 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2872 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2873 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2874 ha->gid_list_info_size = 8;
2875 ha->optrom_size = OPTROM_SIZE_81XX;
2876 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2877 ha->isp_ops = &qla81xx_isp_ops;
2878 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2879 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2880 ha->nvram_conf_off = ~0;
2881 ha->nvram_data_off = ~0;
2882 } else if (IS_QLA82XX(ha)) {
2883 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2884 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2885 req_length = REQUEST_ENTRY_CNT_82XX;
2886 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2887 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2888 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2889 ha->gid_list_info_size = 8;
2890 ha->optrom_size = OPTROM_SIZE_82XX;
2891 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2892 ha->isp_ops = &qla82xx_isp_ops;
2893 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2894 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2895 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2896 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2897 } else if (IS_QLA8044(ha)) {
2898 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2899 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2900 req_length = REQUEST_ENTRY_CNT_82XX;
2901 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2902 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2903 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2904 ha->gid_list_info_size = 8;
2905 ha->optrom_size = OPTROM_SIZE_83XX;
2906 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2907 ha->isp_ops = &qla8044_isp_ops;
2908 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2909 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2910 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2911 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2912 } else if (IS_QLA83XX(ha)) {
2913 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2914 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2915 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2916 req_length = REQUEST_ENTRY_CNT_83XX;
2917 rsp_length = RESPONSE_ENTRY_CNT_83XX;
2918 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2919 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2920 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2921 ha->gid_list_info_size = 8;
2922 ha->optrom_size = OPTROM_SIZE_83XX;
2923 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2924 ha->isp_ops = &qla83xx_isp_ops;
2925 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2926 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2927 ha->nvram_conf_off = ~0;
2928 ha->nvram_data_off = ~0;
2929 } else if (IS_QLAFX00(ha)) {
2930 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2931 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2932 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2933 req_length = REQUEST_ENTRY_CNT_FX00;
2934 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2935 ha->isp_ops = &qlafx00_isp_ops;
2936 ha->port_down_retry_count = 30; /* default value */
2937 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2938 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2939 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2940 ha->mr.fw_hbt_en = 1;
2941 ha->mr.host_info_resend = false;
2942 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
2943 } else if (IS_QLA27XX(ha)) {
2944 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2945 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2946 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2947 req_length = REQUEST_ENTRY_CNT_83XX;
2948 rsp_length = RESPONSE_ENTRY_CNT_83XX;
2949 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2950 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2951 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2952 ha->gid_list_info_size = 8;
2953 ha->optrom_size = OPTROM_SIZE_83XX;
2954 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2955 ha->isp_ops = &qla27xx_isp_ops;
2956 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2957 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2958 ha->nvram_conf_off = ~0;
2959 ha->nvram_data_off = ~0;
2960 }
2961
2962 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2963 "mbx_count=%d, req_length=%d, "
2964 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2965 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2966 "max_fibre_devices=%d.\n",
2967 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2968 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2969 ha->nvram_npiv_size, ha->max_fibre_devices);
2970 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2971 "isp_ops=%p, flash_conf_off=%d, "
2972 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2973 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2974 ha->nvram_conf_off, ha->nvram_data_off);
2975
2976 /* Configure PCI I/O space */
2977 ret = ha->isp_ops->iospace_config(ha);
2978 if (ret)
2979 goto iospace_config_failed;
2980
2981 ql_log_pci(ql_log_info, pdev, 0x001d,
2982 "Found an ISP%04X irq %d iobase 0x%p.\n",
2983 pdev->device, pdev->irq, ha->iobase);
2984 mutex_init(&ha->vport_lock);
2985 mutex_init(&ha->mq_lock);
2986 init_completion(&ha->mbx_cmd_comp);
2987 complete(&ha->mbx_cmd_comp);
2988 init_completion(&ha->mbx_intr_comp);
2989 init_completion(&ha->dcbx_comp);
2990 init_completion(&ha->lb_portup_comp);
2991
2992 set_bit(0, (unsigned long *) ha->vp_idx_map);
2993
2994 qla2x00_config_dma_addressing(ha);
2995 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2996 "64 Bit addressing is %s.\n",
2997 ha->flags.enable_64bit_addressing ? "enable" :
2998 "disable");
2999 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3000 if (ret) {
3001 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3002 "Failed to allocate memory for adapter, aborting.\n");
3003
3004 goto probe_hw_failed;
3005 }
3006
3007 req->max_q_depth = MAX_Q_DEPTH;
3008 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3009 req->max_q_depth = ql2xmaxqdepth;
3010
3011
3012 base_vha = qla2x00_create_host(sht, ha);
3013 if (!base_vha) {
3014 ret = -ENOMEM;
3015 qla2x00_mem_free(ha);
3016 qla2x00_free_req_que(ha, req);
3017 qla2x00_free_rsp_que(ha, rsp);
3018 goto probe_hw_failed;
3019 }
3020
3021 pci_set_drvdata(pdev, base_vha);
3022 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3023
3024 host = base_vha->host;
3025 base_vha->req = req;
3026 if (IS_QLA2XXX_MIDTYPE(ha))
3027 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
3028 else
3029 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3030 base_vha->vp_idx;
3031
3032 /* Setup fcport template structure. */
3033 ha->mr.fcport.vha = base_vha;
3034 ha->mr.fcport.port_type = FCT_UNKNOWN;
3035 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3036 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3037 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3038 ha->mr.fcport.scan_state = 1;
3039
3040 /* Set the SG table size based on ISP type */
3041 if (!IS_FWI2_CAPABLE(ha)) {
3042 if (IS_QLA2100(ha))
3043 host->sg_tablesize = 32;
3044 } else {
3045 if (!IS_QLA82XX(ha))
3046 host->sg_tablesize = QLA_SG_ALL;
3047 }
3048 host->max_id = ha->max_fibre_devices;
3049 host->cmd_per_lun = 3;
3050 host->unique_id = host->host_no;
3051 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3052 host->max_cmd_len = 32;
3053 else
3054 host->max_cmd_len = MAX_CMDSZ;
3055 host->max_channel = MAX_BUSES - 1;
3056 /* Older HBAs support only 16-bit LUNs */
3057 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3058 ql2xmaxlun > 0xffff)
3059 host->max_lun = 0xffff;
3060 else
3061 host->max_lun = ql2xmaxlun;
3062 host->transportt = qla2xxx_transport_template;
3063 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3064
3065 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3066 "max_id=%d this_id=%d "
3067 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3068 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3069 host->this_id, host->cmd_per_lun, host->unique_id,
3070 host->max_cmd_len, host->max_channel, host->max_lun,
3071 host->transportt, sht->vendor_id);
3072
3073 /* Set up the irqs */
3074 ret = qla2x00_request_irqs(ha, rsp);
3075 if (ret)
3076 goto probe_init_failed;
3077
3078 /* Alloc arrays of request and response ring ptrs */
3079 if (!qla2x00_alloc_queues(ha, req, rsp)) {
3080 ql_log(ql_log_fatal, base_vha, 0x003d,
3081 "Failed to allocate memory for queue pointers..."
3082 "aborting.\n");
3083 goto probe_init_failed;
3084 }
3085
3086 if (ha->mqenable && shost_use_blk_mq(host)) {
3087 /* number of hardware queues supported by blk/scsi-mq*/
3088 host->nr_hw_queues = ha->max_qpairs;
3089
3090 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3091 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3092 } else
3093 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3094 "blk/scsi-mq disabled.\n");
3095
3096 qlt_probe_one_stage1(base_vha, ha);
3097
3098 pci_save_state(pdev);
3099
3100 /* Assign back pointers */
3101 rsp->req = req;
3102 req->rsp = rsp;
3103
3104 if (IS_QLAFX00(ha)) {
3105 ha->rsp_q_map[0] = rsp;
3106 ha->req_q_map[0] = req;
3107 set_bit(0, ha->req_qid_map);
3108 set_bit(0, ha->rsp_qid_map);
3109 }
3110
3111 /* FWI2-capable only. */
3112 req->req_q_in = &ha->iobase->isp24.req_q_in;
3113 req->req_q_out = &ha->iobase->isp24.req_q_out;
3114 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3115 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3116 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3117 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3118 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3119 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3120 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3121 }
3122
3123 if (IS_QLAFX00(ha)) {
3124 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3125 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3126 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3127 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3128 }
3129
3130 if (IS_P3P_TYPE(ha)) {
3131 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3132 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3133 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3134 }
3135
3136 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3137 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3138 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3139 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3140 "req->req_q_in=%p req->req_q_out=%p "
3141 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3142 req->req_q_in, req->req_q_out,
3143 rsp->rsp_q_in, rsp->rsp_q_out);
3144 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3145 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3146 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3147 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3148 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3149 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3150
3151 if (ha->isp_ops->initialize_adapter(base_vha)) {
3152 ql_log(ql_log_fatal, base_vha, 0x00d6,
3153 "Failed to initialize adapter - Adapter flags %x.\n",
3154 base_vha->device_flags);
3155
3156 if (IS_QLA82XX(ha)) {
3157 qla82xx_idc_lock(ha);
3158 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3159 QLA8XXX_DEV_FAILED);
3160 qla82xx_idc_unlock(ha);
3161 ql_log(ql_log_fatal, base_vha, 0x00d7,
3162 "HW State: FAILED.\n");
3163 } else if (IS_QLA8044(ha)) {
3164 qla8044_idc_lock(ha);
3165 qla8044_wr_direct(base_vha,
3166 QLA8044_CRB_DEV_STATE_INDEX,
3167 QLA8XXX_DEV_FAILED);
3168 qla8044_idc_unlock(ha);
3169 ql_log(ql_log_fatal, base_vha, 0x0150,
3170 "HW State: FAILED.\n");
3171 }
3172
3173 ret = -ENODEV;
3174 goto probe_failed;
3175 }
3176
3177 if (IS_QLAFX00(ha))
3178 host->can_queue = QLAFX00_MAX_CANQUEUE;
3179 else
3180 host->can_queue = req->num_outstanding_cmds - 10;
3181
3182 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3183 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3184 host->can_queue, base_vha->req,
3185 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3186
3187 if (ha->mqenable) {
3188 bool mq = false;
3189 bool startit = false;
3190 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
3191
3192 if (QLA_TGT_MODE_ENABLED()) {
3193 mq = true;
3194 startit = false;
3195 }
3196
3197 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3198 shost_use_blk_mq(host)) {
3199 mq = true;
3200 startit = true;
3201 }
3202
3203 if (mq) {
3204 /* Create start of day qpairs for Block MQ */
3205 for (i = 0; i < ha->max_qpairs; i++)
3206 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3207 }
3208 }
3209
3210 if (ha->flags.running_gold_fw)
3211 goto skip_dpc;
3212
3213 /*
3214 * Startup the kernel thread for this host adapter
3215 */
3216 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3217 "%s_dpc", base_vha->host_str);
3218 if (IS_ERR(ha->dpc_thread)) {
3219 ql_log(ql_log_fatal, base_vha, 0x00ed,
3220 "Failed to start DPC thread.\n");
3221 ret = PTR_ERR(ha->dpc_thread);
3222 goto probe_failed;
3223 }
3224 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3225 "DPC thread started successfully.\n");
3226
3227 /*
3228 * If we're not coming up in initiator mode, we might sit for
3229 * a while without waking up the dpc thread, which leads to a
3230 * stuck process warning. So just kick the dpc once here and
3231 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3232 */
3233 qla2xxx_wake_dpc(base_vha);
3234
3235 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3236 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3237
3238 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3239 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3240 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3241 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3242
3243 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3244 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3245 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3246 INIT_WORK(&ha->idc_state_handler,
3247 qla83xx_idc_state_handler_work);
3248 INIT_WORK(&ha->nic_core_unrecoverable,
3249 qla83xx_nic_core_unrecoverable_work);
3250 }
3251
3252 skip_dpc:
3253 list_add_tail(&base_vha->list, &ha->vp_list);
3254 base_vha->host->irq = ha->pdev->irq;
3255
3256 /* Initialized the timer */
3257 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
3258 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3259 "Started qla2x00_timer with "
3260 "interval=%d.\n", WATCH_INTERVAL);
3261 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3262 "Detected hba at address=%p.\n",
3263 ha);
3264
3265 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3266 if (ha->fw_attributes & BIT_4) {
3267 int prot = 0, guard;
3268 base_vha->flags.difdix_supported = 1;
3269 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3270 "Registering for DIF/DIX type 1 and 3 protection.\n");
3271 if (ql2xenabledif == 1)
3272 prot = SHOST_DIX_TYPE0_PROTECTION;
3273 scsi_host_set_prot(host,
3274 prot | SHOST_DIF_TYPE1_PROTECTION
3275 | SHOST_DIF_TYPE2_PROTECTION
3276 | SHOST_DIF_TYPE3_PROTECTION
3277 | SHOST_DIX_TYPE1_PROTECTION
3278 | SHOST_DIX_TYPE2_PROTECTION
3279 | SHOST_DIX_TYPE3_PROTECTION);
3280
3281 guard = SHOST_DIX_GUARD_CRC;
3282
3283 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3284 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3285 guard |= SHOST_DIX_GUARD_IP;
3286
3287 scsi_host_set_guard(host, guard);
3288 } else
3289 base_vha->flags.difdix_supported = 0;
3290 }
3291
3292 ha->isp_ops->enable_intrs(ha);
3293
3294 if (IS_QLAFX00(ha)) {
3295 ret = qlafx00_fx_disc(base_vha,
3296 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3297 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3298 QLA_SG_ALL : 128;
3299 }
3300
3301 ret = scsi_add_host(host, &pdev->dev);
3302 if (ret)
3303 goto probe_failed;
3304
3305 base_vha->flags.init_done = 1;
3306 base_vha->flags.online = 1;
3307 ha->prev_minidump_failed = 0;
3308
3309 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3310 "Init done and hba is online.\n");
3311
3312 if (qla_ini_mode_enabled(base_vha) ||
3313 qla_dual_mode_enabled(base_vha))
3314 scsi_scan_host(host);
3315 else
3316 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3317 "skipping scsi_scan_host() for non-initiator port\n");
3318
3319 qla2x00_alloc_sysfs_attr(base_vha);
3320
3321 if (IS_QLAFX00(ha)) {
3322 ret = qlafx00_fx_disc(base_vha,
3323 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3324
3325 /* Register system information */
3326 ret = qlafx00_fx_disc(base_vha,
3327 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3328 }
3329
3330 qla2x00_init_host_attr(base_vha);
3331
3332 qla2x00_dfs_setup(base_vha);
3333
3334 ql_log(ql_log_info, base_vha, 0x00fb,
3335 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3336 ql_log(ql_log_info, base_vha, 0x00fc,
3337 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3338 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3339 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3340 base_vha->host_no,
3341 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3342
3343 qlt_add_target(ha, base_vha);
3344
3345 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3346
3347 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3348 return -ENODEV;
3349
3350 if (ha->flags.detected_lr_sfp) {
3351 ql_log(ql_log_info, base_vha, 0xffff,
3352 "Reset chip to pick up LR SFP setting\n");
3353 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3354 qla2xxx_wake_dpc(base_vha);
3355 }
3356
3357 return 0;
3358
3359 probe_init_failed:
3360 qla2x00_free_req_que(ha, req);
3361 ha->req_q_map[0] = NULL;
3362 clear_bit(0, ha->req_qid_map);
3363 qla2x00_free_rsp_que(ha, rsp);
3364 ha->rsp_q_map[0] = NULL;
3365 clear_bit(0, ha->rsp_qid_map);
3366 ha->max_req_queues = ha->max_rsp_queues = 0;
3367
3368 probe_failed:
3369 if (base_vha->timer_active)
3370 qla2x00_stop_timer(base_vha);
3371 base_vha->flags.online = 0;
3372 if (ha->dpc_thread) {
3373 struct task_struct *t = ha->dpc_thread;
3374
3375 ha->dpc_thread = NULL;
3376 kthread_stop(t);
3377 }
3378
3379 qla2x00_free_device(base_vha);
3380
3381 scsi_host_put(base_vha->host);
3382
3383 probe_hw_failed:
3384 qla2x00_clear_drv_active(ha);
3385
3386 iospace_config_failed:
3387 if (IS_P3P_TYPE(ha)) {
3388 if (!ha->nx_pcibase)
3389 iounmap((device_reg_t *)ha->nx_pcibase);
3390 if (!ql2xdbwr)
3391 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3392 } else {
3393 if (ha->iobase)
3394 iounmap(ha->iobase);
3395 if (ha->cregbase)
3396 iounmap(ha->cregbase);
3397 }
3398 pci_release_selected_regions(ha->pdev, ha->bars);
3399 kfree(ha);
3400
3401 disable_device:
3402 pci_disable_device(pdev);
3403 return ret;
3404 }
3405
3406 static void
3407 qla2x00_shutdown(struct pci_dev *pdev)
3408 {
3409 scsi_qla_host_t *vha;
3410 struct qla_hw_data *ha;
3411
3412 vha = pci_get_drvdata(pdev);
3413 ha = vha->hw;
3414
3415 ql_log(ql_log_info, vha, 0xfffa,
3416 "Adapter shutdown\n");
3417
3418 /*
3419 * Prevent future board_disable and wait
3420 * until any pending board_disable has completed.
3421 */
3422 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3423 cancel_work_sync(&ha->board_disable);
3424
3425 if (!atomic_read(&pdev->enable_cnt))
3426 return;
3427
3428 /* Notify ISPFX00 firmware */
3429 if (IS_QLAFX00(ha))
3430 qlafx00_driver_shutdown(vha, 20);
3431
3432 /* Turn-off FCE trace */
3433 if (ha->flags.fce_enabled) {
3434 qla2x00_disable_fce_trace(vha, NULL, NULL);
3435 ha->flags.fce_enabled = 0;
3436 }
3437
3438 /* Turn-off EFT trace */
3439 if (ha->eft)
3440 qla2x00_disable_eft_trace(vha);
3441
3442 /* Stop currently executing firmware. */
3443 qla2x00_try_to_stop_firmware(vha);
3444
3445 /* Turn adapter off line */
3446 vha->flags.online = 0;
3447
3448 /* turn-off interrupts on the card */
3449 if (ha->interrupts_on) {
3450 vha->flags.init_done = 0;
3451 ha->isp_ops->disable_intrs(ha);
3452 }
3453
3454 qla2x00_free_irqs(vha);
3455
3456 qla2x00_free_fw_dump(ha);
3457
3458 pci_disable_device(pdev);
3459 ql_log(ql_log_info, vha, 0xfffe,
3460 "Adapter shutdown successfully.\n");
3461 }
3462
3463 /* Deletes all the virtual ports for a given ha */
3464 static void
3465 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3466 {
3467 scsi_qla_host_t *vha;
3468 unsigned long flags;
3469
3470 mutex_lock(&ha->vport_lock);
3471 while (ha->cur_vport_count) {
3472 spin_lock_irqsave(&ha->vport_slock, flags);
3473
3474 BUG_ON(base_vha->list.next == &ha->vp_list);
3475 /* This assumes first entry in ha->vp_list is always base vha */
3476 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3477 scsi_host_get(vha->host);
3478
3479 spin_unlock_irqrestore(&ha->vport_slock, flags);
3480 mutex_unlock(&ha->vport_lock);
3481
3482 fc_vport_terminate(vha->fc_vport);
3483 scsi_host_put(vha->host);
3484
3485 mutex_lock(&ha->vport_lock);
3486 }
3487 mutex_unlock(&ha->vport_lock);
3488 }
3489
3490 /* Stops all deferred work threads */
3491 static void
3492 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3493 {
3494 /* Cancel all work and destroy DPC workqueues */
3495 if (ha->dpc_lp_wq) {
3496 cancel_work_sync(&ha->idc_aen);
3497 destroy_workqueue(ha->dpc_lp_wq);
3498 ha->dpc_lp_wq = NULL;
3499 }
3500
3501 if (ha->dpc_hp_wq) {
3502 cancel_work_sync(&ha->nic_core_reset);
3503 cancel_work_sync(&ha->idc_state_handler);
3504 cancel_work_sync(&ha->nic_core_unrecoverable);
3505 destroy_workqueue(ha->dpc_hp_wq);
3506 ha->dpc_hp_wq = NULL;
3507 }
3508
3509 /* Kill the kernel thread for this host */
3510 if (ha->dpc_thread) {
3511 struct task_struct *t = ha->dpc_thread;
3512
3513 /*
3514 * qla2xxx_wake_dpc checks for ->dpc_thread
3515 * so we need to zero it out.
3516 */
3517 ha->dpc_thread = NULL;
3518 kthread_stop(t);
3519 }
3520 }
3521
3522 static void
3523 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3524 {
3525 if (IS_QLA82XX(ha)) {
3526
3527 iounmap((device_reg_t *)ha->nx_pcibase);
3528 if (!ql2xdbwr)
3529 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3530 } else {
3531 if (ha->iobase)
3532 iounmap(ha->iobase);
3533
3534 if (ha->cregbase)
3535 iounmap(ha->cregbase);
3536
3537 if (ha->mqiobase)
3538 iounmap(ha->mqiobase);
3539
3540 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
3541 iounmap(ha->msixbase);
3542 }
3543 }
3544
3545 static void
3546 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3547 {
3548 if (IS_QLA8044(ha)) {
3549 qla8044_idc_lock(ha);
3550 qla8044_clear_drv_active(ha);
3551 qla8044_idc_unlock(ha);
3552 } else if (IS_QLA82XX(ha)) {
3553 qla82xx_idc_lock(ha);
3554 qla82xx_clear_drv_active(ha);
3555 qla82xx_idc_unlock(ha);
3556 }
3557 }
3558
3559 static void
3560 qla2x00_remove_one(struct pci_dev *pdev)
3561 {
3562 scsi_qla_host_t *base_vha;
3563 struct qla_hw_data *ha;
3564
3565 base_vha = pci_get_drvdata(pdev);
3566 ha = base_vha->hw;
3567
3568 /* Indicate device removal to prevent future board_disable and wait
3569 * until any pending board_disable has completed. */
3570 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3571 cancel_work_sync(&ha->board_disable);
3572
3573 /*
3574 * If the PCI device is disabled then there was a PCI-disconnect and
3575 * qla2x00_disable_board_on_pci_error has taken care of most of the
3576 * resources.
3577 */
3578 if (!atomic_read(&pdev->enable_cnt)) {
3579 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3580 base_vha->gnl.l, base_vha->gnl.ldma);
3581
3582 scsi_host_put(base_vha->host);
3583 kfree(ha);
3584 pci_set_drvdata(pdev, NULL);
3585 return;
3586 }
3587 qla2x00_wait_for_hba_ready(base_vha);
3588
3589 /*
3590 * if UNLOAD flag is already set, then continue unload,
3591 * where it was set first.
3592 */
3593 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3594 return;
3595
3596 set_bit(UNLOADING, &base_vha->dpc_flags);
3597
3598 qla_nvme_delete(base_vha);
3599
3600 dma_free_coherent(&ha->pdev->dev,
3601 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3602
3603 if (IS_QLAFX00(ha))
3604 qlafx00_driver_shutdown(base_vha, 20);
3605
3606 qla2x00_delete_all_vps(ha, base_vha);
3607
3608 if (IS_QLA8031(ha)) {
3609 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3610 "Clearing fcoe driver presence.\n");
3611 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3612 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3613 "Error while clearing DRV-Presence.\n");
3614 }
3615
3616 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3617
3618 qla2x00_dfs_remove(base_vha);
3619
3620 qla84xx_put_chip(base_vha);
3621
3622 /* Laser should be disabled only for ISP2031 */
3623 if (IS_QLA2031(ha))
3624 qla83xx_disable_laser(base_vha);
3625
3626 /* Disable timer */
3627 if (base_vha->timer_active)
3628 qla2x00_stop_timer(base_vha);
3629
3630 base_vha->flags.online = 0;
3631
3632 /* free DMA memory */
3633 if (ha->exlogin_buf)
3634 qla2x00_free_exlogin_buffer(ha);
3635
3636 /* free DMA memory */
3637 if (ha->exchoffld_buf)
3638 qla2x00_free_exchoffld_buffer(ha);
3639
3640 qla2x00_destroy_deferred_work(ha);
3641
3642 qlt_remove_target(ha, base_vha);
3643
3644 qla2x00_free_sysfs_attr(base_vha, true);
3645
3646 fc_remove_host(base_vha->host);
3647 qlt_remove_target_resources(ha);
3648
3649 scsi_remove_host(base_vha->host);
3650
3651 qla2x00_free_device(base_vha);
3652
3653 qla2x00_clear_drv_active(ha);
3654
3655 scsi_host_put(base_vha->host);
3656
3657 qla2x00_unmap_iobases(ha);
3658
3659 pci_release_selected_regions(ha->pdev, ha->bars);
3660 kfree(ha);
3661
3662 pci_disable_pcie_error_reporting(pdev);
3663
3664 pci_disable_device(pdev);
3665 }
3666
3667 static void
3668 qla2x00_free_device(scsi_qla_host_t *vha)
3669 {
3670 struct qla_hw_data *ha = vha->hw;
3671
3672 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3673
3674 /* Disable timer */
3675 if (vha->timer_active)
3676 qla2x00_stop_timer(vha);
3677
3678 qla25xx_delete_queues(vha);
3679
3680 if (ha->flags.fce_enabled)
3681 qla2x00_disable_fce_trace(vha, NULL, NULL);
3682
3683 if (ha->eft)
3684 qla2x00_disable_eft_trace(vha);
3685
3686 /* Stop currently executing firmware. */
3687 qla2x00_try_to_stop_firmware(vha);
3688
3689 vha->flags.online = 0;
3690
3691 /* turn-off interrupts on the card */
3692 if (ha->interrupts_on) {
3693 vha->flags.init_done = 0;
3694 ha->isp_ops->disable_intrs(ha);
3695 }
3696
3697 qla2x00_free_fcports(vha);
3698
3699 qla2x00_free_irqs(vha);
3700
3701 /* Flush the work queue and remove it */
3702 if (ha->wq) {
3703 flush_workqueue(ha->wq);
3704 destroy_workqueue(ha->wq);
3705 ha->wq = NULL;
3706 }
3707
3708
3709 qla2x00_mem_free(ha);
3710
3711 qla82xx_md_free(vha);
3712
3713 qla2x00_free_queues(ha);
3714 }
3715
3716 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3717 {
3718 fc_port_t *fcport, *tfcport;
3719
3720 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3721 list_del(&fcport->list);
3722 qla2x00_clear_loop_id(fcport);
3723 kfree(fcport);
3724 }
3725 }
3726
3727 static inline void
3728 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3729 int defer)
3730 {
3731 struct fc_rport *rport;
3732 scsi_qla_host_t *base_vha;
3733 unsigned long flags;
3734
3735 if (!fcport->rport)
3736 return;
3737
3738 rport = fcport->rport;
3739 if (defer) {
3740 base_vha = pci_get_drvdata(vha->hw->pdev);
3741 spin_lock_irqsave(vha->host->host_lock, flags);
3742 fcport->drport = rport;
3743 spin_unlock_irqrestore(vha->host->host_lock, flags);
3744 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
3745 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3746 qla2xxx_wake_dpc(base_vha);
3747 } else {
3748 int now;
3749 if (rport) {
3750 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3751 "%s %8phN. rport %p roles %x\n",
3752 __func__, fcport->port_name, rport,
3753 rport->roles);
3754 fc_remote_port_delete(rport);
3755 }
3756 qlt_do_generation_tick(vha, &now);
3757 }
3758 }
3759
3760 /*
3761 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3762 *
3763 * Input: ha = adapter block pointer. fcport = port structure pointer.
3764 *
3765 * Return: None.
3766 *
3767 * Context:
3768 */
3769 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3770 int do_login, int defer)
3771 {
3772 if (IS_QLAFX00(vha->hw)) {
3773 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3774 qla2x00_schedule_rport_del(vha, fcport, defer);
3775 return;
3776 }
3777
3778 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3779 vha->vp_idx == fcport->vha->vp_idx) {
3780 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3781 qla2x00_schedule_rport_del(vha, fcport, defer);
3782 }
3783 /*
3784 * We may need to retry the login, so don't change the state of the
3785 * port but do the retries.
3786 */
3787 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3788 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3789
3790 if (!do_login)
3791 return;
3792
3793 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3794
3795 if (fcport->login_retry == 0) {
3796 fcport->login_retry = vha->hw->login_retry_count;
3797
3798 ql_dbg(ql_dbg_disc, vha, 0x20a3,
3799 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
3800 fcport->port_name, fcport->loop_id, fcport->login_retry);
3801 }
3802 }
3803
3804 /*
3805 * qla2x00_mark_all_devices_lost
3806 * Updates fcport state when device goes offline.
3807 *
3808 * Input:
3809 * ha = adapter block pointer.
3810 * fcport = port structure pointer.
3811 *
3812 * Return:
3813 * None.
3814 *
3815 * Context:
3816 */
3817 void
3818 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3819 {
3820 fc_port_t *fcport;
3821
3822 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3823 "Mark all dev lost\n");
3824
3825 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3826 fcport->scan_state = 0;
3827 qlt_schedule_sess_for_deletion_lock(fcport);
3828
3829 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3830 continue;
3831
3832 /*
3833 * No point in marking the device as lost, if the device is
3834 * already DEAD.
3835 */
3836 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3837 continue;
3838 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3839 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3840 if (defer)
3841 qla2x00_schedule_rport_del(vha, fcport, defer);
3842 else if (vha->vp_idx == fcport->vha->vp_idx)
3843 qla2x00_schedule_rport_del(vha, fcport, defer);
3844 }
3845 }
3846 }
3847
3848 /*
3849 * qla2x00_mem_alloc
3850 * Allocates adapter memory.
3851 *
3852 * Returns:
3853 * 0 = success.
3854 * !0 = failure.
3855 */
3856 static int
3857 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3858 struct req_que **req, struct rsp_que **rsp)
3859 {
3860 char name[16];
3861
3862 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3863 &ha->init_cb_dma, GFP_KERNEL);
3864 if (!ha->init_cb)
3865 goto fail;
3866
3867 if (qlt_mem_alloc(ha) < 0)
3868 goto fail_free_init_cb;
3869
3870 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3871 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3872 if (!ha->gid_list)
3873 goto fail_free_tgt_mem;
3874
3875 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3876 if (!ha->srb_mempool)
3877 goto fail_free_gid_list;
3878
3879 if (IS_P3P_TYPE(ha)) {
3880 /* Allocate cache for CT6 Ctx. */
3881 if (!ctx_cachep) {
3882 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3883 sizeof(struct ct6_dsd), 0,
3884 SLAB_HWCACHE_ALIGN, NULL);
3885 if (!ctx_cachep)
3886 goto fail_free_srb_mempool;
3887 }
3888 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3889 ctx_cachep);
3890 if (!ha->ctx_mempool)
3891 goto fail_free_srb_mempool;
3892 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3893 "ctx_cachep=%p ctx_mempool=%p.\n",
3894 ctx_cachep, ha->ctx_mempool);
3895 }
3896
3897 /* Get memory for cached NVRAM */
3898 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3899 if (!ha->nvram)
3900 goto fail_free_ctx_mempool;
3901
3902 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3903 ha->pdev->device);
3904 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3905 DMA_POOL_SIZE, 8, 0);
3906 if (!ha->s_dma_pool)
3907 goto fail_free_nvram;
3908
3909 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3910 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3911 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3912
3913 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3914 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3915 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3916 if (!ha->dl_dma_pool) {
3917 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3918 "Failed to allocate memory for dl_dma_pool.\n");
3919 goto fail_s_dma_pool;
3920 }
3921
3922 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3923 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3924 if (!ha->fcp_cmnd_dma_pool) {
3925 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3926 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3927 goto fail_dl_dma_pool;
3928 }
3929 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3930 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3931 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3932 }
3933
3934 /* Allocate memory for SNS commands */
3935 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3936 /* Get consistent memory allocated for SNS commands */
3937 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3938 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3939 if (!ha->sns_cmd)
3940 goto fail_dma_pool;
3941 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3942 "sns_cmd: %p.\n", ha->sns_cmd);
3943 } else {
3944 /* Get consistent memory allocated for MS IOCB */
3945 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3946 &ha->ms_iocb_dma);
3947 if (!ha->ms_iocb)
3948 goto fail_dma_pool;
3949 /* Get consistent memory allocated for CT SNS commands */
3950 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3951 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3952 if (!ha->ct_sns)
3953 goto fail_free_ms_iocb;
3954 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3955 "ms_iocb=%p ct_sns=%p.\n",
3956 ha->ms_iocb, ha->ct_sns);
3957 }
3958
3959 /* Allocate memory for request ring */
3960 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3961 if (!*req) {
3962 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3963 "Failed to allocate memory for req.\n");
3964 goto fail_req;
3965 }
3966 (*req)->length = req_len;
3967 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3968 ((*req)->length + 1) * sizeof(request_t),
3969 &(*req)->dma, GFP_KERNEL);
3970 if (!(*req)->ring) {
3971 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3972 "Failed to allocate memory for req_ring.\n");
3973 goto fail_req_ring;
3974 }
3975 /* Allocate memory for response ring */
3976 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3977 if (!*rsp) {
3978 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3979 "Failed to allocate memory for rsp.\n");
3980 goto fail_rsp;
3981 }
3982 (*rsp)->hw = ha;
3983 (*rsp)->length = rsp_len;
3984 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3985 ((*rsp)->length + 1) * sizeof(response_t),
3986 &(*rsp)->dma, GFP_KERNEL);
3987 if (!(*rsp)->ring) {
3988 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3989 "Failed to allocate memory for rsp_ring.\n");
3990 goto fail_rsp_ring;
3991 }
3992 (*req)->rsp = *rsp;
3993 (*rsp)->req = *req;
3994 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3995 "req=%p req->length=%d req->ring=%p rsp=%p "
3996 "rsp->length=%d rsp->ring=%p.\n",
3997 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3998 (*rsp)->ring);
3999 /* Allocate memory for NVRAM data for vports */
4000 if (ha->nvram_npiv_size) {
4001 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
4002 ha->nvram_npiv_size, GFP_KERNEL);
4003 if (!ha->npiv_info) {
4004 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4005 "Failed to allocate memory for npiv_info.\n");
4006 goto fail_npiv_info;
4007 }
4008 } else
4009 ha->npiv_info = NULL;
4010
4011 /* Get consistent memory allocated for EX-INIT-CB. */
4012 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
4013 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4014 &ha->ex_init_cb_dma);
4015 if (!ha->ex_init_cb)
4016 goto fail_ex_init_cb;
4017 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4018 "ex_init_cb=%p.\n", ha->ex_init_cb);
4019 }
4020
4021 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4022
4023 /* Get consistent memory allocated for Async Port-Database. */
4024 if (!IS_FWI2_CAPABLE(ha)) {
4025 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4026 &ha->async_pd_dma);
4027 if (!ha->async_pd)
4028 goto fail_async_pd;
4029 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4030 "async_pd=%p.\n", ha->async_pd);
4031 }
4032
4033 INIT_LIST_HEAD(&ha->vp_list);
4034
4035 /* Allocate memory for our loop_id bitmap */
4036 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
4037 GFP_KERNEL);
4038 if (!ha->loop_id_map)
4039 goto fail_loop_id_map;
4040 else {
4041 qla2x00_set_reserved_loop_ids(ha);
4042 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4043 "loop_id_map=%p.\n", ha->loop_id_map);
4044 }
4045
4046 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4047 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4048 if (!ha->sfp_data) {
4049 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4050 "Unable to allocate memory for SFP read-data.\n");
4051 goto fail_sfp_data;
4052 }
4053
4054 return 0;
4055
4056 fail_sfp_data:
4057 kfree(ha->loop_id_map);
4058 fail_loop_id_map:
4059 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4060 fail_async_pd:
4061 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4062 fail_ex_init_cb:
4063 kfree(ha->npiv_info);
4064 fail_npiv_info:
4065 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4066 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4067 (*rsp)->ring = NULL;
4068 (*rsp)->dma = 0;
4069 fail_rsp_ring:
4070 kfree(*rsp);
4071 fail_rsp:
4072 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4073 sizeof(request_t), (*req)->ring, (*req)->dma);
4074 (*req)->ring = NULL;
4075 (*req)->dma = 0;
4076 fail_req_ring:
4077 kfree(*req);
4078 fail_req:
4079 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4080 ha->ct_sns, ha->ct_sns_dma);
4081 ha->ct_sns = NULL;
4082 ha->ct_sns_dma = 0;
4083 fail_free_ms_iocb:
4084 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4085 ha->ms_iocb = NULL;
4086 ha->ms_iocb_dma = 0;
4087
4088 if (ha->sns_cmd)
4089 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4090 ha->sns_cmd, ha->sns_cmd_dma);
4091 fail_dma_pool:
4092 if (IS_QLA82XX(ha) || ql2xenabledif) {
4093 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4094 ha->fcp_cmnd_dma_pool = NULL;
4095 }
4096 fail_dl_dma_pool:
4097 if (IS_QLA82XX(ha) || ql2xenabledif) {
4098 dma_pool_destroy(ha->dl_dma_pool);
4099 ha->dl_dma_pool = NULL;
4100 }
4101 fail_s_dma_pool:
4102 dma_pool_destroy(ha->s_dma_pool);
4103 ha->s_dma_pool = NULL;
4104 fail_free_nvram:
4105 kfree(ha->nvram);
4106 ha->nvram = NULL;
4107 fail_free_ctx_mempool:
4108 if (ha->ctx_mempool)
4109 mempool_destroy(ha->ctx_mempool);
4110 ha->ctx_mempool = NULL;
4111 fail_free_srb_mempool:
4112 if (ha->srb_mempool)
4113 mempool_destroy(ha->srb_mempool);
4114 ha->srb_mempool = NULL;
4115 fail_free_gid_list:
4116 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4117 ha->gid_list,
4118 ha->gid_list_dma);
4119 ha->gid_list = NULL;
4120 ha->gid_list_dma = 0;
4121 fail_free_tgt_mem:
4122 qlt_mem_free(ha);
4123 fail_free_init_cb:
4124 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4125 ha->init_cb_dma);
4126 ha->init_cb = NULL;
4127 ha->init_cb_dma = 0;
4128 fail:
4129 ql_log(ql_log_fatal, NULL, 0x0030,
4130 "Memory allocation failure.\n");
4131 return -ENOMEM;
4132 }
4133
4134 int
4135 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4136 {
4137 int rval;
4138 uint16_t size, max_cnt, temp;
4139 struct qla_hw_data *ha = vha->hw;
4140
4141 /* Return if we don't need to alloacate any extended logins */
4142 if (!ql2xexlogins)
4143 return QLA_SUCCESS;
4144
4145 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4146 return QLA_SUCCESS;
4147
4148 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4149 max_cnt = 0;
4150 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4151 if (rval != QLA_SUCCESS) {
4152 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4153 "Failed to get exlogin status.\n");
4154 return rval;
4155 }
4156
4157 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4158 temp *= size;
4159
4160 if (temp != ha->exlogin_size) {
4161 qla2x00_free_exlogin_buffer(ha);
4162 ha->exlogin_size = temp;
4163
4164 ql_log(ql_log_info, vha, 0xd024,
4165 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4166 max_cnt, size, temp);
4167
4168 ql_log(ql_log_info, vha, 0xd025,
4169 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4170
4171 /* Get consistent memory for extended logins */
4172 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4173 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4174 if (!ha->exlogin_buf) {
4175 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4176 "Failed to allocate memory for exlogin_buf_dma.\n");
4177 return -ENOMEM;
4178 }
4179 }
4180
4181 /* Now configure the dma buffer */
4182 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4183 if (rval) {
4184 ql_log(ql_log_fatal, vha, 0xd033,
4185 "Setup extended login buffer ****FAILED****.\n");
4186 qla2x00_free_exlogin_buffer(ha);
4187 }
4188
4189 return rval;
4190 }
4191
4192 /*
4193 * qla2x00_free_exlogin_buffer
4194 *
4195 * Input:
4196 * ha = adapter block pointer
4197 */
4198 void
4199 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4200 {
4201 if (ha->exlogin_buf) {
4202 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4203 ha->exlogin_buf, ha->exlogin_buf_dma);
4204 ha->exlogin_buf = NULL;
4205 ha->exlogin_size = 0;
4206 }
4207 }
4208
4209 static void
4210 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4211 {
4212 u32 temp;
4213 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4214
4215 if (qla_ini_mode_enabled(vha)) {
4216 if (ql2xiniexchg > max_cnt)
4217 ql2xiniexchg = max_cnt;
4218
4219 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4220 *ret_cnt = ql2xiniexchg;
4221 } else if (qla_tgt_mode_enabled(vha)) {
4222 if (ql2xexchoffld > max_cnt)
4223 ql2xexchoffld = max_cnt;
4224
4225 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4226 *ret_cnt = ql2xexchoffld;
4227 } else if (qla_dual_mode_enabled(vha)) {
4228 temp = ql2xiniexchg + ql2xexchoffld;
4229 if (temp > max_cnt) {
4230 ql2xiniexchg -= (temp - max_cnt)/2;
4231 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4232 temp = max_cnt;
4233 }
4234
4235 if (temp > FW_DEF_EXCHANGES_CNT)
4236 *ret_cnt = temp;
4237 }
4238 }
4239
4240 int
4241 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4242 {
4243 int rval;
4244 u16 size, max_cnt;
4245 u32 temp;
4246 struct qla_hw_data *ha = vha->hw;
4247
4248 if (!ha->flags.exchoffld_enabled)
4249 return QLA_SUCCESS;
4250
4251 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4252 return QLA_SUCCESS;
4253
4254 max_cnt = 0;
4255 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4256 if (rval != QLA_SUCCESS) {
4257 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4258 "Failed to get exlogin status.\n");
4259 return rval;
4260 }
4261
4262 qla2x00_number_of_exch(vha, &temp, max_cnt);
4263 temp *= size;
4264
4265 if (temp != ha->exchoffld_size) {
4266 qla2x00_free_exchoffld_buffer(ha);
4267 ha->exchoffld_size = temp;
4268
4269 ql_log(ql_log_info, vha, 0xd016,
4270 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4271 max_cnt, size, temp);
4272
4273 ql_log(ql_log_info, vha, 0xd017,
4274 "Exchange Buffers requested size = 0x%x\n",
4275 ha->exchoffld_size);
4276
4277 /* Get consistent memory for extended logins */
4278 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4279 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4280 if (!ha->exchoffld_buf) {
4281 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4282 "Failed to allocate memory for exchoffld_buf_dma.\n");
4283 return -ENOMEM;
4284 }
4285 }
4286
4287 /* Now configure the dma buffer */
4288 rval = qla_set_exchoffld_mem_cfg(vha);
4289 if (rval) {
4290 ql_log(ql_log_fatal, vha, 0xd02e,
4291 "Setup exchange offload buffer ****FAILED****.\n");
4292 qla2x00_free_exchoffld_buffer(ha);
4293 } else {
4294 /* re-adjust number of target exchange */
4295 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4296
4297 if (qla_ini_mode_enabled(vha))
4298 icb->exchange_count = 0;
4299 else
4300 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
4301 }
4302
4303 return rval;
4304 }
4305
4306 /*
4307 * qla2x00_free_exchoffld_buffer
4308 *
4309 * Input:
4310 * ha = adapter block pointer
4311 */
4312 void
4313 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4314 {
4315 if (ha->exchoffld_buf) {
4316 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4317 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4318 ha->exchoffld_buf = NULL;
4319 ha->exchoffld_size = 0;
4320 }
4321 }
4322
4323 /*
4324 * qla2x00_free_fw_dump
4325 * Frees fw dump stuff.
4326 *
4327 * Input:
4328 * ha = adapter block pointer
4329 */
4330 static void
4331 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4332 {
4333 if (ha->fce)
4334 dma_free_coherent(&ha->pdev->dev,
4335 FCE_SIZE, ha->fce, ha->fce_dma);
4336
4337 if (ha->eft)
4338 dma_free_coherent(&ha->pdev->dev,
4339 EFT_SIZE, ha->eft, ha->eft_dma);
4340
4341 if (ha->fw_dump)
4342 vfree(ha->fw_dump);
4343 if (ha->fw_dump_template)
4344 vfree(ha->fw_dump_template);
4345
4346 ha->fce = NULL;
4347 ha->fce_dma = 0;
4348 ha->eft = NULL;
4349 ha->eft_dma = 0;
4350 ha->fw_dumped = 0;
4351 ha->fw_dump_cap_flags = 0;
4352 ha->fw_dump_reading = 0;
4353 ha->fw_dump = NULL;
4354 ha->fw_dump_len = 0;
4355 ha->fw_dump_template = NULL;
4356 ha->fw_dump_template_len = 0;
4357 }
4358
4359 /*
4360 * qla2x00_mem_free
4361 * Frees all adapter allocated memory.
4362 *
4363 * Input:
4364 * ha = adapter block pointer.
4365 */
4366 static void
4367 qla2x00_mem_free(struct qla_hw_data *ha)
4368 {
4369 qla2x00_free_fw_dump(ha);
4370
4371 if (ha->mctp_dump)
4372 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4373 ha->mctp_dump_dma);
4374
4375 if (ha->srb_mempool)
4376 mempool_destroy(ha->srb_mempool);
4377
4378 if (ha->dcbx_tlv)
4379 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4380 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4381
4382 if (ha->xgmac_data)
4383 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4384 ha->xgmac_data, ha->xgmac_data_dma);
4385
4386 if (ha->sns_cmd)
4387 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4388 ha->sns_cmd, ha->sns_cmd_dma);
4389
4390 if (ha->ct_sns)
4391 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4392 ha->ct_sns, ha->ct_sns_dma);
4393
4394 if (ha->sfp_data)
4395 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4396 ha->sfp_data_dma);
4397
4398 if (ha->ms_iocb)
4399 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4400
4401 if (ha->ex_init_cb)
4402 dma_pool_free(ha->s_dma_pool,
4403 ha->ex_init_cb, ha->ex_init_cb_dma);
4404
4405 if (ha->async_pd)
4406 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4407
4408 if (ha->s_dma_pool)
4409 dma_pool_destroy(ha->s_dma_pool);
4410
4411 if (ha->gid_list)
4412 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4413 ha->gid_list, ha->gid_list_dma);
4414
4415 if (IS_QLA82XX(ha)) {
4416 if (!list_empty(&ha->gbl_dsd_list)) {
4417 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4418
4419 /* clean up allocated prev pool */
4420 list_for_each_entry_safe(dsd_ptr,
4421 tdsd_ptr, &ha->gbl_dsd_list, list) {
4422 dma_pool_free(ha->dl_dma_pool,
4423 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4424 list_del(&dsd_ptr->list);
4425 kfree(dsd_ptr);
4426 }
4427 }
4428 }
4429
4430 if (ha->dl_dma_pool)
4431 dma_pool_destroy(ha->dl_dma_pool);
4432
4433 if (ha->fcp_cmnd_dma_pool)
4434 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4435
4436 if (ha->ctx_mempool)
4437 mempool_destroy(ha->ctx_mempool);
4438
4439 qlt_mem_free(ha);
4440
4441 if (ha->init_cb)
4442 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
4443 ha->init_cb, ha->init_cb_dma);
4444 vfree(ha->optrom_buffer);
4445 kfree(ha->nvram);
4446 kfree(ha->npiv_info);
4447 kfree(ha->swl);
4448 kfree(ha->loop_id_map);
4449
4450 ha->srb_mempool = NULL;
4451 ha->ctx_mempool = NULL;
4452 ha->sns_cmd = NULL;
4453 ha->sns_cmd_dma = 0;
4454 ha->ct_sns = NULL;
4455 ha->ct_sns_dma = 0;
4456 ha->ms_iocb = NULL;
4457 ha->ms_iocb_dma = 0;
4458 ha->init_cb = NULL;
4459 ha->init_cb_dma = 0;
4460 ha->ex_init_cb = NULL;
4461 ha->ex_init_cb_dma = 0;
4462 ha->async_pd = NULL;
4463 ha->async_pd_dma = 0;
4464
4465 ha->s_dma_pool = NULL;
4466 ha->dl_dma_pool = NULL;
4467 ha->fcp_cmnd_dma_pool = NULL;
4468
4469 ha->gid_list = NULL;
4470 ha->gid_list_dma = 0;
4471
4472 ha->tgt.atio_ring = NULL;
4473 ha->tgt.atio_dma = 0;
4474 ha->tgt.tgt_vp_map = NULL;
4475 }
4476
4477 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4478 struct qla_hw_data *ha)
4479 {
4480 struct Scsi_Host *host;
4481 struct scsi_qla_host *vha = NULL;
4482
4483 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4484 if (!host) {
4485 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4486 "Failed to allocate host from the scsi layer, aborting.\n");
4487 return NULL;
4488 }
4489
4490 /* Clear our data area */
4491 vha = shost_priv(host);
4492 memset(vha, 0, sizeof(scsi_qla_host_t));
4493
4494 vha->host = host;
4495 vha->host_no = host->host_no;
4496 vha->hw = ha;
4497
4498 INIT_LIST_HEAD(&vha->vp_fcports);
4499 INIT_LIST_HEAD(&vha->work_list);
4500 INIT_LIST_HEAD(&vha->list);
4501 INIT_LIST_HEAD(&vha->qla_cmd_list);
4502 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
4503 INIT_LIST_HEAD(&vha->logo_list);
4504 INIT_LIST_HEAD(&vha->plogi_ack_list);
4505 INIT_LIST_HEAD(&vha->qp_list);
4506 INIT_LIST_HEAD(&vha->gnl.fcports);
4507 INIT_LIST_HEAD(&vha->nvme_rport_list);
4508
4509 spin_lock_init(&vha->work_lock);
4510 spin_lock_init(&vha->cmd_list_lock);
4511 init_waitqueue_head(&vha->fcport_waitQ);
4512 init_waitqueue_head(&vha->vref_waitq);
4513
4514 vha->gnl.size = sizeof(struct get_name_list_extended) *
4515 (ha->max_loop_id + 1);
4516 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4517 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4518 if (!vha->gnl.l) {
4519 ql_log(ql_log_fatal, vha, 0xd04a,
4520 "Alloc failed for name list.\n");
4521 scsi_remove_host(vha->host);
4522 return NULL;
4523 }
4524
4525 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
4526 ql_dbg(ql_dbg_init, vha, 0x0041,
4527 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4528 vha->host, vha->hw, vha,
4529 dev_name(&(ha->pdev->dev)));
4530
4531 return vha;
4532 }
4533
4534 struct qla_work_evt *
4535 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
4536 {
4537 struct qla_work_evt *e;
4538 uint8_t bail;
4539
4540 QLA_VHA_MARK_BUSY(vha, bail);
4541 if (bail)
4542 return NULL;
4543
4544 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
4545 if (!e) {
4546 QLA_VHA_MARK_NOT_BUSY(vha);
4547 return NULL;
4548 }
4549
4550 INIT_LIST_HEAD(&e->list);
4551 e->type = type;
4552 e->flags = QLA_EVT_FLAG_FREE;
4553 return e;
4554 }
4555
4556 int
4557 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
4558 {
4559 unsigned long flags;
4560
4561 spin_lock_irqsave(&vha->work_lock, flags);
4562 list_add_tail(&e->list, &vha->work_list);
4563 spin_unlock_irqrestore(&vha->work_lock, flags);
4564
4565 if (QLA_EARLY_LINKUP(vha->hw))
4566 schedule_work(&vha->iocb_work);
4567 else
4568 qla2xxx_wake_dpc(vha);
4569
4570 return QLA_SUCCESS;
4571 }
4572
4573 int
4574 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
4575 u32 data)
4576 {
4577 struct qla_work_evt *e;
4578
4579 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
4580 if (!e)
4581 return QLA_FUNCTION_FAILED;
4582
4583 e->u.aen.code = code;
4584 e->u.aen.data = data;
4585 return qla2x00_post_work(vha, e);
4586 }
4587
4588 int
4589 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4590 {
4591 struct qla_work_evt *e;
4592
4593 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
4594 if (!e)
4595 return QLA_FUNCTION_FAILED;
4596
4597 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4598 return qla2x00_post_work(vha, e);
4599 }
4600
4601 #define qla2x00_post_async_work(name, type) \
4602 int qla2x00_post_async_##name##_work( \
4603 struct scsi_qla_host *vha, \
4604 fc_port_t *fcport, uint16_t *data) \
4605 { \
4606 struct qla_work_evt *e; \
4607 \
4608 e = qla2x00_alloc_work(vha, type); \
4609 if (!e) \
4610 return QLA_FUNCTION_FAILED; \
4611 \
4612 e->u.logio.fcport = fcport; \
4613 if (data) { \
4614 e->u.logio.data[0] = data[0]; \
4615 e->u.logio.data[1] = data[1]; \
4616 } \
4617 return qla2x00_post_work(vha, e); \
4618 }
4619
4620 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4621 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4622 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
4623 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4624 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
4625
4626 int
4627 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4628 {
4629 struct qla_work_evt *e;
4630
4631 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4632 if (!e)
4633 return QLA_FUNCTION_FAILED;
4634
4635 e->u.uevent.code = code;
4636 return qla2x00_post_work(vha, e);
4637 }
4638
4639 static void
4640 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4641 {
4642 char event_string[40];
4643 char *envp[] = { event_string, NULL };
4644
4645 switch (code) {
4646 case QLA_UEVENT_CODE_FW_DUMP:
4647 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4648 vha->host_no);
4649 break;
4650 default:
4651 /* do nothing */
4652 break;
4653 }
4654 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4655 }
4656
4657 int
4658 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4659 uint32_t *data, int cnt)
4660 {
4661 struct qla_work_evt *e;
4662
4663 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4664 if (!e)
4665 return QLA_FUNCTION_FAILED;
4666
4667 e->u.aenfx.evtcode = evtcode;
4668 e->u.aenfx.count = cnt;
4669 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4670 return qla2x00_post_work(vha, e);
4671 }
4672
4673 int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4674 {
4675 struct qla_work_evt *e;
4676
4677 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4678 if (!e)
4679 return QLA_FUNCTION_FAILED;
4680
4681 e->u.fcport.fcport = fcport;
4682 return qla2x00_post_work(vha, e);
4683 }
4684
4685 static
4686 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4687 {
4688 unsigned long flags;
4689 fc_port_t *fcport = NULL, *tfcp;
4690 struct qlt_plogi_ack_t *pla =
4691 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4692 uint8_t free_fcport = 0;
4693
4694 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4695 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4696 if (fcport) {
4697 fcport->d_id = e->u.new_sess.id;
4698 if (pla) {
4699 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4700 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4701 /* we took an extra ref_count to prevent PLOGI ACK when
4702 * fcport/sess has not been created.
4703 */
4704 pla->ref_count--;
4705 }
4706 } else {
4707 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4708 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4709 if (fcport) {
4710 fcport->d_id = e->u.new_sess.id;
4711 fcport->scan_state = QLA_FCPORT_FOUND;
4712 fcport->flags |= FCF_FABRIC_DEVICE;
4713 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4714
4715 memcpy(fcport->port_name, e->u.new_sess.port_name,
4716 WWN_SIZE);
4717 } else {
4718 ql_dbg(ql_dbg_disc, vha, 0xffff,
4719 "%s %8phC mem alloc fail.\n",
4720 __func__, e->u.new_sess.port_name);
4721
4722 if (pla)
4723 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4724 return;
4725 }
4726
4727 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4728 /* search again to make sure one else got ahead */
4729 tfcp = qla2x00_find_fcport_by_wwpn(vha,
4730 e->u.new_sess.port_name, 1);
4731 if (tfcp) {
4732 /* should rarily happen */
4733 ql_dbg(ql_dbg_disc, vha, 0xffff,
4734 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
4735 __func__, tfcp->port_name, tfcp->disc_state,
4736 tfcp->fw_login_state);
4737
4738 free_fcport = 1;
4739 } else {
4740 list_add_tail(&fcport->list, &vha->vp_fcports);
4741
4742 if (pla) {
4743 qlt_plogi_ack_link(vha, pla, fcport,
4744 QLT_PLOGI_LINK_SAME_WWN);
4745 pla->ref_count--;
4746 }
4747 }
4748 }
4749 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4750
4751 if (fcport) {
4752 if (pla)
4753 qlt_plogi_ack_unref(vha, pla);
4754 else
4755 qla24xx_async_gnl(vha, fcport);
4756 }
4757
4758 if (free_fcport) {
4759 qla2x00_free_fcport(fcport);
4760 if (pla)
4761 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4762 }
4763 }
4764
4765 void
4766 qla2x00_do_work(struct scsi_qla_host *vha)
4767 {
4768 struct qla_work_evt *e, *tmp;
4769 unsigned long flags;
4770 LIST_HEAD(work);
4771
4772 spin_lock_irqsave(&vha->work_lock, flags);
4773 list_splice_init(&vha->work_list, &work);
4774 spin_unlock_irqrestore(&vha->work_lock, flags);
4775
4776 list_for_each_entry_safe(e, tmp, &work, list) {
4777 list_del_init(&e->list);
4778
4779 switch (e->type) {
4780 case QLA_EVT_AEN:
4781 fc_host_post_event(vha->host, fc_get_event_number(),
4782 e->u.aen.code, e->u.aen.data);
4783 break;
4784 case QLA_EVT_IDC_ACK:
4785 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4786 break;
4787 case QLA_EVT_ASYNC_LOGIN:
4788 qla2x00_async_login(vha, e->u.logio.fcport,
4789 e->u.logio.data);
4790 break;
4791 case QLA_EVT_ASYNC_LOGOUT:
4792 qla2x00_async_logout(vha, e->u.logio.fcport);
4793 break;
4794 case QLA_EVT_ASYNC_LOGOUT_DONE:
4795 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4796 e->u.logio.data);
4797 break;
4798 case QLA_EVT_ASYNC_ADISC:
4799 qla2x00_async_adisc(vha, e->u.logio.fcport,
4800 e->u.logio.data);
4801 break;
4802 case QLA_EVT_ASYNC_ADISC_DONE:
4803 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4804 e->u.logio.data);
4805 break;
4806 case QLA_EVT_UEVENT:
4807 qla2x00_uevent_emit(vha, e->u.uevent.code);
4808 break;
4809 case QLA_EVT_AENFX:
4810 qlafx00_process_aen(vha, e);
4811 break;
4812 case QLA_EVT_GIDPN:
4813 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4814 break;
4815 case QLA_EVT_GPNID:
4816 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4817 break;
4818 case QLA_EVT_GPNID_DONE:
4819 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4820 break;
4821 case QLA_EVT_NEW_SESS:
4822 qla24xx_create_new_sess(vha, e);
4823 break;
4824 case QLA_EVT_GPDB:
4825 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4826 e->u.fcport.opt);
4827 break;
4828 case QLA_EVT_PRLI:
4829 qla24xx_async_prli(vha, e->u.fcport.fcport);
4830 break;
4831 case QLA_EVT_GPSC:
4832 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4833 break;
4834 case QLA_EVT_UPD_FCPORT:
4835 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4836 break;
4837 case QLA_EVT_GNL:
4838 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4839 break;
4840 case QLA_EVT_NACK:
4841 qla24xx_do_nack_work(vha, e);
4842 break;
4843 }
4844 if (e->flags & QLA_EVT_FLAG_FREE)
4845 kfree(e);
4846
4847 /* For each work completed decrement vha ref count */
4848 QLA_VHA_MARK_NOT_BUSY(vha);
4849 }
4850 }
4851
4852 /* Relogins all the fcports of a vport
4853 * Context: dpc thread
4854 */
4855 void qla2x00_relogin(struct scsi_qla_host *vha)
4856 {
4857 fc_port_t *fcport;
4858 int status;
4859 struct event_arg ea;
4860
4861 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4862 /*
4863 * If the port is not ONLINE then try to login
4864 * to it if we haven't run out of retries.
4865 */
4866 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4867 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
4868 fcport->login_retry--;
4869 if (fcport->flags & FCF_FABRIC_DEVICE) {
4870 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108,
4871 "%s %8phC DS %d LS %d\n", __func__,
4872 fcport->port_name, fcport->disc_state,
4873 fcport->fw_login_state);
4874 memset(&ea, 0, sizeof(ea));
4875 ea.event = FCME_RELOGIN;
4876 ea.fcport = fcport;
4877 qla2x00_fcport_event_handler(vha, &ea);
4878 } else {
4879 status = qla2x00_local_device_login(vha,
4880 fcport);
4881 if (status == QLA_SUCCESS) {
4882 fcport->old_loop_id = fcport->loop_id;
4883 ql_dbg(ql_dbg_disc, vha, 0x2003,
4884 "Port login OK: logged in ID 0x%x.\n",
4885 fcport->loop_id);
4886 qla2x00_update_fcport(vha, fcport);
4887 } else if (status == 1) {
4888 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4889 /* retry the login again */
4890 ql_dbg(ql_dbg_disc, vha, 0x2007,
4891 "Retrying %d login again loop_id 0x%x.\n",
4892 fcport->login_retry,
4893 fcport->loop_id);
4894 } else {
4895 fcport->login_retry = 0;
4896 }
4897
4898 if (fcport->login_retry == 0 &&
4899 status != QLA_SUCCESS)
4900 qla2x00_clear_loop_id(fcport);
4901 }
4902 }
4903 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4904 break;
4905 }
4906 }
4907
4908 /* Schedule work on any of the dpc-workqueues */
4909 void
4910 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4911 {
4912 struct qla_hw_data *ha = base_vha->hw;
4913
4914 switch (work_code) {
4915 case MBA_IDC_AEN: /* 0x8200 */
4916 if (ha->dpc_lp_wq)
4917 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4918 break;
4919
4920 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4921 if (!ha->flags.nic_core_reset_hdlr_active) {
4922 if (ha->dpc_hp_wq)
4923 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4924 } else
4925 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4926 "NIC Core reset is already active. Skip "
4927 "scheduling it again.\n");
4928 break;
4929 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4930 if (ha->dpc_hp_wq)
4931 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4932 break;
4933 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4934 if (ha->dpc_hp_wq)
4935 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4936 break;
4937 default:
4938 ql_log(ql_log_warn, base_vha, 0xb05f,
4939 "Unknown work-code=0x%x.\n", work_code);
4940 }
4941
4942 return;
4943 }
4944
4945 /* Work: Perform NIC Core Unrecoverable state handling */
4946 void
4947 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4948 {
4949 struct qla_hw_data *ha =
4950 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4951 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4952 uint32_t dev_state = 0;
4953
4954 qla83xx_idc_lock(base_vha, 0);
4955 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4956 qla83xx_reset_ownership(base_vha);
4957 if (ha->flags.nic_core_reset_owner) {
4958 ha->flags.nic_core_reset_owner = 0;
4959 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4960 QLA8XXX_DEV_FAILED);
4961 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4962 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4963 }
4964 qla83xx_idc_unlock(base_vha, 0);
4965 }
4966
4967 /* Work: Execute IDC state handler */
4968 void
4969 qla83xx_idc_state_handler_work(struct work_struct *work)
4970 {
4971 struct qla_hw_data *ha =
4972 container_of(work, struct qla_hw_data, idc_state_handler);
4973 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4974 uint32_t dev_state = 0;
4975
4976 qla83xx_idc_lock(base_vha, 0);
4977 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4978 if (dev_state == QLA8XXX_DEV_FAILED ||
4979 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4980 qla83xx_idc_state_handler(base_vha);
4981 qla83xx_idc_unlock(base_vha, 0);
4982 }
4983
4984 static int
4985 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4986 {
4987 int rval = QLA_SUCCESS;
4988 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4989 uint32_t heart_beat_counter1, heart_beat_counter2;
4990
4991 do {
4992 if (time_after(jiffies, heart_beat_wait)) {
4993 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4994 "Nic Core f/w is not alive.\n");
4995 rval = QLA_FUNCTION_FAILED;
4996 break;
4997 }
4998
4999 qla83xx_idc_lock(base_vha, 0);
5000 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5001 &heart_beat_counter1);
5002 qla83xx_idc_unlock(base_vha, 0);
5003 msleep(100);
5004 qla83xx_idc_lock(base_vha, 0);
5005 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5006 &heart_beat_counter2);
5007 qla83xx_idc_unlock(base_vha, 0);
5008 } while (heart_beat_counter1 == heart_beat_counter2);
5009
5010 return rval;
5011 }
5012
5013 /* Work: Perform NIC Core Reset handling */
5014 void
5015 qla83xx_nic_core_reset_work(struct work_struct *work)
5016 {
5017 struct qla_hw_data *ha =
5018 container_of(work, struct qla_hw_data, nic_core_reset);
5019 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5020 uint32_t dev_state = 0;
5021
5022 if (IS_QLA2031(ha)) {
5023 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5024 ql_log(ql_log_warn, base_vha, 0xb081,
5025 "Failed to dump mctp\n");
5026 return;
5027 }
5028
5029 if (!ha->flags.nic_core_reset_hdlr_active) {
5030 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5031 qla83xx_idc_lock(base_vha, 0);
5032 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5033 &dev_state);
5034 qla83xx_idc_unlock(base_vha, 0);
5035 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5036 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5037 "Nic Core f/w is alive.\n");
5038 return;
5039 }
5040 }
5041
5042 ha->flags.nic_core_reset_hdlr_active = 1;
5043 if (qla83xx_nic_core_reset(base_vha)) {
5044 /* NIC Core reset failed. */
5045 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5046 "NIC Core reset failed.\n");
5047 }
5048 ha->flags.nic_core_reset_hdlr_active = 0;
5049 }
5050 }
5051
5052 /* Work: Handle 8200 IDC aens */
5053 void
5054 qla83xx_service_idc_aen(struct work_struct *work)
5055 {
5056 struct qla_hw_data *ha =
5057 container_of(work, struct qla_hw_data, idc_aen);
5058 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5059 uint32_t dev_state, idc_control;
5060
5061 qla83xx_idc_lock(base_vha, 0);
5062 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5063 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5064 qla83xx_idc_unlock(base_vha, 0);
5065 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5066 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5067 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5068 "Application requested NIC Core Reset.\n");
5069 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5070 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5071 QLA_SUCCESS) {
5072 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5073 "Other protocol driver requested NIC Core Reset.\n");
5074 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5075 }
5076 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5077 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5078 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5079 }
5080 }
5081
5082 static void
5083 qla83xx_wait_logic(void)
5084 {
5085 int i;
5086
5087 /* Yield CPU */
5088 if (!in_interrupt()) {
5089 /*
5090 * Wait about 200ms before retrying again.
5091 * This controls the number of retries for single
5092 * lock operation.
5093 */
5094 msleep(100);
5095 schedule();
5096 } else {
5097 for (i = 0; i < 20; i++)
5098 cpu_relax(); /* This a nop instr on i386 */
5099 }
5100 }
5101
5102 static int
5103 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5104 {
5105 int rval;
5106 uint32_t data;
5107 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5108 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5109 struct qla_hw_data *ha = base_vha->hw;
5110 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5111 "Trying force recovery of the IDC lock.\n");
5112
5113 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5114 if (rval)
5115 return rval;
5116
5117 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5118 return QLA_SUCCESS;
5119 } else {
5120 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5121 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5122 data);
5123 if (rval)
5124 return rval;
5125
5126 msleep(200);
5127
5128 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5129 &data);
5130 if (rval)
5131 return rval;
5132
5133 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5134 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5135 ~(idc_lck_rcvry_stage_mask));
5136 rval = qla83xx_wr_reg(base_vha,
5137 QLA83XX_IDC_LOCK_RECOVERY, data);
5138 if (rval)
5139 return rval;
5140
5141 /* Forcefully perform IDC UnLock */
5142 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5143 &data);
5144 if (rval)
5145 return rval;
5146 /* Clear lock-id by setting 0xff */
5147 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5148 0xff);
5149 if (rval)
5150 return rval;
5151 /* Clear lock-recovery by setting 0x0 */
5152 rval = qla83xx_wr_reg(base_vha,
5153 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5154 if (rval)
5155 return rval;
5156 } else
5157 return QLA_SUCCESS;
5158 }
5159
5160 return rval;
5161 }
5162
5163 static int
5164 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5165 {
5166 int rval = QLA_SUCCESS;
5167 uint32_t o_drv_lockid, n_drv_lockid;
5168 unsigned long lock_recovery_timeout;
5169
5170 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5171 retry_lockid:
5172 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5173 if (rval)
5174 goto exit;
5175
5176 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5177 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5178 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5179 return QLA_SUCCESS;
5180 else
5181 return QLA_FUNCTION_FAILED;
5182 }
5183
5184 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5185 if (rval)
5186 goto exit;
5187
5188 if (o_drv_lockid == n_drv_lockid) {
5189 qla83xx_wait_logic();
5190 goto retry_lockid;
5191 } else
5192 return QLA_SUCCESS;
5193
5194 exit:
5195 return rval;
5196 }
5197
5198 void
5199 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5200 {
5201 uint16_t options = (requester_id << 15) | BIT_6;
5202 uint32_t data;
5203 uint32_t lock_owner;
5204 struct qla_hw_data *ha = base_vha->hw;
5205
5206 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5207 retry_lock:
5208 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5209 == QLA_SUCCESS) {
5210 if (data) {
5211 /* Setting lock-id to our function-number */
5212 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5213 ha->portnum);
5214 } else {
5215 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5216 &lock_owner);
5217 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5218 "Failed to acquire IDC lock, acquired by %d, "
5219 "retrying...\n", lock_owner);
5220
5221 /* Retry/Perform IDC-Lock recovery */
5222 if (qla83xx_idc_lock_recovery(base_vha)
5223 == QLA_SUCCESS) {
5224 qla83xx_wait_logic();
5225 goto retry_lock;
5226 } else
5227 ql_log(ql_log_warn, base_vha, 0xb075,
5228 "IDC Lock recovery FAILED.\n");
5229 }
5230
5231 }
5232
5233 return;
5234
5235 /* XXX: IDC-lock implementation using access-control mbx */
5236 retry_lock2:
5237 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5238 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5239 "Failed to acquire IDC lock. retrying...\n");
5240 /* Retry/Perform IDC-Lock recovery */
5241 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5242 qla83xx_wait_logic();
5243 goto retry_lock2;
5244 } else
5245 ql_log(ql_log_warn, base_vha, 0xb076,
5246 "IDC Lock recovery FAILED.\n");
5247 }
5248
5249 return;
5250 }
5251
5252 void
5253 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5254 {
5255 #if 0
5256 uint16_t options = (requester_id << 15) | BIT_7;
5257 #endif
5258 uint16_t retry;
5259 uint32_t data;
5260 struct qla_hw_data *ha = base_vha->hw;
5261
5262 /* IDC-unlock implementation using driver-unlock/lock-id
5263 * remote registers
5264 */
5265 retry = 0;
5266 retry_unlock:
5267 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5268 == QLA_SUCCESS) {
5269 if (data == ha->portnum) {
5270 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5271 /* Clearing lock-id by setting 0xff */
5272 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5273 } else if (retry < 10) {
5274 /* SV: XXX: IDC unlock retrying needed here? */
5275
5276 /* Retry for IDC-unlock */
5277 qla83xx_wait_logic();
5278 retry++;
5279 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
5280 "Failed to release IDC lock, retrying=%d\n", retry);
5281 goto retry_unlock;
5282 }
5283 } else if (retry < 10) {
5284 /* Retry for IDC-unlock */
5285 qla83xx_wait_logic();
5286 retry++;
5287 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
5288 "Failed to read drv-lockid, retrying=%d\n", retry);
5289 goto retry_unlock;
5290 }
5291
5292 return;
5293
5294 #if 0
5295 /* XXX: IDC-unlock implementation using access-control mbx */
5296 retry = 0;
5297 retry_unlock2:
5298 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5299 if (retry < 10) {
5300 /* Retry for IDC-unlock */
5301 qla83xx_wait_logic();
5302 retry++;
5303 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
5304 "Failed to release IDC lock, retrying=%d\n", retry);
5305 goto retry_unlock2;
5306 }
5307 }
5308
5309 return;
5310 #endif
5311 }
5312
5313 int
5314 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5315 {
5316 int rval = QLA_SUCCESS;
5317 struct qla_hw_data *ha = vha->hw;
5318 uint32_t drv_presence;
5319
5320 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5321 if (rval == QLA_SUCCESS) {
5322 drv_presence |= (1 << ha->portnum);
5323 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5324 drv_presence);
5325 }
5326
5327 return rval;
5328 }
5329
5330 int
5331 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5332 {
5333 int rval = QLA_SUCCESS;
5334
5335 qla83xx_idc_lock(vha, 0);
5336 rval = __qla83xx_set_drv_presence(vha);
5337 qla83xx_idc_unlock(vha, 0);
5338
5339 return rval;
5340 }
5341
5342 int
5343 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5344 {
5345 int rval = QLA_SUCCESS;
5346 struct qla_hw_data *ha = vha->hw;
5347 uint32_t drv_presence;
5348
5349 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5350 if (rval == QLA_SUCCESS) {
5351 drv_presence &= ~(1 << ha->portnum);
5352 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5353 drv_presence);
5354 }
5355
5356 return rval;
5357 }
5358
5359 int
5360 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5361 {
5362 int rval = QLA_SUCCESS;
5363
5364 qla83xx_idc_lock(vha, 0);
5365 rval = __qla83xx_clear_drv_presence(vha);
5366 qla83xx_idc_unlock(vha, 0);
5367
5368 return rval;
5369 }
5370
5371 static void
5372 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5373 {
5374 struct qla_hw_data *ha = vha->hw;
5375 uint32_t drv_ack, drv_presence;
5376 unsigned long ack_timeout;
5377
5378 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5379 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5380 while (1) {
5381 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5382 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5383 if ((drv_ack & drv_presence) == drv_presence)
5384 break;
5385
5386 if (time_after_eq(jiffies, ack_timeout)) {
5387 ql_log(ql_log_warn, vha, 0xb067,
5388 "RESET ACK TIMEOUT! drv_presence=0x%x "
5389 "drv_ack=0x%x\n", drv_presence, drv_ack);
5390 /*
5391 * The function(s) which did not ack in time are forced
5392 * to withdraw any further participation in the IDC
5393 * reset.
5394 */
5395 if (drv_ack != drv_presence)
5396 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5397 drv_ack);
5398 break;
5399 }
5400
5401 qla83xx_idc_unlock(vha, 0);
5402 msleep(1000);
5403 qla83xx_idc_lock(vha, 0);
5404 }
5405
5406 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5407 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5408 }
5409
5410 static int
5411 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5412 {
5413 int rval = QLA_SUCCESS;
5414 uint32_t idc_control;
5415
5416 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5417 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5418
5419 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5420 __qla83xx_get_idc_control(vha, &idc_control);
5421 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5422 __qla83xx_set_idc_control(vha, 0);
5423
5424 qla83xx_idc_unlock(vha, 0);
5425 rval = qla83xx_restart_nic_firmware(vha);
5426 qla83xx_idc_lock(vha, 0);
5427
5428 if (rval != QLA_SUCCESS) {
5429 ql_log(ql_log_fatal, vha, 0xb06a,
5430 "Failed to restart NIC f/w.\n");
5431 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5432 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5433 } else {
5434 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5435 "Success in restarting nic f/w.\n");
5436 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5437 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5438 }
5439
5440 return rval;
5441 }
5442
5443 /* Assumes idc_lock always held on entry */
5444 int
5445 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5446 {
5447 struct qla_hw_data *ha = base_vha->hw;
5448 int rval = QLA_SUCCESS;
5449 unsigned long dev_init_timeout;
5450 uint32_t dev_state;
5451
5452 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5453 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5454
5455 while (1) {
5456
5457 if (time_after_eq(jiffies, dev_init_timeout)) {
5458 ql_log(ql_log_warn, base_vha, 0xb06e,
5459 "Initialization TIMEOUT!\n");
5460 /* Init timeout. Disable further NIC Core
5461 * communication.
5462 */
5463 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5464 QLA8XXX_DEV_FAILED);
5465 ql_log(ql_log_info, base_vha, 0xb06f,
5466 "HW State: FAILED.\n");
5467 }
5468
5469 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5470 switch (dev_state) {
5471 case QLA8XXX_DEV_READY:
5472 if (ha->flags.nic_core_reset_owner)
5473 qla83xx_idc_audit(base_vha,
5474 IDC_AUDIT_COMPLETION);
5475 ha->flags.nic_core_reset_owner = 0;
5476 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5477 "Reset_owner reset by 0x%x.\n",
5478 ha->portnum);
5479 goto exit;
5480 case QLA8XXX_DEV_COLD:
5481 if (ha->flags.nic_core_reset_owner)
5482 rval = qla83xx_device_bootstrap(base_vha);
5483 else {
5484 /* Wait for AEN to change device-state */
5485 qla83xx_idc_unlock(base_vha, 0);
5486 msleep(1000);
5487 qla83xx_idc_lock(base_vha, 0);
5488 }
5489 break;
5490 case QLA8XXX_DEV_INITIALIZING:
5491 /* Wait for AEN to change device-state */
5492 qla83xx_idc_unlock(base_vha, 0);
5493 msleep(1000);
5494 qla83xx_idc_lock(base_vha, 0);
5495 break;
5496 case QLA8XXX_DEV_NEED_RESET:
5497 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5498 qla83xx_need_reset_handler(base_vha);
5499 else {
5500 /* Wait for AEN to change device-state */
5501 qla83xx_idc_unlock(base_vha, 0);
5502 msleep(1000);
5503 qla83xx_idc_lock(base_vha, 0);
5504 }
5505 /* reset timeout value after need reset handler */
5506 dev_init_timeout = jiffies +
5507 (ha->fcoe_dev_init_timeout * HZ);
5508 break;
5509 case QLA8XXX_DEV_NEED_QUIESCENT:
5510 /* XXX: DEBUG for now */
5511 qla83xx_idc_unlock(base_vha, 0);
5512 msleep(1000);
5513 qla83xx_idc_lock(base_vha, 0);
5514 break;
5515 case QLA8XXX_DEV_QUIESCENT:
5516 /* XXX: DEBUG for now */
5517 if (ha->flags.quiesce_owner)
5518 goto exit;
5519
5520 qla83xx_idc_unlock(base_vha, 0);
5521 msleep(1000);
5522 qla83xx_idc_lock(base_vha, 0);
5523 dev_init_timeout = jiffies +
5524 (ha->fcoe_dev_init_timeout * HZ);
5525 break;
5526 case QLA8XXX_DEV_FAILED:
5527 if (ha->flags.nic_core_reset_owner)
5528 qla83xx_idc_audit(base_vha,
5529 IDC_AUDIT_COMPLETION);
5530 ha->flags.nic_core_reset_owner = 0;
5531 __qla83xx_clear_drv_presence(base_vha);
5532 qla83xx_idc_unlock(base_vha, 0);
5533 qla8xxx_dev_failed_handler(base_vha);
5534 rval = QLA_FUNCTION_FAILED;
5535 qla83xx_idc_lock(base_vha, 0);
5536 goto exit;
5537 case QLA8XXX_BAD_VALUE:
5538 qla83xx_idc_unlock(base_vha, 0);
5539 msleep(1000);
5540 qla83xx_idc_lock(base_vha, 0);
5541 break;
5542 default:
5543 ql_log(ql_log_warn, base_vha, 0xb071,
5544 "Unknown Device State: %x.\n", dev_state);
5545 qla83xx_idc_unlock(base_vha, 0);
5546 qla8xxx_dev_failed_handler(base_vha);
5547 rval = QLA_FUNCTION_FAILED;
5548 qla83xx_idc_lock(base_vha, 0);
5549 goto exit;
5550 }
5551 }
5552
5553 exit:
5554 return rval;
5555 }
5556
5557 void
5558 qla2x00_disable_board_on_pci_error(struct work_struct *work)
5559 {
5560 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5561 board_disable);
5562 struct pci_dev *pdev = ha->pdev;
5563 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5564
5565 /*
5566 * if UNLOAD flag is already set, then continue unload,
5567 * where it was set first.
5568 */
5569 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5570 return;
5571
5572 ql_log(ql_log_warn, base_vha, 0x015b,
5573 "Disabling adapter.\n");
5574
5575 if (!atomic_read(&pdev->enable_cnt)) {
5576 ql_log(ql_log_info, base_vha, 0xfffc,
5577 "PCI device disabled, no action req for PCI error=%lx\n",
5578 base_vha->pci_flags);
5579 return;
5580 }
5581
5582 qla2x00_wait_for_sess_deletion(base_vha);
5583
5584 set_bit(UNLOADING, &base_vha->dpc_flags);
5585
5586 qla2x00_delete_all_vps(ha, base_vha);
5587
5588 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5589
5590 qla2x00_dfs_remove(base_vha);
5591
5592 qla84xx_put_chip(base_vha);
5593
5594 if (base_vha->timer_active)
5595 qla2x00_stop_timer(base_vha);
5596
5597 base_vha->flags.online = 0;
5598
5599 qla2x00_destroy_deferred_work(ha);
5600
5601 /*
5602 * Do not try to stop beacon blink as it will issue a mailbox
5603 * command.
5604 */
5605 qla2x00_free_sysfs_attr(base_vha, false);
5606
5607 fc_remove_host(base_vha->host);
5608
5609 scsi_remove_host(base_vha->host);
5610
5611 base_vha->flags.init_done = 0;
5612 qla25xx_delete_queues(base_vha);
5613 qla2x00_free_fcports(base_vha);
5614 qla2x00_free_irqs(base_vha);
5615 qla2x00_mem_free(ha);
5616 qla82xx_md_free(base_vha);
5617 qla2x00_free_queues(ha);
5618
5619 qla2x00_unmap_iobases(ha);
5620
5621 pci_release_selected_regions(ha->pdev, ha->bars);
5622 pci_disable_pcie_error_reporting(pdev);
5623 pci_disable_device(pdev);
5624
5625 /*
5626 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5627 */
5628 }
5629
5630 /**************************************************************************
5631 * qla2x00_do_dpc
5632 * This kernel thread is a task that is schedule by the interrupt handler
5633 * to perform the background processing for interrupts.
5634 *
5635 * Notes:
5636 * This task always run in the context of a kernel thread. It
5637 * is kick-off by the driver's detect code and starts up
5638 * up one per adapter. It immediately goes to sleep and waits for
5639 * some fibre event. When either the interrupt handler or
5640 * the timer routine detects a event it will one of the task
5641 * bits then wake us up.
5642 **************************************************************************/
5643 static int
5644 qla2x00_do_dpc(void *data)
5645 {
5646 scsi_qla_host_t *base_vha;
5647 struct qla_hw_data *ha;
5648 uint32_t online;
5649 struct qla_qpair *qpair;
5650
5651 ha = (struct qla_hw_data *)data;
5652 base_vha = pci_get_drvdata(ha->pdev);
5653
5654 set_user_nice(current, MIN_NICE);
5655
5656 set_current_state(TASK_INTERRUPTIBLE);
5657 while (!kthread_should_stop()) {
5658 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5659 "DPC handler sleeping.\n");
5660
5661 schedule();
5662
5663 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5664 goto end_loop;
5665
5666 if (ha->flags.eeh_busy) {
5667 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5668 "eeh_busy=%d.\n", ha->flags.eeh_busy);
5669 goto end_loop;
5670 }
5671
5672 ha->dpc_active = 1;
5673
5674 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5675 "DPC handler waking up, dpc_flags=0x%lx.\n",
5676 base_vha->dpc_flags);
5677
5678 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5679 break;
5680
5681 qla2x00_do_work(base_vha);
5682
5683 if (IS_P3P_TYPE(ha)) {
5684 if (IS_QLA8044(ha)) {
5685 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5686 &base_vha->dpc_flags)) {
5687 qla8044_idc_lock(ha);
5688 qla8044_wr_direct(base_vha,
5689 QLA8044_CRB_DEV_STATE_INDEX,
5690 QLA8XXX_DEV_FAILED);
5691 qla8044_idc_unlock(ha);
5692 ql_log(ql_log_info, base_vha, 0x4004,
5693 "HW State: FAILED.\n");
5694 qla8044_device_state_handler(base_vha);
5695 continue;
5696 }
5697
5698 } else {
5699 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5700 &base_vha->dpc_flags)) {
5701 qla82xx_idc_lock(ha);
5702 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5703 QLA8XXX_DEV_FAILED);
5704 qla82xx_idc_unlock(ha);
5705 ql_log(ql_log_info, base_vha, 0x0151,
5706 "HW State: FAILED.\n");
5707 qla82xx_device_state_handler(base_vha);
5708 continue;
5709 }
5710 }
5711
5712 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5713 &base_vha->dpc_flags)) {
5714
5715 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5716 "FCoE context reset scheduled.\n");
5717 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5718 &base_vha->dpc_flags))) {
5719 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5720 /* FCoE-ctx reset failed.
5721 * Escalate to chip-reset
5722 */
5723 set_bit(ISP_ABORT_NEEDED,
5724 &base_vha->dpc_flags);
5725 }
5726 clear_bit(ABORT_ISP_ACTIVE,
5727 &base_vha->dpc_flags);
5728 }
5729
5730 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5731 "FCoE context reset end.\n");
5732 }
5733 } else if (IS_QLAFX00(ha)) {
5734 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5735 &base_vha->dpc_flags)) {
5736 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5737 "Firmware Reset Recovery\n");
5738 if (qlafx00_reset_initialize(base_vha)) {
5739 /* Failed. Abort isp later. */
5740 if (!test_bit(UNLOADING,
5741 &base_vha->dpc_flags)) {
5742 set_bit(ISP_UNRECOVERABLE,
5743 &base_vha->dpc_flags);
5744 ql_dbg(ql_dbg_dpc, base_vha,
5745 0x4021,
5746 "Reset Recovery Failed\n");
5747 }
5748 }
5749 }
5750
5751 if (test_and_clear_bit(FX00_TARGET_SCAN,
5752 &base_vha->dpc_flags)) {
5753 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5754 "ISPFx00 Target Scan scheduled\n");
5755 if (qlafx00_rescan_isp(base_vha)) {
5756 if (!test_bit(UNLOADING,
5757 &base_vha->dpc_flags))
5758 set_bit(ISP_UNRECOVERABLE,
5759 &base_vha->dpc_flags);
5760 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5761 "ISPFx00 Target Scan Failed\n");
5762 }
5763 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5764 "ISPFx00 Target Scan End\n");
5765 }
5766 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5767 &base_vha->dpc_flags)) {
5768 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5769 "ISPFx00 Host Info resend scheduled\n");
5770 qlafx00_fx_disc(base_vha,
5771 &base_vha->hw->mr.fcport,
5772 FXDISC_REG_HOST_INFO);
5773 }
5774 }
5775
5776 if (test_and_clear_bit(DETECT_SFP_CHANGE,
5777 &base_vha->dpc_flags) &&
5778 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
5779 qla24xx_detect_sfp(base_vha);
5780
5781 if (ha->flags.detected_lr_sfp !=
5782 ha->flags.using_lr_setting)
5783 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
5784 }
5785
5786 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5787 &base_vha->dpc_flags)) {
5788
5789 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5790 "ISP abort scheduled.\n");
5791 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5792 &base_vha->dpc_flags))) {
5793
5794 if (ha->isp_ops->abort_isp(base_vha)) {
5795 /* failed. retry later */
5796 set_bit(ISP_ABORT_NEEDED,
5797 &base_vha->dpc_flags);
5798 }
5799 clear_bit(ABORT_ISP_ACTIVE,
5800 &base_vha->dpc_flags);
5801 }
5802
5803 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5804 "ISP abort end.\n");
5805 }
5806
5807 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5808 &base_vha->dpc_flags)) {
5809 qla2x00_update_fcports(base_vha);
5810 }
5811
5812 if (IS_QLAFX00(ha))
5813 goto loop_resync_check;
5814
5815 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
5816 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5817 "Quiescence mode scheduled.\n");
5818 if (IS_P3P_TYPE(ha)) {
5819 if (IS_QLA82XX(ha))
5820 qla82xx_device_state_handler(base_vha);
5821 if (IS_QLA8044(ha))
5822 qla8044_device_state_handler(base_vha);
5823 clear_bit(ISP_QUIESCE_NEEDED,
5824 &base_vha->dpc_flags);
5825 if (!ha->flags.quiesce_owner) {
5826 qla2x00_perform_loop_resync(base_vha);
5827 if (IS_QLA82XX(ha)) {
5828 qla82xx_idc_lock(ha);
5829 qla82xx_clear_qsnt_ready(
5830 base_vha);
5831 qla82xx_idc_unlock(ha);
5832 } else if (IS_QLA8044(ha)) {
5833 qla8044_idc_lock(ha);
5834 qla8044_clear_qsnt_ready(
5835 base_vha);
5836 qla8044_idc_unlock(ha);
5837 }
5838 }
5839 } else {
5840 clear_bit(ISP_QUIESCE_NEEDED,
5841 &base_vha->dpc_flags);
5842 qla2x00_quiesce_io(base_vha);
5843 }
5844 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5845 "Quiescence mode end.\n");
5846 }
5847
5848 if (test_and_clear_bit(RESET_MARKER_NEEDED,
5849 &base_vha->dpc_flags) &&
5850 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
5851
5852 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5853 "Reset marker scheduled.\n");
5854 qla2x00_rst_aen(base_vha);
5855 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
5856 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5857 "Reset marker end.\n");
5858 }
5859
5860 /* Retry each device up to login retry count */
5861 if ((test_and_clear_bit(RELOGIN_NEEDED,
5862 &base_vha->dpc_flags)) &&
5863 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5864 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
5865
5866 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5867 "Relogin scheduled.\n");
5868 qla2x00_relogin(base_vha);
5869 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5870 "Relogin end.\n");
5871 }
5872 loop_resync_check:
5873 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
5874 &base_vha->dpc_flags)) {
5875
5876 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5877 "Loop resync scheduled.\n");
5878
5879 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
5880 &base_vha->dpc_flags))) {
5881
5882 qla2x00_loop_resync(base_vha);
5883
5884 clear_bit(LOOP_RESYNC_ACTIVE,
5885 &base_vha->dpc_flags);
5886 }
5887
5888 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5889 "Loop resync end.\n");
5890 }
5891
5892 if (IS_QLAFX00(ha))
5893 goto intr_on_check;
5894
5895 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5896 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5897 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5898 qla2xxx_flash_npiv_conf(base_vha);
5899 }
5900
5901 intr_on_check:
5902 if (!ha->interrupts_on)
5903 ha->isp_ops->enable_intrs(ha);
5904
5905 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5906 &base_vha->dpc_flags)) {
5907 if (ha->beacon_blink_led == 1)
5908 ha->isp_ops->beacon_blink(base_vha);
5909 }
5910
5911 /* qpair online check */
5912 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5913 &base_vha->dpc_flags)) {
5914 if (ha->flags.eeh_busy ||
5915 ha->flags.pci_channel_io_perm_failure)
5916 online = 0;
5917 else
5918 online = 1;
5919
5920 mutex_lock(&ha->mq_lock);
5921 list_for_each_entry(qpair, &base_vha->qp_list,
5922 qp_list_elem)
5923 qpair->online = online;
5924 mutex_unlock(&ha->mq_lock);
5925 }
5926
5927 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
5928 ql_log(ql_log_info, base_vha, 0xffffff,
5929 "nvme: SET ZIO Activity exchange threshold to %d.\n",
5930 ha->nvme_last_rptd_aen);
5931 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
5932 ql_log(ql_log_info, base_vha, 0xffffff,
5933 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
5934 ha->nvme_last_rptd_aen);
5935 }
5936 }
5937
5938 if (!IS_QLAFX00(ha))
5939 qla2x00_do_dpc_all_vps(base_vha);
5940
5941 ha->dpc_active = 0;
5942 end_loop:
5943 set_current_state(TASK_INTERRUPTIBLE);
5944 } /* End of while(1) */
5945 __set_current_state(TASK_RUNNING);
5946
5947 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5948 "DPC handler exiting.\n");
5949
5950 /*
5951 * Make sure that nobody tries to wake us up again.
5952 */
5953 ha->dpc_active = 0;
5954
5955 /* Cleanup any residual CTX SRBs. */
5956 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5957
5958 return 0;
5959 }
5960
5961 void
5962 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5963 {
5964 struct qla_hw_data *ha = vha->hw;
5965 struct task_struct *t = ha->dpc_thread;
5966
5967 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5968 wake_up_process(t);
5969 }
5970
5971 /*
5972 * qla2x00_rst_aen
5973 * Processes asynchronous reset.
5974 *
5975 * Input:
5976 * ha = adapter block pointer.
5977 */
5978 static void
5979 qla2x00_rst_aen(scsi_qla_host_t *vha)
5980 {
5981 if (vha->flags.online && !vha->flags.reset_active &&
5982 !atomic_read(&vha->loop_down_timer) &&
5983 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5984 do {
5985 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5986
5987 /*
5988 * Issue marker command only when we are going to start
5989 * the I/O.
5990 */
5991 vha->marker_needed = 1;
5992 } while (!atomic_read(&vha->loop_down_timer) &&
5993 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
5994 }
5995 }
5996
5997 /**************************************************************************
5998 * qla2x00_timer
5999 *
6000 * Description:
6001 * One second timer
6002 *
6003 * Context: Interrupt
6004 ***************************************************************************/
6005 void
6006 qla2x00_timer(scsi_qla_host_t *vha)
6007 {
6008 unsigned long cpu_flags = 0;
6009 int start_dpc = 0;
6010 int index;
6011 srb_t *sp;
6012 uint16_t w;
6013 struct qla_hw_data *ha = vha->hw;
6014 struct req_que *req;
6015
6016 if (ha->flags.eeh_busy) {
6017 ql_dbg(ql_dbg_timer, vha, 0x6000,
6018 "EEH = %d, restarting timer.\n",
6019 ha->flags.eeh_busy);
6020 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6021 return;
6022 }
6023
6024 /*
6025 * Hardware read to raise pending EEH errors during mailbox waits. If
6026 * the read returns -1 then disable the board.
6027 */
6028 if (!pci_channel_offline(ha->pdev)) {
6029 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
6030 qla2x00_check_reg16_for_disconnect(vha, w);
6031 }
6032
6033 /* Make sure qla82xx_watchdog is run only for physical port */
6034 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
6035 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6036 start_dpc++;
6037 if (IS_QLA82XX(ha))
6038 qla82xx_watchdog(vha);
6039 else if (IS_QLA8044(ha))
6040 qla8044_watchdog(vha);
6041 }
6042
6043 if (!vha->vp_idx && IS_QLAFX00(ha))
6044 qlafx00_timer_routine(vha);
6045
6046 /* Loop down handler. */
6047 if (atomic_read(&vha->loop_down_timer) > 0 &&
6048 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6049 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
6050 && vha->flags.online) {
6051
6052 if (atomic_read(&vha->loop_down_timer) ==
6053 vha->loop_down_abort_time) {
6054
6055 ql_log(ql_log_info, vha, 0x6008,
6056 "Loop down - aborting the queues before time expires.\n");
6057
6058 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6059 atomic_set(&vha->loop_state, LOOP_DEAD);
6060
6061 /*
6062 * Schedule an ISP abort to return any FCP2-device
6063 * commands.
6064 */
6065 /* NPIV - scan physical port only */
6066 if (!vha->vp_idx) {
6067 spin_lock_irqsave(&ha->hardware_lock,
6068 cpu_flags);
6069 req = ha->req_q_map[0];
6070 for (index = 1;
6071 index < req->num_outstanding_cmds;
6072 index++) {
6073 fc_port_t *sfcp;
6074
6075 sp = req->outstanding_cmds[index];
6076 if (!sp)
6077 continue;
6078 if (sp->cmd_type != TYPE_SRB)
6079 continue;
6080 if (sp->type != SRB_SCSI_CMD)
6081 continue;
6082 sfcp = sp->fcport;
6083 if (!(sfcp->flags & FCF_FCP2_DEVICE))
6084 continue;
6085
6086 if (IS_QLA82XX(ha))
6087 set_bit(FCOE_CTX_RESET_NEEDED,
6088 &vha->dpc_flags);
6089 else
6090 set_bit(ISP_ABORT_NEEDED,
6091 &vha->dpc_flags);
6092 break;
6093 }
6094 spin_unlock_irqrestore(&ha->hardware_lock,
6095 cpu_flags);
6096 }
6097 start_dpc++;
6098 }
6099
6100 /* if the loop has been down for 4 minutes, reinit adapter */
6101 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
6102 if (!(vha->device_flags & DFLG_NO_CABLE)) {
6103 ql_log(ql_log_warn, vha, 0x6009,
6104 "Loop down - aborting ISP.\n");
6105
6106 if (IS_QLA82XX(ha))
6107 set_bit(FCOE_CTX_RESET_NEEDED,
6108 &vha->dpc_flags);
6109 else
6110 set_bit(ISP_ABORT_NEEDED,
6111 &vha->dpc_flags);
6112 }
6113 }
6114 ql_dbg(ql_dbg_timer, vha, 0x600a,
6115 "Loop down - seconds remaining %d.\n",
6116 atomic_read(&vha->loop_down_timer));
6117 }
6118 /* Check if beacon LED needs to be blinked for physical host only */
6119 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
6120 /* There is no beacon_blink function for ISP82xx */
6121 if (!IS_P3P_TYPE(ha)) {
6122 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6123 start_dpc++;
6124 }
6125 }
6126
6127 /* Process any deferred work. */
6128 if (!list_empty(&vha->work_list))
6129 start_dpc++;
6130
6131 /*
6132 * FC-NVME
6133 * see if the active AEN count has changed from what was last reported.
6134 */
6135 if (!vha->vp_idx &&
6136 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
6137 ha->zio_mode == QLA_ZIO_MODE_6) {
6138 ql_log(ql_log_info, vha, 0x3002,
6139 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6140 ha->nvme_last_rptd_aen);
6141 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6142 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6143 start_dpc++;
6144 }
6145
6146 /* Schedule the DPC routine if needed */
6147 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6148 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6149 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
6150 start_dpc ||
6151 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6152 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
6153 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6154 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
6155 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
6156 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
6157 ql_dbg(ql_dbg_timer, vha, 0x600b,
6158 "isp_abort_needed=%d loop_resync_needed=%d "
6159 "fcport_update_needed=%d start_dpc=%d "
6160 "reset_marker_needed=%d",
6161 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6162 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6163 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6164 start_dpc,
6165 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6166 ql_dbg(ql_dbg_timer, vha, 0x600c,
6167 "beacon_blink_needed=%d isp_unrecoverable=%d "
6168 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
6169 "relogin_needed=%d.\n",
6170 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6171 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6172 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6173 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
6174 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
6175 qla2xxx_wake_dpc(vha);
6176 }
6177
6178 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6179 }
6180
6181 /* Firmware interface routines. */
6182
6183 #define FW_BLOBS 11
6184 #define FW_ISP21XX 0
6185 #define FW_ISP22XX 1
6186 #define FW_ISP2300 2
6187 #define FW_ISP2322 3
6188 #define FW_ISP24XX 4
6189 #define FW_ISP25XX 5
6190 #define FW_ISP81XX 6
6191 #define FW_ISP82XX 7
6192 #define FW_ISP2031 8
6193 #define FW_ISP8031 9
6194 #define FW_ISP27XX 10
6195
6196 #define FW_FILE_ISP21XX "ql2100_fw.bin"
6197 #define FW_FILE_ISP22XX "ql2200_fw.bin"
6198 #define FW_FILE_ISP2300 "ql2300_fw.bin"
6199 #define FW_FILE_ISP2322 "ql2322_fw.bin"
6200 #define FW_FILE_ISP24XX "ql2400_fw.bin"
6201 #define FW_FILE_ISP25XX "ql2500_fw.bin"
6202 #define FW_FILE_ISP81XX "ql8100_fw.bin"
6203 #define FW_FILE_ISP82XX "ql8200_fw.bin"
6204 #define FW_FILE_ISP2031 "ql2600_fw.bin"
6205 #define FW_FILE_ISP8031 "ql8300_fw.bin"
6206 #define FW_FILE_ISP27XX "ql2700_fw.bin"
6207
6208
6209 static DEFINE_MUTEX(qla_fw_lock);
6210
6211 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
6212 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6213 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6214 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6215 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6216 { .name = FW_FILE_ISP24XX, },
6217 { .name = FW_FILE_ISP25XX, },
6218 { .name = FW_FILE_ISP81XX, },
6219 { .name = FW_FILE_ISP82XX, },
6220 { .name = FW_FILE_ISP2031, },
6221 { .name = FW_FILE_ISP8031, },
6222 { .name = FW_FILE_ISP27XX, },
6223 };
6224
6225 struct fw_blob *
6226 qla2x00_request_firmware(scsi_qla_host_t *vha)
6227 {
6228 struct qla_hw_data *ha = vha->hw;
6229 struct fw_blob *blob;
6230
6231 if (IS_QLA2100(ha)) {
6232 blob = &qla_fw_blobs[FW_ISP21XX];
6233 } else if (IS_QLA2200(ha)) {
6234 blob = &qla_fw_blobs[FW_ISP22XX];
6235 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
6236 blob = &qla_fw_blobs[FW_ISP2300];
6237 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
6238 blob = &qla_fw_blobs[FW_ISP2322];
6239 } else if (IS_QLA24XX_TYPE(ha)) {
6240 blob = &qla_fw_blobs[FW_ISP24XX];
6241 } else if (IS_QLA25XX(ha)) {
6242 blob = &qla_fw_blobs[FW_ISP25XX];
6243 } else if (IS_QLA81XX(ha)) {
6244 blob = &qla_fw_blobs[FW_ISP81XX];
6245 } else if (IS_QLA82XX(ha)) {
6246 blob = &qla_fw_blobs[FW_ISP82XX];
6247 } else if (IS_QLA2031(ha)) {
6248 blob = &qla_fw_blobs[FW_ISP2031];
6249 } else if (IS_QLA8031(ha)) {
6250 blob = &qla_fw_blobs[FW_ISP8031];
6251 } else if (IS_QLA27XX(ha)) {
6252 blob = &qla_fw_blobs[FW_ISP27XX];
6253 } else {
6254 return NULL;
6255 }
6256
6257 mutex_lock(&qla_fw_lock);
6258 if (blob->fw)
6259 goto out;
6260
6261 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
6262 ql_log(ql_log_warn, vha, 0x0063,
6263 "Failed to load firmware image (%s).\n", blob->name);
6264 blob->fw = NULL;
6265 blob = NULL;
6266 goto out;
6267 }
6268
6269 out:
6270 mutex_unlock(&qla_fw_lock);
6271 return blob;
6272 }
6273
6274 static void
6275 qla2x00_release_firmware(void)
6276 {
6277 int idx;
6278
6279 mutex_lock(&qla_fw_lock);
6280 for (idx = 0; idx < FW_BLOBS; idx++)
6281 release_firmware(qla_fw_blobs[idx].fw);
6282 mutex_unlock(&qla_fw_lock);
6283 }
6284
6285 static pci_ers_result_t
6286 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6287 {
6288 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6289 struct qla_hw_data *ha = vha->hw;
6290
6291 ql_dbg(ql_dbg_aer, vha, 0x9000,
6292 "PCI error detected, state %x.\n", state);
6293
6294 if (!atomic_read(&pdev->enable_cnt)) {
6295 ql_log(ql_log_info, vha, 0xffff,
6296 "PCI device is disabled,state %x\n", state);
6297 return PCI_ERS_RESULT_NEED_RESET;
6298 }
6299
6300 switch (state) {
6301 case pci_channel_io_normal:
6302 ha->flags.eeh_busy = 0;
6303 if (ql2xmqsupport) {
6304 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6305 qla2xxx_wake_dpc(vha);
6306 }
6307 return PCI_ERS_RESULT_CAN_RECOVER;
6308 case pci_channel_io_frozen:
6309 ha->flags.eeh_busy = 1;
6310 /* For ISP82XX complete any pending mailbox cmd */
6311 if (IS_QLA82XX(ha)) {
6312 ha->flags.isp82xx_fw_hung = 1;
6313 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6314 qla82xx_clear_pending_mbx(vha);
6315 }
6316 qla2x00_free_irqs(vha);
6317 pci_disable_device(pdev);
6318 /* Return back all IOs */
6319 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6320 if (ql2xmqsupport) {
6321 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6322 qla2xxx_wake_dpc(vha);
6323 }
6324 return PCI_ERS_RESULT_NEED_RESET;
6325 case pci_channel_io_perm_failure:
6326 ha->flags.pci_channel_io_perm_failure = 1;
6327 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
6328 if (ql2xmqsupport) {
6329 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6330 qla2xxx_wake_dpc(vha);
6331 }
6332 return PCI_ERS_RESULT_DISCONNECT;
6333 }
6334 return PCI_ERS_RESULT_NEED_RESET;
6335 }
6336
6337 static pci_ers_result_t
6338 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6339 {
6340 int risc_paused = 0;
6341 uint32_t stat;
6342 unsigned long flags;
6343 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6344 struct qla_hw_data *ha = base_vha->hw;
6345 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6346 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6347
6348 if (IS_QLA82XX(ha))
6349 return PCI_ERS_RESULT_RECOVERED;
6350
6351 spin_lock_irqsave(&ha->hardware_lock, flags);
6352 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6353 stat = RD_REG_DWORD(&reg->hccr);
6354 if (stat & HCCR_RISC_PAUSE)
6355 risc_paused = 1;
6356 } else if (IS_QLA23XX(ha)) {
6357 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6358 if (stat & HSR_RISC_PAUSED)
6359 risc_paused = 1;
6360 } else if (IS_FWI2_CAPABLE(ha)) {
6361 stat = RD_REG_DWORD(&reg24->host_status);
6362 if (stat & HSRX_RISC_PAUSED)
6363 risc_paused = 1;
6364 }
6365 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6366
6367 if (risc_paused) {
6368 ql_log(ql_log_info, base_vha, 0x9003,
6369 "RISC paused -- mmio_enabled, Dumping firmware.\n");
6370 ha->isp_ops->fw_dump(base_vha, 0);
6371
6372 return PCI_ERS_RESULT_NEED_RESET;
6373 } else
6374 return PCI_ERS_RESULT_RECOVERED;
6375 }
6376
6377 static uint32_t
6378 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
6379 {
6380 uint32_t rval = QLA_FUNCTION_FAILED;
6381 uint32_t drv_active = 0;
6382 struct qla_hw_data *ha = base_vha->hw;
6383 int fn;
6384 struct pci_dev *other_pdev = NULL;
6385
6386 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6387 "Entered %s.\n", __func__);
6388
6389 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6390
6391 if (base_vha->flags.online) {
6392 /* Abort all outstanding commands,
6393 * so as to be requeued later */
6394 qla2x00_abort_isp_cleanup(base_vha);
6395 }
6396
6397
6398 fn = PCI_FUNC(ha->pdev->devfn);
6399 while (fn > 0) {
6400 fn--;
6401 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6402 "Finding pci device at function = 0x%x.\n", fn);
6403 other_pdev =
6404 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6405 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6406 fn));
6407
6408 if (!other_pdev)
6409 continue;
6410 if (atomic_read(&other_pdev->enable_cnt)) {
6411 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6412 "Found PCI func available and enable at 0x%x.\n",
6413 fn);
6414 pci_dev_put(other_pdev);
6415 break;
6416 }
6417 pci_dev_put(other_pdev);
6418 }
6419
6420 if (!fn) {
6421 /* Reset owner */
6422 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6423 "This devfn is reset owner = 0x%x.\n",
6424 ha->pdev->devfn);
6425 qla82xx_idc_lock(ha);
6426
6427 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6428 QLA8XXX_DEV_INITIALIZING);
6429
6430 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6431 QLA82XX_IDC_VERSION);
6432
6433 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
6434 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6435 "drv_active = 0x%x.\n", drv_active);
6436
6437 qla82xx_idc_unlock(ha);
6438 /* Reset if device is not already reset
6439 * drv_active would be 0 if a reset has already been done
6440 */
6441 if (drv_active)
6442 rval = qla82xx_start_firmware(base_vha);
6443 else
6444 rval = QLA_SUCCESS;
6445 qla82xx_idc_lock(ha);
6446
6447 if (rval != QLA_SUCCESS) {
6448 ql_log(ql_log_info, base_vha, 0x900b,
6449 "HW State: FAILED.\n");
6450 qla82xx_clear_drv_active(ha);
6451 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6452 QLA8XXX_DEV_FAILED);
6453 } else {
6454 ql_log(ql_log_info, base_vha, 0x900c,
6455 "HW State: READY.\n");
6456 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6457 QLA8XXX_DEV_READY);
6458 qla82xx_idc_unlock(ha);
6459 ha->flags.isp82xx_fw_hung = 0;
6460 rval = qla82xx_restart_isp(base_vha);
6461 qla82xx_idc_lock(ha);
6462 /* Clear driver state register */
6463 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6464 qla82xx_set_drv_active(base_vha);
6465 }
6466 qla82xx_idc_unlock(ha);
6467 } else {
6468 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6469 "This devfn is not reset owner = 0x%x.\n",
6470 ha->pdev->devfn);
6471 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
6472 QLA8XXX_DEV_READY)) {
6473 ha->flags.isp82xx_fw_hung = 0;
6474 rval = qla82xx_restart_isp(base_vha);
6475 qla82xx_idc_lock(ha);
6476 qla82xx_set_drv_active(base_vha);
6477 qla82xx_idc_unlock(ha);
6478 }
6479 }
6480 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6481
6482 return rval;
6483 }
6484
6485 static pci_ers_result_t
6486 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6487 {
6488 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
6489 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6490 struct qla_hw_data *ha = base_vha->hw;
6491 struct rsp_que *rsp;
6492 int rc, retries = 10;
6493
6494 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6495 "Slot Reset.\n");
6496
6497 /* Workaround: qla2xxx driver which access hardware earlier
6498 * needs error state to be pci_channel_io_online.
6499 * Otherwise mailbox command timesout.
6500 */
6501 pdev->error_state = pci_channel_io_normal;
6502
6503 pci_restore_state(pdev);
6504
6505 /* pci_restore_state() clears the saved_state flag of the device
6506 * save restored state which resets saved_state flag
6507 */
6508 pci_save_state(pdev);
6509
6510 if (ha->mem_only)
6511 rc = pci_enable_device_mem(pdev);
6512 else
6513 rc = pci_enable_device(pdev);
6514
6515 if (rc) {
6516 ql_log(ql_log_warn, base_vha, 0x9005,
6517 "Can't re-enable PCI device after reset.\n");
6518 goto exit_slot_reset;
6519 }
6520
6521 rsp = ha->rsp_q_map[0];
6522 if (qla2x00_request_irqs(ha, rsp))
6523 goto exit_slot_reset;
6524
6525 if (ha->isp_ops->pci_config(base_vha))
6526 goto exit_slot_reset;
6527
6528 if (IS_QLA82XX(ha)) {
6529 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6530 ret = PCI_ERS_RESULT_RECOVERED;
6531 goto exit_slot_reset;
6532 } else
6533 goto exit_slot_reset;
6534 }
6535
6536 while (ha->flags.mbox_busy && retries--)
6537 msleep(1000);
6538
6539 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6540 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
6541 ret = PCI_ERS_RESULT_RECOVERED;
6542 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6543
6544
6545 exit_slot_reset:
6546 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6547 "slot_reset return %x.\n", ret);
6548
6549 return ret;
6550 }
6551
6552 static void
6553 qla2xxx_pci_resume(struct pci_dev *pdev)
6554 {
6555 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6556 struct qla_hw_data *ha = base_vha->hw;
6557 int ret;
6558
6559 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6560 "pci_resume.\n");
6561
6562 ret = qla2x00_wait_for_hba_online(base_vha);
6563 if (ret != QLA_SUCCESS) {
6564 ql_log(ql_log_fatal, base_vha, 0x9002,
6565 "The device failed to resume I/O from slot/link_reset.\n");
6566 }
6567
6568 pci_cleanup_aer_uncorrect_error_status(pdev);
6569
6570 ha->flags.eeh_busy = 0;
6571 }
6572
6573 static void
6574 qla83xx_disable_laser(scsi_qla_host_t *vha)
6575 {
6576 uint32_t reg, data, fn;
6577 struct qla_hw_data *ha = vha->hw;
6578 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6579
6580 /* pci func #/port # */
6581 ql_dbg(ql_dbg_init, vha, 0x004b,
6582 "Disabling Laser for hba: %p\n", vha);
6583
6584 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6585 (BIT_15|BIT_14|BIT_13|BIT_12));
6586
6587 fn = (fn >> 12);
6588
6589 if (fn & 1)
6590 reg = PORT_1_2031;
6591 else
6592 reg = PORT_0_2031;
6593
6594 data = LASER_OFF_2031;
6595
6596 qla83xx_wr_reg(vha, reg, data);
6597 }
6598
6599 static int qla2xxx_map_queues(struct Scsi_Host *shost)
6600 {
6601 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6602
6603 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6604 }
6605
6606 static const struct pci_error_handlers qla2xxx_err_handler = {
6607 .error_detected = qla2xxx_pci_error_detected,
6608 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6609 .slot_reset = qla2xxx_pci_slot_reset,
6610 .resume = qla2xxx_pci_resume,
6611 };
6612
6613 static struct pci_device_id qla2xxx_pci_tbl[] = {
6614 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6615 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6616 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6617 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6618 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6619 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6620 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6621 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6622 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
6623 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
6624 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6625 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
6626 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6627 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
6628 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
6629 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
6630 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
6631 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
6632 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
6633 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
6634 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
6635 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
6636 { 0 },
6637 };
6638 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6639
6640 static struct pci_driver qla2xxx_pci_driver = {
6641 .name = QLA2XXX_DRIVER_NAME,
6642 .driver = {
6643 .owner = THIS_MODULE,
6644 },
6645 .id_table = qla2xxx_pci_tbl,
6646 .probe = qla2x00_probe_one,
6647 .remove = qla2x00_remove_one,
6648 .shutdown = qla2x00_shutdown,
6649 .err_handler = &qla2xxx_err_handler,
6650 };
6651
6652 static const struct file_operations apidev_fops = {
6653 .owner = THIS_MODULE,
6654 .llseek = noop_llseek,
6655 };
6656
6657 /**
6658 * qla2x00_module_init - Module initialization.
6659 **/
6660 static int __init
6661 qla2x00_module_init(void)
6662 {
6663 int ret = 0;
6664
6665 /* Allocate cache for SRBs. */
6666 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
6667 SLAB_HWCACHE_ALIGN, NULL);
6668 if (srb_cachep == NULL) {
6669 ql_log(ql_log_fatal, NULL, 0x0001,
6670 "Unable to allocate SRB cache...Failing load!.\n");
6671 return -ENOMEM;
6672 }
6673
6674 /* Initialize target kmem_cache and mem_pools */
6675 ret = qlt_init();
6676 if (ret < 0) {
6677 kmem_cache_destroy(srb_cachep);
6678 return ret;
6679 } else if (ret > 0) {
6680 /*
6681 * If initiator mode is explictly disabled by qlt_init(),
6682 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6683 * performing scsi_scan_target() during LOOP UP event.
6684 */
6685 qla2xxx_transport_functions.disable_target_scan = 1;
6686 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6687 }
6688
6689 /* Derive version string. */
6690 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
6691 if (ql2xextended_error_logging)
6692 strcat(qla2x00_version_str, "-debug");
6693 if (ql2xextended_error_logging == 1)
6694 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
6695
6696 qla2xxx_transport_template =
6697 fc_attach_transport(&qla2xxx_transport_functions);
6698 if (!qla2xxx_transport_template) {
6699 kmem_cache_destroy(srb_cachep);
6700 ql_log(ql_log_fatal, NULL, 0x0002,
6701 "fc_attach_transport failed...Failing load!.\n");
6702 qlt_exit();
6703 return -ENODEV;
6704 }
6705
6706 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6707 if (apidev_major < 0) {
6708 ql_log(ql_log_fatal, NULL, 0x0003,
6709 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6710 }
6711
6712 qla2xxx_transport_vport_template =
6713 fc_attach_transport(&qla2xxx_transport_vport_functions);
6714 if (!qla2xxx_transport_vport_template) {
6715 kmem_cache_destroy(srb_cachep);
6716 qlt_exit();
6717 fc_release_transport(qla2xxx_transport_template);
6718 ql_log(ql_log_fatal, NULL, 0x0004,
6719 "fc_attach_transport vport failed...Failing load!.\n");
6720 return -ENODEV;
6721 }
6722 ql_log(ql_log_info, NULL, 0x0005,
6723 "QLogic Fibre Channel HBA Driver: %s.\n",
6724 qla2x00_version_str);
6725 ret = pci_register_driver(&qla2xxx_pci_driver);
6726 if (ret) {
6727 kmem_cache_destroy(srb_cachep);
6728 qlt_exit();
6729 fc_release_transport(qla2xxx_transport_template);
6730 fc_release_transport(qla2xxx_transport_vport_template);
6731 ql_log(ql_log_fatal, NULL, 0x0006,
6732 "pci_register_driver failed...ret=%d Failing load!.\n",
6733 ret);
6734 }
6735 return ret;
6736 }
6737
6738 /**
6739 * qla2x00_module_exit - Module cleanup.
6740 **/
6741 static void __exit
6742 qla2x00_module_exit(void)
6743 {
6744 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
6745 pci_unregister_driver(&qla2xxx_pci_driver);
6746 qla2x00_release_firmware();
6747 kmem_cache_destroy(srb_cachep);
6748 qlt_exit();
6749 if (ctx_cachep)
6750 kmem_cache_destroy(ctx_cachep);
6751 fc_release_transport(qla2xxx_transport_template);
6752 fc_release_transport(qla2xxx_transport_vport_template);
6753 }
6754
6755 module_init(qla2x00_module_init);
6756 module_exit(qla2x00_module_exit);
6757
6758 MODULE_AUTHOR("QLogic Corporation");
6759 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6760 MODULE_LICENSE("GPL");
6761 MODULE_VERSION(QLA2XXX_VERSION);
6762 MODULE_FIRMWARE(FW_FILE_ISP21XX);
6763 MODULE_FIRMWARE(FW_FILE_ISP22XX);
6764 MODULE_FIRMWARE(FW_FILE_ISP2300);
6765 MODULE_FIRMWARE(FW_FILE_ISP2322);
6766 MODULE_FIRMWARE(FW_FILE_ISP24XX);
6767 MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux with added FPC-III support