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perf intel-pt: Factor out intel_pt_8b_tsc()
[linux/fpc-iii.git] / drivers / phy / marvell / phy-mvebu-cp110-comphy.c
blobd98e0451f6a18a85cd3d1113912f29a3dcb44a4d
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017 Marvell
4 *
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
6 */
7
8 #include <linux/io.h>
9 #include <linux/iopoll.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/module.h>
12 #include <linux/phy.h>
13 #include <linux/phy/phy.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16
17 /* Relative to priv->base */
18 #define MVEBU_COMPHY_SERDES_CFG0(n) (0x0 + (n) * 0x1000)
19 #define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1)
20 #define MVEBU_COMPHY_SERDES_CFG0_GEN_RX(n) ((n) << 3)
21 #define MVEBU_COMPHY_SERDES_CFG0_GEN_TX(n) ((n) << 7)
22 #define MVEBU_COMPHY_SERDES_CFG0_PU_RX BIT(11)
23 #define MVEBU_COMPHY_SERDES_CFG0_PU_TX BIT(12)
24 #define MVEBU_COMPHY_SERDES_CFG0_HALF_BUS BIT(14)
25 #define MVEBU_COMPHY_SERDES_CFG1(n) (0x4 + (n) * 0x1000)
26 #define MVEBU_COMPHY_SERDES_CFG1_RESET BIT(3)
27 #define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4)
28 #define MVEBU_COMPHY_SERDES_CFG1_CORE_RESET BIT(5)
29 #define MVEBU_COMPHY_SERDES_CFG1_RF_RESET BIT(6)
30 #define MVEBU_COMPHY_SERDES_CFG2(n) (0x8 + (n) * 0x1000)
31 #define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4)
32 #define MVEBU_COMPHY_SERDES_STATUS0(n) (0x18 + (n) * 0x1000)
33 #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2)
34 #define MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY BIT(3)
35 #define MVEBU_COMPHY_SERDES_STATUS0_RX_INIT BIT(4)
36 #define MVEBU_COMPHY_PWRPLL_CTRL(n) (0x804 + (n) * 0x1000)
37 #define MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(n) ((n) << 0)
38 #define MVEBU_COMPHY_PWRPLL_PHY_MODE(n) ((n) << 5)
39 #define MVEBU_COMPHY_IMP_CAL(n) (0x80c + (n) * 0x1000)
40 #define MVEBU_COMPHY_IMP_CAL_TX_EXT(n) ((n) << 10)
41 #define MVEBU_COMPHY_IMP_CAL_TX_EXT_EN BIT(15)
42 #define MVEBU_COMPHY_DFE_RES(n) (0x81c + (n) * 0x1000)
43 #define MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL BIT(15)
44 #define MVEBU_COMPHY_COEF(n) (0x828 + (n) * 0x1000)
45 #define MVEBU_COMPHY_COEF_DFE_EN BIT(14)
46 #define MVEBU_COMPHY_COEF_DFE_CTRL BIT(15)
47 #define MVEBU_COMPHY_GEN1_S0(n) (0x834 + (n) * 0x1000)
48 #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1)
49 #define MVEBU_COMPHY_GEN1_S0_TX_EMPH(n) ((n) << 7)
50 #define MVEBU_COMPHY_GEN1_S1(n) (0x838 + (n) * 0x1000)
51 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(n) ((n) << 0)
52 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(n) ((n) << 3)
53 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(n) ((n) << 6)
54 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(n) ((n) << 8)
55 #define MVEBU_COMPHY_GEN1_S1_RX_DFE_EN BIT(10)
56 #define MVEBU_COMPHY_GEN1_S1_RX_DIV(n) ((n) << 11)
57 #define MVEBU_COMPHY_GEN1_S2(n) (0x8f4 + (n) * 0x1000)
58 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH(n) ((n) << 0)
59 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4)
60 #define MVEBU_COMPHY_LOOPBACK(n) (0x88c + (n) * 0x1000)
61 #define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1)
62 #define MVEBU_COMPHY_VDD_CAL0(n) (0x908 + (n) * 0x1000)
63 #define MVEBU_COMPHY_VDD_CAL0_CONT_MODE BIT(15)
64 #define MVEBU_COMPHY_EXT_SELV(n) (0x914 + (n) * 0x1000)
65 #define MVEBU_COMPHY_EXT_SELV_RX_SAMPL(n) ((n) << 5)
66 #define MVEBU_COMPHY_MISC_CTRL0(n) (0x93c + (n) * 0x1000)
67 #define MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE BIT(5)
68 #define MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL BIT(10)
69 #define MVEBU_COMPHY_RX_CTRL1(n) (0x940 + (n) * 0x1000)
70 #define MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL BIT(11)
71 #define MVEBU_COMPHY_RX_CTRL1_CLK8T_EN BIT(12)
72 #define MVEBU_COMPHY_SPEED_DIV(n) (0x954 + (n) * 0x1000)
73 #define MVEBU_COMPHY_SPEED_DIV_TX_FORCE BIT(7)
74 #define MVEBU_SP_CALIB(n) (0x96c + (n) * 0x1000)
75 #define MVEBU_SP_CALIB_SAMPLER(n) ((n) << 8)
76 #define MVEBU_SP_CALIB_SAMPLER_EN BIT(12)
77 #define MVEBU_COMPHY_TX_SLEW_RATE(n) (0x974 + (n) * 0x1000)
78 #define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5)
79 #define MVEBU_COMPHY_TX_SLEW_RATE_SLC(n) ((n) << 10)
80 #define MVEBU_COMPHY_DLT_CTRL(n) (0x984 + (n) * 0x1000)
81 #define MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN BIT(2)
82 #define MVEBU_COMPHY_FRAME_DETECT0(n) (0xa14 + (n) * 0x1000)
83 #define MVEBU_COMPHY_FRAME_DETECT0_PATN(n) ((n) << 7)
84 #define MVEBU_COMPHY_FRAME_DETECT3(n) (0xa20 + (n) * 0x1000)
85 #define MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN BIT(12)
86 #define MVEBU_COMPHY_DME(n) (0xa28 + (n) * 0x1000)
87 #define MVEBU_COMPHY_DME_ETH_MODE BIT(7)
88 #define MVEBU_COMPHY_TRAINING0(n) (0xa68 + (n) * 0x1000)
89 #define MVEBU_COMPHY_TRAINING0_P2P_HOLD BIT(15)
90 #define MVEBU_COMPHY_TRAINING5(n) (0xaa4 + (n) * 0x1000)
91 #define MVEBU_COMPHY_TRAINING5_RX_TIMER(n) ((n) << 0)
92 #define MVEBU_COMPHY_TX_TRAIN_PRESET(n) (0xb1c + (n) * 0x1000)
93 #define MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN BIT(8)
94 #define MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11 BIT(9)
95 #define MVEBU_COMPHY_GEN1_S3(n) (0xc40 + (n) * 0x1000)
96 #define MVEBU_COMPHY_GEN1_S3_FBCK_SEL BIT(9)
97 #define MVEBU_COMPHY_GEN1_S4(n) (0xc44 + (n) * 0x1000)
98 #define MVEBU_COMPHY_GEN1_S4_DFE_RES(n) ((n) << 8)
99 #define MVEBU_COMPHY_TX_PRESET(n) (0xc68 + (n) * 0x1000)
100 #define MVEBU_COMPHY_TX_PRESET_INDEX(n) ((n) << 0)
101 #define MVEBU_COMPHY_GEN1_S5(n) (0xd38 + (n) * 0x1000)
102 #define MVEBU_COMPHY_GEN1_S5_ICP(n) ((n) << 0)
103
104 /* Relative to priv->regmap */
105 #define MVEBU_COMPHY_CONF1(n) (0x1000 + (n) * 0x28)
106 #define MVEBU_COMPHY_CONF1_PWRUP BIT(1)
107 #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */
108 #define MVEBU_COMPHY_CONF6(n) (0x1014 + (n) * 0x28)
109 #define MVEBU_COMPHY_CONF6_40B BIT(18)
110 #define MVEBU_COMPHY_SELECTOR 0x1140
111 #define MVEBU_COMPHY_SELECTOR_PHY(n) ((n) * 0x4)
112 #define MVEBU_COMPHY_PIPE_SELECTOR 0x1144
113 #define MVEBU_COMPHY_PIPE_SELECTOR_PIPE(n) ((n) * 0x4)
114
115 #define MVEBU_COMPHY_LANES 6
116 #define MVEBU_COMPHY_PORTS 3
117
118 struct mvebu_comphy_conf {
119 enum phy_mode mode;
120 int submode;
121 unsigned lane;
122 unsigned port;
123 u32 mux;
124 };
125
126 #define MVEBU_COMPHY_CONF(_lane, _port, _submode, _mux) \
127 { \
128 .lane = _lane, \
129 .port = _port, \
130 .mode = PHY_MODE_ETHERNET, \
131 .submode = _submode, \
132 .mux = _mux, \
133 }
134
135 static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
136 /* lane 0 */
137 MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1),
138 MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1),
139 /* lane 1 */
140 MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1),
141 MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1),
142 /* lane 2 */
143 MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1),
144 MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1),
145 MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1),
146 /* lane 3 */
147 MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2),
148 MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2),
149 /* lane 4 */
150 MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2),
151 MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2),
152 MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2),
153 MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1),
154 /* lane 5 */
155 MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1),
156 MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1),
157 };
158
159 struct mvebu_comphy_priv {
160 void __iomem *base;
161 struct regmap *regmap;
162 struct device *dev;
163 };
164
165 struct mvebu_comphy_lane {
166 struct mvebu_comphy_priv *priv;
167 unsigned id;
168 enum phy_mode mode;
169 int submode;
170 int port;
171 };
172
173 static int mvebu_comphy_get_mux(int lane, int port,
174 enum phy_mode mode, int submode)
175 {
176 int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes);
177
178 /* Unused PHY mux value is 0x0 */
179 if (mode == PHY_MODE_INVALID)
180 return 0;
181
182 for (i = 0; i < n; i++) {
183 if (mvebu_comphy_cp110_modes[i].lane == lane &&
184 mvebu_comphy_cp110_modes[i].port == port &&
185 mvebu_comphy_cp110_modes[i].mode == mode &&
186 mvebu_comphy_cp110_modes[i].submode == submode)
187 break;
188 }
189
190 if (i == n)
191 return -EINVAL;
192
193 return mvebu_comphy_cp110_modes[i].mux;
194 }
195
196 static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
197 {
198 struct mvebu_comphy_priv *priv = lane->priv;
199 u32 val;
200
201 regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);
202 val &= ~MVEBU_COMPHY_CONF1_USB_PCIE;
203 val |= MVEBU_COMPHY_CONF1_PWRUP;
204 regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);
205
206 /* Select baud rates and PLLs */
207 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
208 val &= ~(MVEBU_COMPHY_SERDES_CFG0_PU_PLL |
209 MVEBU_COMPHY_SERDES_CFG0_PU_RX |
210 MVEBU_COMPHY_SERDES_CFG0_PU_TX |
211 MVEBU_COMPHY_SERDES_CFG0_HALF_BUS |
212 MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xf) |
213 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xf));
214 if (lane->submode == PHY_INTERFACE_MODE_10GKR)
215 val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) |
216 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe);
217 else if (lane->submode == PHY_INTERFACE_MODE_2500BASEX)
218 val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x8) |
219 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x8) |
220 MVEBU_COMPHY_SERDES_CFG0_HALF_BUS;
221 else if (lane->submode == PHY_INTERFACE_MODE_SGMII)
222 val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) |
223 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) |
224 MVEBU_COMPHY_SERDES_CFG0_HALF_BUS;
225 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
226
227 /* reset */
228 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
229 val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET |
230 MVEBU_COMPHY_SERDES_CFG1_CORE_RESET |
231 MVEBU_COMPHY_SERDES_CFG1_RF_RESET);
232 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
233
234 /* de-assert reset */
235 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
236 val |= MVEBU_COMPHY_SERDES_CFG1_RESET |
237 MVEBU_COMPHY_SERDES_CFG1_CORE_RESET;
238 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
239
240 /* wait until clocks are ready */
241 mdelay(1);
242
243 /* exlicitly disable 40B, the bits isn't clear on reset */
244 regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val);
245 val &= ~MVEBU_COMPHY_CONF6_40B;
246 regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val);
247
248 /* refclk selection */
249 val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
250 val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL;
251 if (lane->submode == PHY_INTERFACE_MODE_10GKR)
252 val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE;
253 writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
254
255 /* power and pll selection */
256 val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));
257 val &= ~(MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1f) |
258 MVEBU_COMPHY_PWRPLL_PHY_MODE(0x7));
259 val |= MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1) |
260 MVEBU_COMPHY_PWRPLL_PHY_MODE(0x4);
261 writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));
262
263 val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));
264 val &= ~MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x7);
265 val |= MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x1);
266 writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));
267 }
268
269 static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane)
270 {
271 struct mvebu_comphy_priv *priv = lane->priv;
272 u32 val;
273
274 /* SERDES external config */
275 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
276 val |= MVEBU_COMPHY_SERDES_CFG0_PU_PLL |
277 MVEBU_COMPHY_SERDES_CFG0_PU_RX |
278 MVEBU_COMPHY_SERDES_CFG0_PU_TX;
279 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
280
281 /* check rx/tx pll */
282 readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),
283 val,
284 val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY |
285 MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY),
286 1000, 150000);
287 if (!(val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY |
288 MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY)))
289 return -ETIMEDOUT;
290
291 /* rx init */
292 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
293 val |= MVEBU_COMPHY_SERDES_CFG1_RX_INIT;
294 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
295
296 /* check rx */
297 readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),
298 val, val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT,
299 1000, 10000);
300 if (!(val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT))
301 return -ETIMEDOUT;
302
303 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
304 val &= ~MVEBU_COMPHY_SERDES_CFG1_RX_INIT;
305 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
306
307 return 0;
308 }
309
310 static int mvebu_comphy_set_mode_sgmii(struct phy *phy)
311 {
312 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
313 struct mvebu_comphy_priv *priv = lane->priv;
314 u32 val;
315
316 mvebu_comphy_ethernet_init_reset(lane);
317
318 val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
319 val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN;
320 val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL;
321 writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
322
323 val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id));
324 val &= ~MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN;
325 writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id));
326
327 regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);
328 val &= ~MVEBU_COMPHY_CONF1_USB_PCIE;
329 val |= MVEBU_COMPHY_CONF1_PWRUP;
330 regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);
331
332 val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
333 val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf);
334 val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x1);
335 writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
336
337 return mvebu_comphy_init_plls(lane);
338 }
339
340 static int mvebu_comphy_set_mode_10gkr(struct phy *phy)
341 {
342 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
343 struct mvebu_comphy_priv *priv = lane->priv;
344 u32 val;
345
346 mvebu_comphy_ethernet_init_reset(lane);
347
348 val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
349 val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL |
350 MVEBU_COMPHY_RX_CTRL1_CLK8T_EN;
351 writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
352
353 val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id));
354 val |= MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN;
355 writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id));
356
357 /* Speed divider */
358 val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));
359 val |= MVEBU_COMPHY_SPEED_DIV_TX_FORCE;
360 writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));
361
362 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
363 val |= MVEBU_COMPHY_SERDES_CFG2_DFE_EN;
364 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
365
366 /* DFE resolution */
367 val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
368 val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL;
369 writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
370
371 val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
372 val &= ~(MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1f) |
373 MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf));
374 val |= MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1c) |
375 MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xe);
376 writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
377
378 val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));
379 val &= ~MVEBU_COMPHY_GEN1_S2_TX_EMPH(0xf);
380 val |= MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN;
381 writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));
382
383 val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));
384 val |= MVEBU_COMPHY_TX_SLEW_RATE_EMPH(0x3) |
385 MVEBU_COMPHY_TX_SLEW_RATE_SLC(0x3f);
386 writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));
387
388 /* Impedance calibration */
389 val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));
390 val &= ~MVEBU_COMPHY_IMP_CAL_TX_EXT(0x1f);
391 val |= MVEBU_COMPHY_IMP_CAL_TX_EXT(0xe) |
392 MVEBU_COMPHY_IMP_CAL_TX_EXT_EN;
393 writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));
394
395 val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));
396 val &= ~MVEBU_COMPHY_GEN1_S5_ICP(0xf);
397 writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));
398
399 val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
400 val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) |
401 MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x7) |
402 MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(0x3) |
403 MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x3));
404 val |= MVEBU_COMPHY_GEN1_S1_RX_DFE_EN |
405 MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x2) |
406 MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x2) |
407 MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x1) |
408 MVEBU_COMPHY_GEN1_S1_RX_DIV(0x3);
409 writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
410
411 val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));
412 val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL);
413 writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));
414
415 val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
416 val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3);
417 val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1);
418 writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
419
420 val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));
421 val |= MVEBU_COMPHY_GEN1_S3_FBCK_SEL;
422 writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));
423
424 /* rx training timer */
425 val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id));
426 val &= ~MVEBU_COMPHY_TRAINING5_RX_TIMER(0x3ff);
427 val |= MVEBU_COMPHY_TRAINING5_RX_TIMER(0x13);
428 writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id));
429
430 /* tx train peak to peak hold */
431 val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id));
432 val |= MVEBU_COMPHY_TRAINING0_P2P_HOLD;
433 writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id));
434
435 val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));
436 val &= ~MVEBU_COMPHY_TX_PRESET_INDEX(0xf);
437 val |= MVEBU_COMPHY_TX_PRESET_INDEX(0x2); /* preset coeff */
438 writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));
439
440 val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));
441 val &= ~MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN;
442 writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));
443
444 val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));
445 val |= MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN |
446 MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11;
447 writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));
448
449 val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));
450 val &= ~MVEBU_COMPHY_FRAME_DETECT0_PATN(0x1ff);
451 val |= MVEBU_COMPHY_FRAME_DETECT0_PATN(0x88);
452 writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));
453
454 val = readl(priv->base + MVEBU_COMPHY_DME(lane->id));
455 val |= MVEBU_COMPHY_DME_ETH_MODE;
456 writel(val, priv->base + MVEBU_COMPHY_DME(lane->id));
457
458 val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));
459 val |= MVEBU_COMPHY_VDD_CAL0_CONT_MODE;
460 writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));
461
462 val = readl(priv->base + MVEBU_SP_CALIB(lane->id));
463 val &= ~MVEBU_SP_CALIB_SAMPLER(0x3);
464 val |= MVEBU_SP_CALIB_SAMPLER(0x3) |
465 MVEBU_SP_CALIB_SAMPLER_EN;
466 writel(val, priv->base + MVEBU_SP_CALIB(lane->id));
467 val &= ~MVEBU_SP_CALIB_SAMPLER_EN;
468 writel(val, priv->base + MVEBU_SP_CALIB(lane->id));
469
470 /* External rx regulator */
471 val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));
472 val &= ~MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1f);
473 val |= MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1a);
474 writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));
475
476 return mvebu_comphy_init_plls(lane);
477 }
478
479 static int mvebu_comphy_power_on(struct phy *phy)
480 {
481 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
482 struct mvebu_comphy_priv *priv = lane->priv;
483 int ret, mux;
484 u32 val;
485
486 mux = mvebu_comphy_get_mux(lane->id, lane->port,
487 lane->mode, lane->submode);
488 if (mux < 0)
489 return -ENOTSUPP;
490
491 regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);
492 val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
493 regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);
494
495 regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);
496 val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
497 val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id);
498 regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);
499
500 switch (lane->submode) {
501 case PHY_INTERFACE_MODE_SGMII:
502 case PHY_INTERFACE_MODE_2500BASEX:
503 ret = mvebu_comphy_set_mode_sgmii(phy);
504 break;
505 case PHY_INTERFACE_MODE_10GKR:
506 ret = mvebu_comphy_set_mode_10gkr(phy);
507 break;
508 default:
509 return -ENOTSUPP;
510 }
511
512 /* digital reset */
513 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
514 val |= MVEBU_COMPHY_SERDES_CFG1_RF_RESET;
515 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
516
517 return ret;
518 }
519
520 static int mvebu_comphy_set_mode(struct phy *phy,
521 enum phy_mode mode, int submode)
522 {
523 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
524
525 if (mode != PHY_MODE_ETHERNET)
526 return -EINVAL;
527
528 if (submode == PHY_INTERFACE_MODE_1000BASEX)
529 submode = PHY_INTERFACE_MODE_SGMII;
530
531 if (mvebu_comphy_get_mux(lane->id, lane->port, mode, submode) < 0)
532 return -EINVAL;
533
534 lane->mode = mode;
535 lane->submode = submode;
536 return 0;
537 }
538
539 static int mvebu_comphy_power_off(struct phy *phy)
540 {
541 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
542 struct mvebu_comphy_priv *priv = lane->priv;
543 u32 val;
544
545 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
546 val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET |
547 MVEBU_COMPHY_SERDES_CFG1_CORE_RESET |
548 MVEBU_COMPHY_SERDES_CFG1_RF_RESET);
549 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
550
551 regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);
552 val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
553 regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);
554
555 regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);
556 val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
557 regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);
558
559 return 0;
560 }
561
562 static const struct phy_ops mvebu_comphy_ops = {
563 .power_on = mvebu_comphy_power_on,
564 .power_off = mvebu_comphy_power_off,
565 .set_mode = mvebu_comphy_set_mode,
566 .owner = THIS_MODULE,
567 };
568
569 static struct phy *mvebu_comphy_xlate(struct device *dev,
570 struct of_phandle_args *args)
571 {
572 struct mvebu_comphy_lane *lane;
573 struct phy *phy;
574
575 if (WARN_ON(args->args[0] >= MVEBU_COMPHY_PORTS))
576 return ERR_PTR(-EINVAL);
577
578 phy = of_phy_simple_xlate(dev, args);
579 if (IS_ERR(phy))
580 return phy;
581
582 lane = phy_get_drvdata(phy);
583 lane->port = args->args[0];
584
585 return phy;
586 }
587
588 static int mvebu_comphy_probe(struct platform_device *pdev)
589 {
590 struct mvebu_comphy_priv *priv;
591 struct phy_provider *provider;
592 struct device_node *child;
593 struct resource *res;
594
595 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
596 if (!priv)
597 return -ENOMEM;
598
599 priv->dev = &pdev->dev;
600 priv->regmap =
601 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
602 "marvell,system-controller");
603 if (IS_ERR(priv->regmap))
604 return PTR_ERR(priv->regmap);
605 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
606 priv->base = devm_ioremap_resource(&pdev->dev, res);
607 if (IS_ERR(priv->base))
608 return PTR_ERR(priv->base);
609
610 for_each_available_child_of_node(pdev->dev.of_node, child) {
611 struct mvebu_comphy_lane *lane;
612 struct phy *phy;
613 int ret;
614 u32 val;
615
616 ret = of_property_read_u32(child, "reg", &val);
617 if (ret < 0) {
618 dev_err(&pdev->dev, "missing 'reg' property (%d)\n",
619 ret);
620 continue;
621 }
622
623 if (val >= MVEBU_COMPHY_LANES) {
624 dev_err(&pdev->dev, "invalid 'reg' property\n");
625 continue;
626 }
627
628 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
629 if (!lane)
630 return -ENOMEM;
631
632 phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops);
633 if (IS_ERR(phy))
634 return PTR_ERR(phy);
635
636 lane->priv = priv;
637 lane->mode = PHY_MODE_INVALID;
638 lane->id = val;
639 lane->port = -1;
640 phy_set_drvdata(phy, lane);
641
642 /*
643 * Once all modes are supported in this driver we should call
644 * mvebu_comphy_power_off(phy) here to avoid relying on the
645 * bootloader/firmware configuration.
646 */
647 }
648
649 dev_set_drvdata(&pdev->dev, priv);
650 provider = devm_of_phy_provider_register(&pdev->dev,
651 mvebu_comphy_xlate);
652 return PTR_ERR_OR_ZERO(provider);
653 }
654
655 static const struct of_device_id mvebu_comphy_of_match_table[] = {
656 { .compatible = "marvell,comphy-cp110" },
657 { },
658 };
659 MODULE_DEVICE_TABLE(of, mvebu_comphy_of_match_table);
660
661 static struct platform_driver mvebu_comphy_driver = {
662 .probe = mvebu_comphy_probe,
663 .driver = {
664 .name = "mvebu-comphy",
665 .of_match_table = mvebu_comphy_of_match_table,
666 },
667 };
668 module_platform_driver(mvebu_comphy_driver);
669
670 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
671 MODULE_DESCRIPTION("Common PHY driver for mvebu SoCs");
672 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support