drivers/phy/qualcomm/phy-qcom-ufs-i.h

   1 /*
   2  * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #ifndef UFS_QCOM_PHY_I_H_
  16 #define UFS_QCOM_PHY_I_H_
  17
  18 #include <linux/module.h>
  19 #include <linux/clk.h>
  20 #include <linux/phy/phy.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/reset.h>
  23 #include <linux/slab.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/io.h>
  26 #include <linux/delay.h>
  27 #include <linux/iopoll.h>
  28
  29 #define UFS_QCOM_PHY_CAL_ENTRY(reg, val)        \
  30         {                               \
  31                 .reg_offset = reg,      \
  32                 .cfg_value = val,       \
  33         }
  34
  35 #define UFS_QCOM_PHY_NAME_LEN   30
  36
  37 enum {
  38         MASK_SERDES_START       = 0x1,
  39         MASK_PCS_READY          = 0x1,
  40 };
  41
  42 enum {
  43         OFFSET_SERDES_START     = 0x0,
  44 };
  45
  46 struct ufs_qcom_phy_stored_attributes {
  47         u32 att;
  48         u32 value;
  49 };
  50
  51
  52 struct ufs_qcom_phy_calibration {
  53         u32 reg_offset;
  54         u32 cfg_value;
  55 };
  56
  57 struct ufs_qcom_phy_vreg {
  58         const char *name;
  59         struct regulator *reg;
  60         int max_uA;
  61         int min_uV;
  62         int max_uV;
  63         bool enabled;
  64 };
  65
  66 struct ufs_qcom_phy {
  67         struct list_head list;
  68         struct device *dev;
  69         void __iomem *mmio;
  70         void __iomem *dev_ref_clk_ctrl_mmio;
  71         struct clk *tx_iface_clk;
  72         struct clk *rx_iface_clk;
  73         bool is_iface_clk_enabled;
  74         struct clk *ref_clk_src;
  75         struct clk *ref_clk_parent;
  76         struct clk *ref_clk;
  77         bool is_ref_clk_enabled;
  78         bool is_dev_ref_clk_enabled;
  79         struct ufs_qcom_phy_vreg vdda_pll;
  80         struct ufs_qcom_phy_vreg vdda_phy;
  81         struct ufs_qcom_phy_vreg vddp_ref_clk;
  82         unsigned int quirks;
  83
  84         /*
  85         * If UFS link is put into Hibern8 and if UFS PHY analog hardware is
  86         * power collapsed (by clearing UFS_PHY_POWER_DOWN_CONTROL), Hibern8
  87         * exit might fail even after powering on UFS PHY analog hardware.
  88         * Enabling this quirk will help to solve above issue by doing
  89         * custom PHY settings just before PHY analog power collapse.
  90         */
  91         #define UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE  BIT(0)
  92
  93         u8 host_ctrl_rev_major;
  94         u16 host_ctrl_rev_minor;
  95         u16 host_ctrl_rev_step;
  96
  97         char name[UFS_QCOM_PHY_NAME_LEN];
  98         struct ufs_qcom_phy_calibration *cached_regs;
  99         int cached_regs_table_size;
 100         struct ufs_qcom_phy_specific_ops *phy_spec_ops;
 101
 102         enum phy_mode mode;
 103         struct reset_control *ufs_reset;
 104 };
 105
 106 /**
 107  * struct ufs_qcom_phy_specific_ops - set of pointers to functions which have a
 108  * specific implementation per phy. Each UFS phy, should implement
 109  * those functions according to its spec and requirements
 110  * @start_serdes: pointer to a function that starts the serdes
 111  * @is_physical_coding_sublayer_ready: pointer to a function that
 112  * checks pcs readiness. returns 0 for success and non-zero for error.
 113  * @set_tx_lane_enable: pointer to a function that enable tx lanes
 114  * @power_control: pointer to a function that controls analog rail of phy
 115  * and writes to QSERDES_RX_SIGDET_CNTRL attribute
 116  */
 117 struct ufs_qcom_phy_specific_ops {
 118         int (*calibrate)(struct ufs_qcom_phy *ufs_qcom_phy, bool is_rate_B);
 119         void (*start_serdes)(struct ufs_qcom_phy *phy);
 120         int (*is_physical_coding_sublayer_ready)(struct ufs_qcom_phy *phy);
 121         void (*set_tx_lane_enable)(struct ufs_qcom_phy *phy, u32 val);
 122         void (*power_control)(struct ufs_qcom_phy *phy, bool val);
 123 };
 124
 125 struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy);
 126 int ufs_qcom_phy_power_on(struct phy *generic_phy);
 127 int ufs_qcom_phy_power_off(struct phy *generic_phy);
 128 int ufs_qcom_phy_init_clks(struct ufs_qcom_phy *phy_common);
 129 int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy *phy_common);
 130 int ufs_qcom_phy_remove(struct phy *generic_phy,
 131                        struct ufs_qcom_phy *ufs_qcom_phy);
 132 struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
 133                         struct ufs_qcom_phy *common_cfg,
 134                         const struct phy_ops *ufs_qcom_phy_gen_ops,
 135                         struct ufs_qcom_phy_specific_ops *phy_spec_ops);
 136 int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
 137                         struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A,
 138                         struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B,
 139                         bool is_rate_B);
 140 #endif