drivers/irqchip/irq-gic-common.c

   1 /*
   2  * Copyright (C) 2002 ARM Limited, All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqchip/arm-gic.h>
  21
  22 #include "irq-gic-common.h"
  23
  24 static const struct gic_kvm_info *gic_kvm_info;
  25
  26 const struct gic_kvm_info *gic_get_kvm_info(void)
  27 {
  28         return gic_kvm_info;
  29 }
  30
  31 void gic_set_kvm_info(const struct gic_kvm_info *info)
  32 {
  33         BUG_ON(gic_kvm_info != NULL);
  34         gic_kvm_info = info;
  35 }
  36
  37 void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
  38                 void *data)
  39 {
  40         for (; quirks->desc; quirks++) {
  41                 if (quirks->iidr != (quirks->mask & iidr))
  42                         continue;
  43                 if (quirks->init(data))
  44                         pr_info("GIC: enabling workaround for %s\n",
  45                                 quirks->desc);
  46         }
  47 }
  48
  49 int gic_configure_irq(unsigned int irq, unsigned int type,
  50                        void __iomem *base, void (*sync_access)(void))
  51 {
  52         u32 confmask = 0x2 << ((irq % 16) * 2);
  53         u32 confoff = (irq / 16) * 4;
  54         u32 val, oldval;
  55         int ret = 0;
  56
  57         /*
  58          * Read current configuration register, and insert the config
  59          * for "irq", depending on "type".
  60          */
  61         val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
  62         if (type & IRQ_TYPE_LEVEL_MASK)
  63                 val &= ~confmask;
  64         else if (type & IRQ_TYPE_EDGE_BOTH)
  65                 val |= confmask;
  66
  67         /* If the current configuration is the same, then we are done */
  68         if (val == oldval)
  69                 return 0;
  70
  71         /*
  72          * Write back the new configuration, and possibly re-enable
  73          * the interrupt. If we fail to write a new configuration for
  74          * an SPI then WARN and return an error. If we fail to write the
  75          * configuration for a PPI this is most likely because the GIC
  76          * does not allow us to set the configuration or we are in a
  77          * non-secure mode, and hence it may not be catastrophic.
  78          */
  79         writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
  80         if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val) {
  81                 if (WARN_ON(irq >= 32))
  82                         ret = -EINVAL;
  83                 else
  84                         pr_warn("GIC: PPI%d is secure or misconfigured\n",
  85                                 irq - 16);
  86         }
  87
  88         if (sync_access)
  89                 sync_access();
  90
  91         return ret;
  92 }
  93
  94 void gic_dist_config(void __iomem *base, int gic_irqs,
  95                      void (*sync_access)(void))
  96 {
  97         unsigned int i;
  98
  99         /*
 100          * Set all global interrupts to be level triggered, active low.
 101          */
 102         for (i = 32; i < gic_irqs; i += 16)
 103                 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
 104                                         base + GIC_DIST_CONFIG + i / 4);
 105
 106         /*
 107          * Set priority on all global interrupts.
 108          */
 109         for (i = 32; i < gic_irqs; i += 4)
 110                 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
 111
 112         /*
 113          * Deactivate and disable all SPIs. Leave the PPI and SGIs
 114          * alone as they are in the redistributor registers on GICv3.
 115          */
 116         for (i = 32; i < gic_irqs; i += 32) {
 117                 writel_relaxed(GICD_INT_EN_CLR_X32,
 118                                base + GIC_DIST_ACTIVE_CLEAR + i / 8);
 119                 writel_relaxed(GICD_INT_EN_CLR_X32,
 120                                base + GIC_DIST_ENABLE_CLEAR + i / 8);
 121         }
 122
 123         if (sync_access)
 124                 sync_access();
 125 }
 126
 127 void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
 128 {
 129         int i;
 130
 131         /*
 132          * Deal with the banked PPI and SGI interrupts - disable all
 133          * PPI interrupts, ensure all SGI interrupts are enabled.
 134          * Make sure everything is deactivated.
 135          */
 136         writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR);
 137         writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);
 138         writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);
 139
 140         /*
 141          * Set priority on PPI and SGI interrupts
 142          */
 143         for (i = 0; i < 32; i += 4)
 144                 writel_relaxed(GICD_INT_DEF_PRI_X4,
 145                                         base + GIC_DIST_PRI + i * 4 / 4);
 146
 147         if (sync_access)
 148                 sync_access();
 149 }