arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

   1 /*
   2  * Support for MicroBlaze PVR (processor version register)
   3  *
   4  * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
   5  * Copyright (C) 2007-2009 PetaLogix
   6  * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License. See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12
  13 #include <linux/init.h>
  14 #include <linux/string.h>
  15 #include <asm/pvr.h>
  16 #include <asm/cpuinfo.h>
  17
  18 /*
  19  * Helper macro to map between fields in our struct cpuinfo, and
  20  * the PVR macros in pvr.h.
  21  */
  22
  23 #define CI(c, p) { ci->c = PVR_##p(pvr); }
  24 #define err_printk(x) \
  25         early_printk("ERROR: Microblaze " x "-different for PVR and DTS\n");
  26
  27 void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
  28 {
  29         struct pvr_s pvr;
  30         int temp; /* for saving temp value */
  31         get_pvr(&pvr);
  32
  33         CI(ver_code, VERSION);
  34         if (!ci->ver_code) {
  35                 printk(KERN_ERR "ERROR: MB has broken PVR regs "
  36                                                 "-> use DTS setting\n");
  37                 return;
  38         }
  39
  40         temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) |\
  41                 PVR_USE_PCMP_INSTR(pvr) | PVR_USE_DIV(pvr);
  42         if (ci->use_instr != temp)
  43                 err_printk("BARREL, MSR, PCMP or DIV");
  44         ci->use_instr = temp;
  45
  46         temp = PVR_USE_HW_MUL(pvr) | PVR_USE_MUL64(pvr);
  47         if (ci->use_mult != temp)
  48                 err_printk("HW_MUL");
  49         ci->use_mult = temp;
  50
  51         temp = PVR_USE_FPU(pvr) | PVR_USE_FPU2(pvr);
  52         if (ci->use_fpu != temp)
  53                 err_printk("HW_FPU");
  54         ci->use_fpu = temp;
  55
  56         ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) |\
  57                         PVR_UNALIGNED_EXCEPTION(pvr) |\
  58                         PVR_ILL_OPCODE_EXCEPTION(pvr) |\
  59                         PVR_IOPB_BUS_EXCEPTION(pvr) |\
  60                         PVR_DOPB_BUS_EXCEPTION(pvr) |\
  61                         PVR_DIV_ZERO_EXCEPTION(pvr) |\
  62                         PVR_FPU_EXCEPTION(pvr) |\
  63                         PVR_FSL_EXCEPTION(pvr);
  64
  65         CI(pvr_user1, USER1);
  66         CI(pvr_user2, USER2);
  67
  68         CI(mmu, USE_MMU);
  69
  70         CI(use_icache, USE_ICACHE);
  71         CI(icache_tagbits, ICACHE_ADDR_TAG_BITS);
  72         CI(icache_write, ICACHE_ALLOW_WR);
  73         CI(icache_line, ICACHE_LINE_LEN);
  74         CI(icache_size, ICACHE_BYTE_SIZE);
  75         CI(icache_base, ICACHE_BASEADDR);
  76         CI(icache_high, ICACHE_HIGHADDR);
  77
  78         CI(use_dcache, USE_DCACHE);
  79         CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS);
  80         CI(dcache_write, DCACHE_ALLOW_WR);
  81         CI(dcache_line, DCACHE_LINE_LEN);
  82         CI(dcache_size, DCACHE_BYTE_SIZE);
  83         CI(dcache_base, DCACHE_BASEADDR);
  84         CI(dcache_high, DCACHE_HIGHADDR);
  85
  86         CI(use_dopb, D_OPB);
  87         CI(use_iopb, I_OPB);
  88         CI(use_dlmb, D_LMB);
  89         CI(use_ilmb, I_LMB);
  90         CI(num_fsl, FSL_LINKS);
  91
  92         CI(irq_edge, INTERRUPT_IS_EDGE);
  93         CI(irq_positive, EDGE_IS_POSITIVE);
  94
  95         CI(area_optimised, AREA_OPTIMISED);
  96
  97         CI(hw_debug, DEBUG_ENABLED);
  98         CI(num_pc_brk, NUMBER_OF_PC_BRK);
  99         CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK);
 100         CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK);
 101
 102         CI(fpga_family_code, TARGET_FAMILY);
 103
 104         /* take timebase-frequency from DTS */
 105         ci->cpu_clock_freq = fcpu(cpu, "timebase-frequency");
 106 }