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drm/i915: Move non-phys cursors into the GTT
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_display.c
blob04e1bb499ff8019bc2e1f9d9d6864bdb673b8448
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "drm_dp_helper.h"
37
38 #include "drm_crtc_helper.h"
39
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41
42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
43 static void intel_update_watermarks(struct drm_device *dev);
44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
45
46 typedef struct {
47 /* given values */
48 int n;
49 int m1, m2;
50 int p1, p2;
51 /* derived values */
52 int dot;
53 int vco;
54 int m;
55 int p;
56 } intel_clock_t;
57
58 typedef struct {
59 int min, max;
60 } intel_range_t;
61
62 typedef struct {
63 int dot_limit;
64 int p2_slow, p2_fast;
65 } intel_p2_t;
66
67 #define INTEL_P2_NUM 2
68 typedef struct intel_limit intel_limit_t;
69 struct intel_limit {
70 intel_range_t dot, vco, n, m, m1, m2, p, p1;
71 intel_p2_t p2;
72 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
73 int, int, intel_clock_t *);
74 };
75
76 #define I8XX_DOT_MIN 25000
77 #define I8XX_DOT_MAX 350000
78 #define I8XX_VCO_MIN 930000
79 #define I8XX_VCO_MAX 1400000
80 #define I8XX_N_MIN 3
81 #define I8XX_N_MAX 16
82 #define I8XX_M_MIN 96
83 #define I8XX_M_MAX 140
84 #define I8XX_M1_MIN 18
85 #define I8XX_M1_MAX 26
86 #define I8XX_M2_MIN 6
87 #define I8XX_M2_MAX 16
88 #define I8XX_P_MIN 4
89 #define I8XX_P_MAX 128
90 #define I8XX_P1_MIN 2
91 #define I8XX_P1_MAX 33
92 #define I8XX_P1_LVDS_MIN 1
93 #define I8XX_P1_LVDS_MAX 6
94 #define I8XX_P2_SLOW 4
95 #define I8XX_P2_FAST 2
96 #define I8XX_P2_LVDS_SLOW 14
97 #define I8XX_P2_LVDS_FAST 7
98 #define I8XX_P2_SLOW_LIMIT 165000
99
100 #define I9XX_DOT_MIN 20000
101 #define I9XX_DOT_MAX 400000
102 #define I9XX_VCO_MIN 1400000
103 #define I9XX_VCO_MAX 2800000
104 #define PINEVIEW_VCO_MIN 1700000
105 #define PINEVIEW_VCO_MAX 3500000
106 #define I9XX_N_MIN 1
107 #define I9XX_N_MAX 6
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN 3
110 #define PINEVIEW_N_MAX 6
111 #define I9XX_M_MIN 70
112 #define I9XX_M_MAX 120
113 #define PINEVIEW_M_MIN 2
114 #define PINEVIEW_M_MAX 256
115 #define I9XX_M1_MIN 10
116 #define I9XX_M1_MAX 22
117 #define I9XX_M2_MIN 5
118 #define I9XX_M2_MAX 9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN 0
121 #define PINEVIEW_M1_MAX 0
122 #define PINEVIEW_M2_MIN 0
123 #define PINEVIEW_M2_MAX 254
124 #define I9XX_P_SDVO_DAC_MIN 5
125 #define I9XX_P_SDVO_DAC_MAX 80
126 #define I9XX_P_LVDS_MIN 7
127 #define I9XX_P_LVDS_MAX 98
128 #define PINEVIEW_P_LVDS_MIN 7
129 #define PINEVIEW_P_LVDS_MAX 112
130 #define I9XX_P1_MIN 1
131 #define I9XX_P1_MAX 8
132 #define I9XX_P2_SDVO_DAC_SLOW 10
133 #define I9XX_P2_SDVO_DAC_FAST 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
135 #define I9XX_P2_LVDS_SLOW 14
136 #define I9XX_P2_LVDS_FAST 7
137 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
138
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN 25000
141 #define G4X_DOT_SDVO_MAX 270000
142 #define G4X_VCO_MIN 1750000
143 #define G4X_VCO_MAX 3500000
144 #define G4X_N_SDVO_MIN 1
145 #define G4X_N_SDVO_MAX 4
146 #define G4X_M_SDVO_MIN 104
147 #define G4X_M_SDVO_MAX 138
148 #define G4X_M1_SDVO_MIN 17
149 #define G4X_M1_SDVO_MAX 23
150 #define G4X_M2_SDVO_MIN 5
151 #define G4X_M2_SDVO_MAX 11
152 #define G4X_P_SDVO_MIN 10
153 #define G4X_P_SDVO_MAX 30
154 #define G4X_P1_SDVO_MIN 1
155 #define G4X_P1_SDVO_MAX 3
156 #define G4X_P2_SDVO_SLOW 10
157 #define G4X_P2_SDVO_FAST 10
158 #define G4X_P2_SDVO_LIMIT 270000
159
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN 22000
162 #define G4X_DOT_HDMI_DAC_MAX 400000
163 #define G4X_N_HDMI_DAC_MIN 1
164 #define G4X_N_HDMI_DAC_MAX 4
165 #define G4X_M_HDMI_DAC_MIN 104
166 #define G4X_M_HDMI_DAC_MAX 138
167 #define G4X_M1_HDMI_DAC_MIN 16
168 #define G4X_M1_HDMI_DAC_MAX 23
169 #define G4X_M2_HDMI_DAC_MIN 5
170 #define G4X_M2_HDMI_DAC_MAX 11
171 #define G4X_P_HDMI_DAC_MIN 5
172 #define G4X_P_HDMI_DAC_MAX 80
173 #define G4X_P1_HDMI_DAC_MIN 1
174 #define G4X_P1_HDMI_DAC_MAX 8
175 #define G4X_P2_HDMI_DAC_SLOW 10
176 #define G4X_P2_HDMI_DAC_FAST 5
177 #define G4X_P2_HDMI_DAC_LIMIT 165000
178
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
197
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
216
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN 161670
219 #define G4X_DOT_DISPLAY_PORT_MAX 227000
220 #define G4X_N_DISPLAY_PORT_MIN 1
221 #define G4X_N_DISPLAY_PORT_MAX 2
222 #define G4X_M_DISPLAY_PORT_MIN 97
223 #define G4X_M_DISPLAY_PORT_MAX 108
224 #define G4X_M1_DISPLAY_PORT_MIN 0x10
225 #define G4X_M1_DISPLAY_PORT_MAX 0x12
226 #define G4X_M2_DISPLAY_PORT_MIN 0x05
227 #define G4X_M2_DISPLAY_PORT_MAX 0x06
228 #define G4X_P_DISPLAY_PORT_MIN 10
229 #define G4X_P_DISPLAY_PORT_MAX 20
230 #define G4X_P1_DISPLAY_PORT_MIN 1
231 #define G4X_P1_DISPLAY_PORT_MAX 2
232 #define G4X_P2_DISPLAY_PORT_SLOW 10
233 #define G4X_P2_DISPLAY_PORT_FAST 10
234 #define G4X_P2_DISPLAY_PORT_LIMIT 0
235
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238 N/M1/M2, so here the range value for them is (actual_value-2).
239 */
240 #define IRONLAKE_DOT_MIN 25000
241 #define IRONLAKE_DOT_MAX 350000
242 #define IRONLAKE_VCO_MIN 1760000
243 #define IRONLAKE_VCO_MAX 3510000
244 #define IRONLAKE_M1_MIN 12
245 #define IRONLAKE_M1_MAX 22
246 #define IRONLAKE_M2_MIN 5
247 #define IRONLAKE_M2_MAX 9
248 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
249
250 /* We have parameter ranges for different type of outputs. */
251
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN 1
254 #define IRONLAKE_DAC_N_MAX 5
255 #define IRONLAKE_DAC_M_MIN 79
256 #define IRONLAKE_DAC_M_MAX 127
257 #define IRONLAKE_DAC_P_MIN 5
258 #define IRONLAKE_DAC_P_MAX 80
259 #define IRONLAKE_DAC_P1_MIN 1
260 #define IRONLAKE_DAC_P1_MAX 8
261 #define IRONLAKE_DAC_P2_SLOW 10
262 #define IRONLAKE_DAC_P2_FAST 5
263
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN 1
266 #define IRONLAKE_LVDS_S_N_MAX 3
267 #define IRONLAKE_LVDS_S_M_MIN 79
268 #define IRONLAKE_LVDS_S_M_MAX 118
269 #define IRONLAKE_LVDS_S_P_MIN 28
270 #define IRONLAKE_LVDS_S_P_MAX 112
271 #define IRONLAKE_LVDS_S_P1_MIN 2
272 #define IRONLAKE_LVDS_S_P1_MAX 8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
275
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN 1
278 #define IRONLAKE_LVDS_D_N_MAX 3
279 #define IRONLAKE_LVDS_D_M_MIN 79
280 #define IRONLAKE_LVDS_D_M_MAX 127
281 #define IRONLAKE_LVDS_D_P_MIN 14
282 #define IRONLAKE_LVDS_D_P_MAX 56
283 #define IRONLAKE_LVDS_D_P1_MIN 2
284 #define IRONLAKE_LVDS_D_P1_MAX 8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
287
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
299
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
311
312 /* DisplayPort */
313 #define IRONLAKE_DP_N_MIN 1
314 #define IRONLAKE_DP_N_MAX 2
315 #define IRONLAKE_DP_M_MIN 81
316 #define IRONLAKE_DP_M_MAX 90
317 #define IRONLAKE_DP_P_MIN 10
318 #define IRONLAKE_DP_P_MAX 20
319 #define IRONLAKE_DP_P2_FAST 10
320 #define IRONLAKE_DP_P2_SLOW 10
321 #define IRONLAKE_DP_P2_LIMIT 0
322 #define IRONLAKE_DP_P1_MIN 1
323 #define IRONLAKE_DP_P1_MAX 2
324
325 static bool
326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
327 int target, int refclk, intel_clock_t *best_clock);
328 static bool
329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
330 int target, int refclk, intel_clock_t *best_clock);
331
332 static bool
333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
334 int target, int refclk, intel_clock_t *best_clock);
335 static bool
336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
337 int target, int refclk, intel_clock_t *best_clock);
338
339 static const intel_limit_t intel_limits_i8xx_dvo = {
340 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
341 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
342 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
343 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
344 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
345 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
346 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
347 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
348 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
349 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
350 .find_pll = intel_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_i8xx_lvds = {
354 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
355 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
356 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
357 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
358 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
359 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
360 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
361 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
362 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
363 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
364 .find_pll = intel_find_best_PLL,
365 };
366
367 static const intel_limit_t intel_limits_i9xx_sdvo = {
368 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
369 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
370 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
371 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
372 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
373 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
374 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
375 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
376 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
377 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
378 .find_pll = intel_find_best_PLL,
379 };
380
381 static const intel_limit_t intel_limits_i9xx_lvds = {
382 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
383 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
384 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
385 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
386 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
387 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
388 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
389 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
390 /* The single-channel range is 25-112Mhz, and dual-channel
391 * is 80-224Mhz. Prefer single channel as much as possible.
392 */
393 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
394 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
395 .find_pll = intel_find_best_PLL,
396 };
397
398 /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo = {
400 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
401 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
402 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
403 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
404 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
405 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
406 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
407 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
408 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
409 .p2_slow = G4X_P2_SDVO_SLOW,
410 .p2_fast = G4X_P2_SDVO_FAST
411 },
412 .find_pll = intel_g4x_find_best_PLL,
413 };
414
415 static const intel_limit_t intel_limits_g4x_hdmi = {
416 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
419 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
420 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
421 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
422 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
423 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
424 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
425 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
426 .p2_fast = G4X_P2_HDMI_DAC_FAST
427 },
428 .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
432 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
433 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
434 .vco = { .min = G4X_VCO_MIN,
435 .max = G4X_VCO_MAX },
436 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
437 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
438 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
440 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
441 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
442 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
444 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
446 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
448 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
449 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
450 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
451 },
452 .find_pll = intel_g4x_find_best_PLL,
453 };
454
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
456 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
457 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
458 .vco = { .min = G4X_VCO_MIN,
459 .max = G4X_VCO_MAX },
460 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
461 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
462 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
464 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
465 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
466 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
468 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
470 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
472 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
473 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
474 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
475 },
476 .find_pll = intel_g4x_find_best_PLL,
477 };
478
479 static const intel_limit_t intel_limits_g4x_display_port = {
480 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
481 .max = G4X_DOT_DISPLAY_PORT_MAX },
482 .vco = { .min = G4X_VCO_MIN,
483 .max = G4X_VCO_MAX},
484 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
485 .max = G4X_N_DISPLAY_PORT_MAX },
486 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
487 .max = G4X_M_DISPLAY_PORT_MAX },
488 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
489 .max = G4X_M1_DISPLAY_PORT_MAX },
490 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
491 .max = G4X_M2_DISPLAY_PORT_MAX },
492 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
493 .max = G4X_P_DISPLAY_PORT_MAX },
494 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
495 .max = G4X_P1_DISPLAY_PORT_MAX},
496 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
497 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
498 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
499 .find_pll = intel_find_pll_g4x_dp,
500 };
501
502 static const intel_limit_t intel_limits_pineview_sdvo = {
503 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
504 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
505 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
506 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
507 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
508 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
509 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
510 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
511 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
512 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
513 .find_pll = intel_find_best_PLL,
514 };
515
516 static const intel_limit_t intel_limits_pineview_lvds = {
517 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
518 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
519 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
520 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
521 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
522 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
523 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
524 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
525 /* Pineview only supports single-channel mode. */
526 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
527 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
528 .find_pll = intel_find_best_PLL,
529 };
530
531 static const intel_limit_t intel_limits_ironlake_dac = {
532 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
533 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
534 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
535 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
536 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
537 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
538 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
539 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
540 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
541 .p2_slow = IRONLAKE_DAC_P2_SLOW,
542 .p2_fast = IRONLAKE_DAC_P2_FAST },
543 .find_pll = intel_g4x_find_best_PLL,
544 };
545
546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
547 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
548 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
549 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
550 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
551 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
552 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
553 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
554 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
555 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
556 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
557 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
558 .find_pll = intel_g4x_find_best_PLL,
559 };
560
561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
562 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
563 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
564 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
565 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
566 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
567 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
568 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
569 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
570 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
571 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
572 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
573 .find_pll = intel_g4x_find_best_PLL,
574 };
575
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
577 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
578 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
579 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
580 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
581 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
582 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
583 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
584 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
585 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
586 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
587 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
588 .find_pll = intel_g4x_find_best_PLL,
589 };
590
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
592 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
593 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
594 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
595 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
596 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
597 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
598 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
599 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
600 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
601 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
602 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
603 .find_pll = intel_g4x_find_best_PLL,
604 };
605
606 static const intel_limit_t intel_limits_ironlake_display_port = {
607 .dot = { .min = IRONLAKE_DOT_MIN,
608 .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN,
610 .max = IRONLAKE_VCO_MAX},
611 .n = { .min = IRONLAKE_DP_N_MIN,
612 .max = IRONLAKE_DP_N_MAX },
613 .m = { .min = IRONLAKE_DP_M_MIN,
614 .max = IRONLAKE_DP_M_MAX },
615 .m1 = { .min = IRONLAKE_M1_MIN,
616 .max = IRONLAKE_M1_MAX },
617 .m2 = { .min = IRONLAKE_M2_MIN,
618 .max = IRONLAKE_M2_MAX },
619 .p = { .min = IRONLAKE_DP_P_MIN,
620 .max = IRONLAKE_DP_P_MAX },
621 .p1 = { .min = IRONLAKE_DP_P1_MIN,
622 .max = IRONLAKE_DP_P1_MAX},
623 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
624 .p2_slow = IRONLAKE_DP_P2_SLOW,
625 .p2_fast = IRONLAKE_DP_P2_FAST },
626 .find_pll = intel_find_pll_ironlake_dp,
627 };
628
629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
630 {
631 struct drm_device *dev = crtc->dev;
632 struct drm_i915_private *dev_priv = dev->dev_private;
633 const intel_limit_t *limit;
634 int refclk = 120;
635
636 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
638 refclk = 100;
639
640 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
641 LVDS_CLKB_POWER_UP) {
642 /* LVDS dual channel */
643 if (refclk == 100)
644 limit = &intel_limits_ironlake_dual_lvds_100m;
645 else
646 limit = &intel_limits_ironlake_dual_lvds;
647 } else {
648 if (refclk == 100)
649 limit = &intel_limits_ironlake_single_lvds_100m;
650 else
651 limit = &intel_limits_ironlake_single_lvds;
652 }
653 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
654 HAS_eDP)
655 limit = &intel_limits_ironlake_display_port;
656 else
657 limit = &intel_limits_ironlake_dac;
658
659 return limit;
660 }
661
662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
663 {
664 struct drm_device *dev = crtc->dev;
665 struct drm_i915_private *dev_priv = dev->dev_private;
666 const intel_limit_t *limit;
667
668 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
669 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
670 LVDS_CLKB_POWER_UP)
671 /* LVDS with dual channel */
672 limit = &intel_limits_g4x_dual_channel_lvds;
673 else
674 /* LVDS with dual channel */
675 limit = &intel_limits_g4x_single_channel_lvds;
676 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
677 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
678 limit = &intel_limits_g4x_hdmi;
679 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
680 limit = &intel_limits_g4x_sdvo;
681 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
682 limit = &intel_limits_g4x_display_port;
683 } else /* The option is for other outputs */
684 limit = &intel_limits_i9xx_sdvo;
685
686 return limit;
687 }
688
689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
690 {
691 struct drm_device *dev = crtc->dev;
692 const intel_limit_t *limit;
693
694 if (HAS_PCH_SPLIT(dev))
695 limit = intel_ironlake_limit(crtc);
696 else if (IS_G4X(dev)) {
697 limit = intel_g4x_limit(crtc);
698 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
699 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
700 limit = &intel_limits_i9xx_lvds;
701 else
702 limit = &intel_limits_i9xx_sdvo;
703 } else if (IS_PINEVIEW(dev)) {
704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705 limit = &intel_limits_pineview_lvds;
706 else
707 limit = &intel_limits_pineview_sdvo;
708 } else {
709 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710 limit = &intel_limits_i8xx_lvds;
711 else
712 limit = &intel_limits_i8xx_dvo;
713 }
714 return limit;
715 }
716
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk, intel_clock_t *clock)
719 {
720 clock->m = clock->m2 + 2;
721 clock->p = clock->p1 * clock->p2;
722 clock->vco = refclk * clock->m / clock->n;
723 clock->dot = clock->vco / clock->p;
724 }
725
726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
727 {
728 if (IS_PINEVIEW(dev)) {
729 pineview_clock(refclk, clock);
730 return;
731 }
732 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
733 clock->p = clock->p1 * clock->p2;
734 clock->vco = refclk * clock->m / (clock->n + 2);
735 clock->dot = clock->vco / clock->p;
736 }
737
738 /**
739 * Returns whether any output on the specified pipe is of the specified type
740 */
741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742 {
743 struct drm_device *dev = crtc->dev;
744 struct drm_mode_config *mode_config = &dev->mode_config;
745 struct drm_encoder *l_entry;
746
747 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
748 if (l_entry && l_entry->crtc == crtc) {
749 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
750 if (intel_encoder->type == type)
751 return true;
752 }
753 }
754 return false;
755 }
756
757 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
758 /**
759 * Returns whether the given set of divisors are valid for a given refclk with
760 * the given connectors.
761 */
762
763 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
764 {
765 const intel_limit_t *limit = intel_limit (crtc);
766 struct drm_device *dev = crtc->dev;
767
768 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
769 INTELPllInvalid ("p1 out of range\n");
770 if (clock->p < limit->p.min || limit->p.max < clock->p)
771 INTELPllInvalid ("p out of range\n");
772 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
773 INTELPllInvalid ("m2 out of range\n");
774 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
775 INTELPllInvalid ("m1 out of range\n");
776 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
777 INTELPllInvalid ("m1 <= m2\n");
778 if (clock->m < limit->m.min || limit->m.max < clock->m)
779 INTELPllInvalid ("m out of range\n");
780 if (clock->n < limit->n.min || limit->n.max < clock->n)
781 INTELPllInvalid ("n out of range\n");
782 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
783 INTELPllInvalid ("vco out of range\n");
784 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785 * connector, etc., rather than just a single range.
786 */
787 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
788 INTELPllInvalid ("dot out of range\n");
789
790 return true;
791 }
792
793 static bool
794 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
795 int target, int refclk, intel_clock_t *best_clock)
796
797 {
798 struct drm_device *dev = crtc->dev;
799 struct drm_i915_private *dev_priv = dev->dev_private;
800 intel_clock_t clock;
801 int err = target;
802
803 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
804 (I915_READ(LVDS)) != 0) {
805 /*
806 * For LVDS, if the panel is on, just rely on its current
807 * settings for dual-channel. We haven't figured out how to
808 * reliably set up different single/dual channel state, if we
809 * even can.
810 */
811 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
812 LVDS_CLKB_POWER_UP)
813 clock.p2 = limit->p2.p2_fast;
814 else
815 clock.p2 = limit->p2.p2_slow;
816 } else {
817 if (target < limit->p2.dot_limit)
818 clock.p2 = limit->p2.p2_slow;
819 else
820 clock.p2 = limit->p2.p2_fast;
821 }
822
823 memset (best_clock, 0, sizeof (*best_clock));
824
825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
829 /* m1 is always 0 in Pineview */
830 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
831 break;
832 for (clock.n = limit->n.min;
833 clock.n <= limit->n.max; clock.n++) {
834 for (clock.p1 = limit->p1.min;
835 clock.p1 <= limit->p1.max; clock.p1++) {
836 int this_err;
837
838 intel_clock(dev, refclk, &clock);
839
840 if (!intel_PLL_is_valid(crtc, &clock))
841 continue;
842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854 }
855
856 static bool
857 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
858 int target, int refclk, intel_clock_t *best_clock)
859 {
860 struct drm_device *dev = crtc->dev;
861 struct drm_i915_private *dev_priv = dev->dev_private;
862 intel_clock_t clock;
863 int max_n;
864 bool found;
865 /* approximately equals target * 0.00488 */
866 int err_most = (target >> 8) + (target >> 10);
867 found = false;
868
869 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
870 int lvds_reg;
871
872 if (HAS_PCH_SPLIT(dev))
873 lvds_reg = PCH_LVDS;
874 else
875 lvds_reg = LVDS;
876 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
877 LVDS_CLKB_POWER_UP)
878 clock.p2 = limit->p2.p2_fast;
879 else
880 clock.p2 = limit->p2.p2_slow;
881 } else {
882 if (target < limit->p2.dot_limit)
883 clock.p2 = limit->p2.p2_slow;
884 else
885 clock.p2 = limit->p2.p2_fast;
886 }
887
888 memset(best_clock, 0, sizeof(*best_clock));
889 max_n = limit->n.max;
890 /* based on hardware requirement, prefer smaller n to precision */
891 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
892 /* based on hardware requirement, prefere larger m1,m2 */
893 for (clock.m1 = limit->m1.max;
894 clock.m1 >= limit->m1.min; clock.m1--) {
895 for (clock.m2 = limit->m2.max;
896 clock.m2 >= limit->m2.min; clock.m2--) {
897 for (clock.p1 = limit->p1.max;
898 clock.p1 >= limit->p1.min; clock.p1--) {
899 int this_err;
900
901 intel_clock(dev, refclk, &clock);
902 if (!intel_PLL_is_valid(crtc, &clock))
903 continue;
904 this_err = abs(clock.dot - target) ;
905 if (this_err < err_most) {
906 *best_clock = clock;
907 err_most = this_err;
908 max_n = clock.n;
909 found = true;
910 }
911 }
912 }
913 }
914 }
915 return found;
916 }
917
918 static bool
919 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
920 int target, int refclk, intel_clock_t *best_clock)
921 {
922 struct drm_device *dev = crtc->dev;
923 intel_clock_t clock;
924
925 /* return directly when it is eDP */
926 if (HAS_eDP)
927 return true;
928
929 if (target < 200000) {
930 clock.n = 1;
931 clock.p1 = 2;
932 clock.p2 = 10;
933 clock.m1 = 12;
934 clock.m2 = 9;
935 } else {
936 clock.n = 2;
937 clock.p1 = 1;
938 clock.p2 = 10;
939 clock.m1 = 14;
940 clock.m2 = 8;
941 }
942 intel_clock(dev, refclk, &clock);
943 memcpy(best_clock, &clock, sizeof(intel_clock_t));
944 return true;
945 }
946
947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
948 static bool
949 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
950 int target, int refclk, intel_clock_t *best_clock)
951 {
952 intel_clock_t clock;
953 if (target < 200000) {
954 clock.p1 = 2;
955 clock.p2 = 10;
956 clock.n = 2;
957 clock.m1 = 23;
958 clock.m2 = 8;
959 } else {
960 clock.p1 = 1;
961 clock.p2 = 10;
962 clock.n = 1;
963 clock.m1 = 14;
964 clock.m2 = 2;
965 }
966 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
967 clock.p = (clock.p1 * clock.p2);
968 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
969 clock.vco = 0;
970 memcpy(best_clock, &clock, sizeof(intel_clock_t));
971 return true;
972 }
973
974 void
975 intel_wait_for_vblank(struct drm_device *dev)
976 {
977 /* Wait for 20ms, i.e. one cycle at 50hz. */
978 msleep(20);
979 }
980
981 /* Parameters have changed, update FBC info */
982 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
983 {
984 struct drm_device *dev = crtc->dev;
985 struct drm_i915_private *dev_priv = dev->dev_private;
986 struct drm_framebuffer *fb = crtc->fb;
987 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
988 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
990 int plane, i;
991 u32 fbc_ctl, fbc_ctl2;
992
993 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
994
995 if (fb->pitch < dev_priv->cfb_pitch)
996 dev_priv->cfb_pitch = fb->pitch;
997
998 /* FBC_CTL wants 64B units */
999 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1000 dev_priv->cfb_fence = obj_priv->fence_reg;
1001 dev_priv->cfb_plane = intel_crtc->plane;
1002 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1003
1004 /* Clear old tags */
1005 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1006 I915_WRITE(FBC_TAG + (i * 4), 0);
1007
1008 /* Set it up... */
1009 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1010 if (obj_priv->tiling_mode != I915_TILING_NONE)
1011 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1012 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1013 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1014
1015 /* enable it... */
1016 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1017 if (IS_I945GM(dev))
1018 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1019 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1020 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1021 if (obj_priv->tiling_mode != I915_TILING_NONE)
1022 fbc_ctl |= dev_priv->cfb_fence;
1023 I915_WRITE(FBC_CONTROL, fbc_ctl);
1024
1025 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1026 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1027 }
1028
1029 void i8xx_disable_fbc(struct drm_device *dev)
1030 {
1031 struct drm_i915_private *dev_priv = dev->dev_private;
1032 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1033 u32 fbc_ctl;
1034
1035 if (!I915_HAS_FBC(dev))
1036 return;
1037
1038 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1039 return; /* Already off, just return */
1040
1041 /* Disable compression */
1042 fbc_ctl = I915_READ(FBC_CONTROL);
1043 fbc_ctl &= ~FBC_CTL_EN;
1044 I915_WRITE(FBC_CONTROL, fbc_ctl);
1045
1046 /* Wait for compressing bit to clear */
1047 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1048 if (time_after(jiffies, timeout)) {
1049 DRM_DEBUG_DRIVER("FBC idle timed out\n");
1050 break;
1051 }
1052 ; /* do nothing */
1053 }
1054
1055 intel_wait_for_vblank(dev);
1056
1057 DRM_DEBUG_KMS("disabled FBC\n");
1058 }
1059
1060 static bool i8xx_fbc_enabled(struct drm_device *dev)
1061 {
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1063
1064 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1065 }
1066
1067 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1068 {
1069 struct drm_device *dev = crtc->dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 struct drm_framebuffer *fb = crtc->fb;
1072 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1073 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1075 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1076 DPFC_CTL_PLANEB);
1077 unsigned long stall_watermark = 200;
1078 u32 dpfc_ctl;
1079
1080 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1081 dev_priv->cfb_fence = obj_priv->fence_reg;
1082 dev_priv->cfb_plane = intel_crtc->plane;
1083
1084 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1085 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1086 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1087 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1088 } else {
1089 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1090 }
1091
1092 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1093 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1094 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1095 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1096 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1097
1098 /* enable it... */
1099 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1100
1101 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1102 }
1103
1104 void g4x_disable_fbc(struct drm_device *dev)
1105 {
1106 struct drm_i915_private *dev_priv = dev->dev_private;
1107 u32 dpfc_ctl;
1108
1109 /* Disable compression */
1110 dpfc_ctl = I915_READ(DPFC_CONTROL);
1111 dpfc_ctl &= ~DPFC_CTL_EN;
1112 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1113 intel_wait_for_vblank(dev);
1114
1115 DRM_DEBUG_KMS("disabled FBC\n");
1116 }
1117
1118 static bool g4x_fbc_enabled(struct drm_device *dev)
1119 {
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121
1122 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1123 }
1124
1125 bool intel_fbc_enabled(struct drm_device *dev)
1126 {
1127 struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129 if (!dev_priv->display.fbc_enabled)
1130 return false;
1131
1132 return dev_priv->display.fbc_enabled(dev);
1133 }
1134
1135 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1136 {
1137 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1138
1139 if (!dev_priv->display.enable_fbc)
1140 return;
1141
1142 dev_priv->display.enable_fbc(crtc, interval);
1143 }
1144
1145 void intel_disable_fbc(struct drm_device *dev)
1146 {
1147 struct drm_i915_private *dev_priv = dev->dev_private;
1148
1149 if (!dev_priv->display.disable_fbc)
1150 return;
1151
1152 dev_priv->display.disable_fbc(dev);
1153 }
1154
1155 /**
1156 * intel_update_fbc - enable/disable FBC as needed
1157 * @crtc: CRTC to point the compressor at
1158 * @mode: mode in use
1159 *
1160 * Set up the framebuffer compression hardware at mode set time. We
1161 * enable it if possible:
1162 * - plane A only (on pre-965)
1163 * - no pixel mulitply/line duplication
1164 * - no alpha buffer discard
1165 * - no dual wide
1166 * - framebuffer <= 2048 in width, 1536 in height
1167 *
1168 * We can't assume that any compression will take place (worst case),
1169 * so the compressed buffer has to be the same size as the uncompressed
1170 * one. It also must reside (along with the line length buffer) in
1171 * stolen memory.
1172 *
1173 * We need to enable/disable FBC on a global basis.
1174 */
1175 static void intel_update_fbc(struct drm_crtc *crtc,
1176 struct drm_display_mode *mode)
1177 {
1178 struct drm_device *dev = crtc->dev;
1179 struct drm_i915_private *dev_priv = dev->dev_private;
1180 struct drm_framebuffer *fb = crtc->fb;
1181 struct intel_framebuffer *intel_fb;
1182 struct drm_i915_gem_object *obj_priv;
1183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1184 int plane = intel_crtc->plane;
1185
1186 if (!i915_powersave)
1187 return;
1188
1189 if (!I915_HAS_FBC(dev))
1190 return;
1191
1192 if (!crtc->fb)
1193 return;
1194
1195 intel_fb = to_intel_framebuffer(fb);
1196 obj_priv = to_intel_bo(intel_fb->obj);
1197
1198 /*
1199 * If FBC is already on, we just have to verify that we can
1200 * keep it that way...
1201 * Need to disable if:
1202 * - changing FBC params (stride, fence, mode)
1203 * - new fb is too large to fit in compressed buffer
1204 * - going to an unsupported config (interlace, pixel multiply, etc.)
1205 */
1206 if (intel_fb->obj->size > dev_priv->cfb_size) {
1207 DRM_DEBUG_KMS("framebuffer too large, disabling "
1208 "compression\n");
1209 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1210 goto out_disable;
1211 }
1212 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1213 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1214 DRM_DEBUG_KMS("mode incompatible with compression, "
1215 "disabling\n");
1216 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1217 goto out_disable;
1218 }
1219 if ((mode->hdisplay > 2048) ||
1220 (mode->vdisplay > 1536)) {
1221 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1222 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1223 goto out_disable;
1224 }
1225 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1226 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1227 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1228 goto out_disable;
1229 }
1230 if (obj_priv->tiling_mode != I915_TILING_X) {
1231 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1232 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1233 goto out_disable;
1234 }
1235
1236 if (intel_fbc_enabled(dev)) {
1237 /* We can re-enable it in this case, but need to update pitch */
1238 if ((fb->pitch > dev_priv->cfb_pitch) ||
1239 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1240 (plane != dev_priv->cfb_plane))
1241 intel_disable_fbc(dev);
1242 }
1243
1244 /* Now try to turn it back on if possible */
1245 if (!intel_fbc_enabled(dev))
1246 intel_enable_fbc(crtc, 500);
1247
1248 return;
1249
1250 out_disable:
1251 /* Multiple disables should be harmless */
1252 if (intel_fbc_enabled(dev)) {
1253 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1254 intel_disable_fbc(dev);
1255 }
1256 }
1257
1258 static int
1259 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1260 {
1261 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1262 u32 alignment;
1263 int ret;
1264
1265 switch (obj_priv->tiling_mode) {
1266 case I915_TILING_NONE:
1267 alignment = 64 * 1024;
1268 break;
1269 case I915_TILING_X:
1270 /* pin() will align the object as required by fence */
1271 alignment = 0;
1272 break;
1273 case I915_TILING_Y:
1274 /* FIXME: Is this true? */
1275 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1276 return -EINVAL;
1277 default:
1278 BUG();
1279 }
1280
1281 ret = i915_gem_object_pin(obj, alignment);
1282 if (ret != 0)
1283 return ret;
1284
1285 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1286 * fence, whereas 965+ only requires a fence if using
1287 * framebuffer compression. For simplicity, we always install
1288 * a fence as the cost is not that onerous.
1289 */
1290 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1291 obj_priv->tiling_mode != I915_TILING_NONE) {
1292 ret = i915_gem_object_get_fence_reg(obj);
1293 if (ret != 0) {
1294 i915_gem_object_unpin(obj);
1295 return ret;
1296 }
1297 }
1298
1299 return 0;
1300 }
1301
1302 static int
1303 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1304 struct drm_framebuffer *old_fb)
1305 {
1306 struct drm_device *dev = crtc->dev;
1307 struct drm_i915_private *dev_priv = dev->dev_private;
1308 struct drm_i915_master_private *master_priv;
1309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1310 struct intel_framebuffer *intel_fb;
1311 struct drm_i915_gem_object *obj_priv;
1312 struct drm_gem_object *obj;
1313 int pipe = intel_crtc->pipe;
1314 int plane = intel_crtc->plane;
1315 unsigned long Start, Offset;
1316 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1317 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1318 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1319 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1320 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1321 u32 dspcntr;
1322 int ret;
1323
1324 /* no fb bound */
1325 if (!crtc->fb) {
1326 DRM_DEBUG_KMS("No FB bound\n");
1327 return 0;
1328 }
1329
1330 switch (plane) {
1331 case 0:
1332 case 1:
1333 break;
1334 default:
1335 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1336 return -EINVAL;
1337 }
1338
1339 intel_fb = to_intel_framebuffer(crtc->fb);
1340 obj = intel_fb->obj;
1341 obj_priv = to_intel_bo(obj);
1342
1343 mutex_lock(&dev->struct_mutex);
1344 ret = intel_pin_and_fence_fb_obj(dev, obj);
1345 if (ret != 0) {
1346 mutex_unlock(&dev->struct_mutex);
1347 return ret;
1348 }
1349
1350 ret = i915_gem_object_set_to_display_plane(obj);
1351 if (ret != 0) {
1352 i915_gem_object_unpin(obj);
1353 mutex_unlock(&dev->struct_mutex);
1354 return ret;
1355 }
1356
1357 dspcntr = I915_READ(dspcntr_reg);
1358 /* Mask out pixel format bits in case we change it */
1359 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1360 switch (crtc->fb->bits_per_pixel) {
1361 case 8:
1362 dspcntr |= DISPPLANE_8BPP;
1363 break;
1364 case 16:
1365 if (crtc->fb->depth == 15)
1366 dspcntr |= DISPPLANE_15_16BPP;
1367 else
1368 dspcntr |= DISPPLANE_16BPP;
1369 break;
1370 case 24:
1371 case 32:
1372 if (crtc->fb->depth == 30)
1373 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1374 else
1375 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1376 break;
1377 default:
1378 DRM_ERROR("Unknown color depth\n");
1379 i915_gem_object_unpin(obj);
1380 mutex_unlock(&dev->struct_mutex);
1381 return -EINVAL;
1382 }
1383 if (IS_I965G(dev)) {
1384 if (obj_priv->tiling_mode != I915_TILING_NONE)
1385 dspcntr |= DISPPLANE_TILED;
1386 else
1387 dspcntr &= ~DISPPLANE_TILED;
1388 }
1389
1390 if (HAS_PCH_SPLIT(dev))
1391 /* must disable */
1392 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1393
1394 I915_WRITE(dspcntr_reg, dspcntr);
1395
1396 Start = obj_priv->gtt_offset;
1397 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1398
1399 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1400 Start, Offset, x, y, crtc->fb->pitch);
1401 I915_WRITE(dspstride, crtc->fb->pitch);
1402 if (IS_I965G(dev)) {
1403 I915_WRITE(dspbase, Offset);
1404 I915_READ(dspbase);
1405 I915_WRITE(dspsurf, Start);
1406 I915_READ(dspsurf);
1407 I915_WRITE(dsptileoff, (y << 16) | x);
1408 } else {
1409 I915_WRITE(dspbase, Start + Offset);
1410 I915_READ(dspbase);
1411 }
1412
1413 if ((IS_I965G(dev) || plane == 0))
1414 intel_update_fbc(crtc, &crtc->mode);
1415
1416 intel_wait_for_vblank(dev);
1417
1418 if (old_fb) {
1419 intel_fb = to_intel_framebuffer(old_fb);
1420 obj_priv = to_intel_bo(intel_fb->obj);
1421 i915_gem_object_unpin(intel_fb->obj);
1422 }
1423 intel_increase_pllclock(crtc, true);
1424
1425 mutex_unlock(&dev->struct_mutex);
1426
1427 if (!dev->primary->master)
1428 return 0;
1429
1430 master_priv = dev->primary->master->driver_priv;
1431 if (!master_priv->sarea_priv)
1432 return 0;
1433
1434 if (pipe) {
1435 master_priv->sarea_priv->pipeB_x = x;
1436 master_priv->sarea_priv->pipeB_y = y;
1437 } else {
1438 master_priv->sarea_priv->pipeA_x = x;
1439 master_priv->sarea_priv->pipeA_y = y;
1440 }
1441
1442 return 0;
1443 }
1444
1445 /* Disable the VGA plane that we never use */
1446 static void i915_disable_vga (struct drm_device *dev)
1447 {
1448 struct drm_i915_private *dev_priv = dev->dev_private;
1449 u8 sr1;
1450 u32 vga_reg;
1451
1452 if (HAS_PCH_SPLIT(dev))
1453 vga_reg = CPU_VGACNTRL;
1454 else
1455 vga_reg = VGACNTRL;
1456
1457 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1458 return;
1459
1460 I915_WRITE8(VGA_SR_INDEX, 1);
1461 sr1 = I915_READ8(VGA_SR_DATA);
1462 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1463 udelay(100);
1464
1465 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1466 }
1467
1468 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1469 {
1470 struct drm_device *dev = crtc->dev;
1471 struct drm_i915_private *dev_priv = dev->dev_private;
1472 u32 dpa_ctl;
1473
1474 DRM_DEBUG_KMS("\n");
1475 dpa_ctl = I915_READ(DP_A);
1476 dpa_ctl &= ~DP_PLL_ENABLE;
1477 I915_WRITE(DP_A, dpa_ctl);
1478 }
1479
1480 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1481 {
1482 struct drm_device *dev = crtc->dev;
1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484 u32 dpa_ctl;
1485
1486 dpa_ctl = I915_READ(DP_A);
1487 dpa_ctl |= DP_PLL_ENABLE;
1488 I915_WRITE(DP_A, dpa_ctl);
1489 udelay(200);
1490 }
1491
1492
1493 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1494 {
1495 struct drm_device *dev = crtc->dev;
1496 struct drm_i915_private *dev_priv = dev->dev_private;
1497 u32 dpa_ctl;
1498
1499 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1500 dpa_ctl = I915_READ(DP_A);
1501 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1502
1503 if (clock < 200000) {
1504 u32 temp;
1505 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1506 /* workaround for 160Mhz:
1507 1) program 0x4600c bits 15:0 = 0x8124
1508 2) program 0x46010 bit 0 = 1
1509 3) program 0x46034 bit 24 = 1
1510 4) program 0x64000 bit 14 = 1
1511 */
1512 temp = I915_READ(0x4600c);
1513 temp &= 0xffff0000;
1514 I915_WRITE(0x4600c, temp | 0x8124);
1515
1516 temp = I915_READ(0x46010);
1517 I915_WRITE(0x46010, temp | 1);
1518
1519 temp = I915_READ(0x46034);
1520 I915_WRITE(0x46034, temp | (1 << 24));
1521 } else {
1522 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1523 }
1524 I915_WRITE(DP_A, dpa_ctl);
1525
1526 udelay(500);
1527 }
1528
1529 /* The FDI link training functions for ILK/Ibexpeak. */
1530 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1531 {
1532 struct drm_device *dev = crtc->dev;
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1535 int pipe = intel_crtc->pipe;
1536 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1537 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1538 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1539 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1540 u32 temp, tries = 0;
1541
1542 /* enable CPU FDI TX and PCH FDI RX */
1543 temp = I915_READ(fdi_tx_reg);
1544 temp |= FDI_TX_ENABLE;
1545 temp &= ~(7 << 19);
1546 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1547 temp &= ~FDI_LINK_TRAIN_NONE;
1548 temp |= FDI_LINK_TRAIN_PATTERN_1;
1549 I915_WRITE(fdi_tx_reg, temp);
1550 I915_READ(fdi_tx_reg);
1551
1552 temp = I915_READ(fdi_rx_reg);
1553 temp &= ~FDI_LINK_TRAIN_NONE;
1554 temp |= FDI_LINK_TRAIN_PATTERN_1;
1555 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1556 I915_READ(fdi_rx_reg);
1557 udelay(150);
1558
1559 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1560 for train result */
1561 temp = I915_READ(fdi_rx_imr_reg);
1562 temp &= ~FDI_RX_SYMBOL_LOCK;
1563 temp &= ~FDI_RX_BIT_LOCK;
1564 I915_WRITE(fdi_rx_imr_reg, temp);
1565 I915_READ(fdi_rx_imr_reg);
1566 udelay(150);
1567
1568 for (;;) {
1569 temp = I915_READ(fdi_rx_iir_reg);
1570 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1571
1572 if ((temp & FDI_RX_BIT_LOCK)) {
1573 DRM_DEBUG_KMS("FDI train 1 done.\n");
1574 I915_WRITE(fdi_rx_iir_reg,
1575 temp | FDI_RX_BIT_LOCK);
1576 break;
1577 }
1578
1579 tries++;
1580
1581 if (tries > 5) {
1582 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1583 break;
1584 }
1585 }
1586
1587 /* Train 2 */
1588 temp = I915_READ(fdi_tx_reg);
1589 temp &= ~FDI_LINK_TRAIN_NONE;
1590 temp |= FDI_LINK_TRAIN_PATTERN_2;
1591 I915_WRITE(fdi_tx_reg, temp);
1592
1593 temp = I915_READ(fdi_rx_reg);
1594 temp &= ~FDI_LINK_TRAIN_NONE;
1595 temp |= FDI_LINK_TRAIN_PATTERN_2;
1596 I915_WRITE(fdi_rx_reg, temp);
1597 udelay(150);
1598
1599 tries = 0;
1600
1601 for (;;) {
1602 temp = I915_READ(fdi_rx_iir_reg);
1603 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1604
1605 if (temp & FDI_RX_SYMBOL_LOCK) {
1606 I915_WRITE(fdi_rx_iir_reg,
1607 temp | FDI_RX_SYMBOL_LOCK);
1608 DRM_DEBUG_KMS("FDI train 2 done.\n");
1609 break;
1610 }
1611
1612 tries++;
1613
1614 if (tries > 5) {
1615 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1616 break;
1617 }
1618 }
1619
1620 DRM_DEBUG_KMS("FDI train done\n");
1621 }
1622
1623 static int snb_b_fdi_train_param [] = {
1624 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1625 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1626 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1627 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1628 };
1629
1630 /* The FDI link training functions for SNB/Cougarpoint. */
1631 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1632 {
1633 struct drm_device *dev = crtc->dev;
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1636 int pipe = intel_crtc->pipe;
1637 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1638 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1639 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1640 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1641 u32 temp, i;
1642
1643 /* enable CPU FDI TX and PCH FDI RX */
1644 temp = I915_READ(fdi_tx_reg);
1645 temp |= FDI_TX_ENABLE;
1646 temp &= ~(7 << 19);
1647 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1648 temp &= ~FDI_LINK_TRAIN_NONE;
1649 temp |= FDI_LINK_TRAIN_PATTERN_1;
1650 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1651 /* SNB-B */
1652 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1653 I915_WRITE(fdi_tx_reg, temp);
1654 I915_READ(fdi_tx_reg);
1655
1656 temp = I915_READ(fdi_rx_reg);
1657 if (HAS_PCH_CPT(dev)) {
1658 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1659 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1660 } else {
1661 temp &= ~FDI_LINK_TRAIN_NONE;
1662 temp |= FDI_LINK_TRAIN_PATTERN_1;
1663 }
1664 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1665 I915_READ(fdi_rx_reg);
1666 udelay(150);
1667
1668 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1669 for train result */
1670 temp = I915_READ(fdi_rx_imr_reg);
1671 temp &= ~FDI_RX_SYMBOL_LOCK;
1672 temp &= ~FDI_RX_BIT_LOCK;
1673 I915_WRITE(fdi_rx_imr_reg, temp);
1674 I915_READ(fdi_rx_imr_reg);
1675 udelay(150);
1676
1677 for (i = 0; i < 4; i++ ) {
1678 temp = I915_READ(fdi_tx_reg);
1679 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1680 temp |= snb_b_fdi_train_param[i];
1681 I915_WRITE(fdi_tx_reg, temp);
1682 udelay(500);
1683
1684 temp = I915_READ(fdi_rx_iir_reg);
1685 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1686
1687 if (temp & FDI_RX_BIT_LOCK) {
1688 I915_WRITE(fdi_rx_iir_reg,
1689 temp | FDI_RX_BIT_LOCK);
1690 DRM_DEBUG_KMS("FDI train 1 done.\n");
1691 break;
1692 }
1693 }
1694 if (i == 4)
1695 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1696
1697 /* Train 2 */
1698 temp = I915_READ(fdi_tx_reg);
1699 temp &= ~FDI_LINK_TRAIN_NONE;
1700 temp |= FDI_LINK_TRAIN_PATTERN_2;
1701 if (IS_GEN6(dev)) {
1702 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1703 /* SNB-B */
1704 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1705 }
1706 I915_WRITE(fdi_tx_reg, temp);
1707
1708 temp = I915_READ(fdi_rx_reg);
1709 if (HAS_PCH_CPT(dev)) {
1710 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1711 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1712 } else {
1713 temp &= ~FDI_LINK_TRAIN_NONE;
1714 temp |= FDI_LINK_TRAIN_PATTERN_2;
1715 }
1716 I915_WRITE(fdi_rx_reg, temp);
1717 udelay(150);
1718
1719 for (i = 0; i < 4; i++ ) {
1720 temp = I915_READ(fdi_tx_reg);
1721 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1722 temp |= snb_b_fdi_train_param[i];
1723 I915_WRITE(fdi_tx_reg, temp);
1724 udelay(500);
1725
1726 temp = I915_READ(fdi_rx_iir_reg);
1727 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1728
1729 if (temp & FDI_RX_SYMBOL_LOCK) {
1730 I915_WRITE(fdi_rx_iir_reg,
1731 temp | FDI_RX_SYMBOL_LOCK);
1732 DRM_DEBUG_KMS("FDI train 2 done.\n");
1733 break;
1734 }
1735 }
1736 if (i == 4)
1737 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1738
1739 DRM_DEBUG_KMS("FDI train done.\n");
1740 }
1741
1742 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1743 {
1744 struct drm_device *dev = crtc->dev;
1745 struct drm_i915_private *dev_priv = dev->dev_private;
1746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1747 int pipe = intel_crtc->pipe;
1748 int plane = intel_crtc->plane;
1749 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1750 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1751 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1752 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1753 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1754 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1755 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1756 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1757 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1758 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1759 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1760 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1761 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1762 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1763 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1764 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1765 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1766 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1767 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1768 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1769 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1770 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1771 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1772 u32 temp;
1773 int n;
1774 u32 pipe_bpc;
1775
1776 temp = I915_READ(pipeconf_reg);
1777 pipe_bpc = temp & PIPE_BPC_MASK;
1778
1779 /* XXX: When our outputs are all unaware of DPMS modes other than off
1780 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1781 */
1782 switch (mode) {
1783 case DRM_MODE_DPMS_ON:
1784 case DRM_MODE_DPMS_STANDBY:
1785 case DRM_MODE_DPMS_SUSPEND:
1786 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1787
1788 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1789 temp = I915_READ(PCH_LVDS);
1790 if ((temp & LVDS_PORT_EN) == 0) {
1791 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1792 POSTING_READ(PCH_LVDS);
1793 }
1794 }
1795
1796 if (HAS_eDP) {
1797 /* enable eDP PLL */
1798 ironlake_enable_pll_edp(crtc);
1799 } else {
1800
1801 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1802 temp = I915_READ(fdi_rx_reg);
1803 /*
1804 * make the BPC in FDI Rx be consistent with that in
1805 * pipeconf reg.
1806 */
1807 temp &= ~(0x7 << 16);
1808 temp |= (pipe_bpc << 11);
1809 temp &= ~(7 << 19);
1810 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1811 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1812 I915_READ(fdi_rx_reg);
1813 udelay(200);
1814
1815 /* Switch from Rawclk to PCDclk */
1816 temp = I915_READ(fdi_rx_reg);
1817 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1818 I915_READ(fdi_rx_reg);
1819 udelay(200);
1820
1821 /* Enable CPU FDI TX PLL, always on for Ironlake */
1822 temp = I915_READ(fdi_tx_reg);
1823 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1824 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1825 I915_READ(fdi_tx_reg);
1826 udelay(100);
1827 }
1828 }
1829
1830 /* Enable panel fitting for LVDS */
1831 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1832 temp = I915_READ(pf_ctl_reg);
1833 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1834
1835 /* currently full aspect */
1836 I915_WRITE(pf_win_pos, 0);
1837
1838 I915_WRITE(pf_win_size,
1839 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1840 (dev_priv->panel_fixed_mode->vdisplay));
1841 }
1842
1843 /* Enable CPU pipe */
1844 temp = I915_READ(pipeconf_reg);
1845 if ((temp & PIPEACONF_ENABLE) == 0) {
1846 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1847 I915_READ(pipeconf_reg);
1848 udelay(100);
1849 }
1850
1851 /* configure and enable CPU plane */
1852 temp = I915_READ(dspcntr_reg);
1853 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1854 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1855 /* Flush the plane changes */
1856 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1857 }
1858
1859 if (!HAS_eDP) {
1860 /* For PCH output, training FDI link */
1861 if (IS_GEN6(dev))
1862 gen6_fdi_link_train(crtc);
1863 else
1864 ironlake_fdi_link_train(crtc);
1865
1866 /* enable PCH DPLL */
1867 temp = I915_READ(pch_dpll_reg);
1868 if ((temp & DPLL_VCO_ENABLE) == 0) {
1869 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1870 I915_READ(pch_dpll_reg);
1871 }
1872 udelay(200);
1873
1874 if (HAS_PCH_CPT(dev)) {
1875 /* Be sure PCH DPLL SEL is set */
1876 temp = I915_READ(PCH_DPLL_SEL);
1877 if (trans_dpll_sel == 0 &&
1878 (temp & TRANSA_DPLL_ENABLE) == 0)
1879 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1880 else if (trans_dpll_sel == 1 &&
1881 (temp & TRANSB_DPLL_ENABLE) == 0)
1882 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1883 I915_WRITE(PCH_DPLL_SEL, temp);
1884 I915_READ(PCH_DPLL_SEL);
1885 }
1886
1887 /* set transcoder timing */
1888 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1889 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1890 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1891
1892 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1893 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1894 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1895
1896 /* enable normal train */
1897 temp = I915_READ(fdi_tx_reg);
1898 temp &= ~FDI_LINK_TRAIN_NONE;
1899 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1900 FDI_TX_ENHANCE_FRAME_ENABLE);
1901 I915_READ(fdi_tx_reg);
1902
1903 temp = I915_READ(fdi_rx_reg);
1904 if (HAS_PCH_CPT(dev)) {
1905 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1906 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1907 } else {
1908 temp &= ~FDI_LINK_TRAIN_NONE;
1909 temp |= FDI_LINK_TRAIN_NONE;
1910 }
1911 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1912 I915_READ(fdi_rx_reg);
1913
1914 /* wait one idle pattern time */
1915 udelay(100);
1916
1917 /* For PCH DP, enable TRANS_DP_CTL */
1918 if (HAS_PCH_CPT(dev) &&
1919 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1920 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1921 int reg;
1922
1923 reg = I915_READ(trans_dp_ctl);
1924 reg &= ~TRANS_DP_PORT_SEL_MASK;
1925 reg = TRANS_DP_OUTPUT_ENABLE |
1926 TRANS_DP_ENH_FRAMING |
1927 TRANS_DP_VSYNC_ACTIVE_HIGH |
1928 TRANS_DP_HSYNC_ACTIVE_HIGH;
1929
1930 switch (intel_trans_dp_port_sel(crtc)) {
1931 case PCH_DP_B:
1932 reg |= TRANS_DP_PORT_SEL_B;
1933 break;
1934 case PCH_DP_C:
1935 reg |= TRANS_DP_PORT_SEL_C;
1936 break;
1937 case PCH_DP_D:
1938 reg |= TRANS_DP_PORT_SEL_D;
1939 break;
1940 default:
1941 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1942 reg |= TRANS_DP_PORT_SEL_B;
1943 break;
1944 }
1945
1946 I915_WRITE(trans_dp_ctl, reg);
1947 POSTING_READ(trans_dp_ctl);
1948 }
1949
1950 /* enable PCH transcoder */
1951 temp = I915_READ(transconf_reg);
1952 /*
1953 * make the BPC in transcoder be consistent with
1954 * that in pipeconf reg.
1955 */
1956 temp &= ~PIPE_BPC_MASK;
1957 temp |= pipe_bpc;
1958 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1959 I915_READ(transconf_reg);
1960
1961 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1962 ;
1963
1964 }
1965
1966 intel_crtc_load_lut(crtc);
1967
1968 break;
1969 case DRM_MODE_DPMS_OFF:
1970 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1971
1972 drm_vblank_off(dev, pipe);
1973 /* Disable display plane */
1974 temp = I915_READ(dspcntr_reg);
1975 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1976 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1977 /* Flush the plane changes */
1978 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1979 I915_READ(dspbase_reg);
1980 }
1981
1982 i915_disable_vga(dev);
1983
1984 /* disable cpu pipe, disable after all planes disabled */
1985 temp = I915_READ(pipeconf_reg);
1986 if ((temp & PIPEACONF_ENABLE) != 0) {
1987 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1988 I915_READ(pipeconf_reg);
1989 n = 0;
1990 /* wait for cpu pipe off, pipe state */
1991 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1992 n++;
1993 if (n < 60) {
1994 udelay(500);
1995 continue;
1996 } else {
1997 DRM_DEBUG_KMS("pipe %d off delay\n",
1998 pipe);
1999 break;
2000 }
2001 }
2002 } else
2003 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2004
2005 udelay(100);
2006
2007 /* Disable PF */
2008 temp = I915_READ(pf_ctl_reg);
2009 if ((temp & PF_ENABLE) != 0) {
2010 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2011 I915_READ(pf_ctl_reg);
2012 }
2013 I915_WRITE(pf_win_size, 0);
2014 POSTING_READ(pf_win_size);
2015
2016
2017 /* disable CPU FDI tx and PCH FDI rx */
2018 temp = I915_READ(fdi_tx_reg);
2019 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2020 I915_READ(fdi_tx_reg);
2021
2022 temp = I915_READ(fdi_rx_reg);
2023 /* BPC in FDI rx is consistent with that in pipeconf */
2024 temp &= ~(0x07 << 16);
2025 temp |= (pipe_bpc << 11);
2026 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2027 I915_READ(fdi_rx_reg);
2028
2029 udelay(100);
2030
2031 /* still set train pattern 1 */
2032 temp = I915_READ(fdi_tx_reg);
2033 temp &= ~FDI_LINK_TRAIN_NONE;
2034 temp |= FDI_LINK_TRAIN_PATTERN_1;
2035 I915_WRITE(fdi_tx_reg, temp);
2036 POSTING_READ(fdi_tx_reg);
2037
2038 temp = I915_READ(fdi_rx_reg);
2039 if (HAS_PCH_CPT(dev)) {
2040 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2041 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2042 } else {
2043 temp &= ~FDI_LINK_TRAIN_NONE;
2044 temp |= FDI_LINK_TRAIN_PATTERN_1;
2045 }
2046 I915_WRITE(fdi_rx_reg, temp);
2047 POSTING_READ(fdi_rx_reg);
2048
2049 udelay(100);
2050
2051 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2052 temp = I915_READ(PCH_LVDS);
2053 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2054 I915_READ(PCH_LVDS);
2055 udelay(100);
2056 }
2057
2058 /* disable PCH transcoder */
2059 temp = I915_READ(transconf_reg);
2060 if ((temp & TRANS_ENABLE) != 0) {
2061 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2062 I915_READ(transconf_reg);
2063 n = 0;
2064 /* wait for PCH transcoder off, transcoder state */
2065 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2066 n++;
2067 if (n < 60) {
2068 udelay(500);
2069 continue;
2070 } else {
2071 DRM_DEBUG_KMS("transcoder %d off "
2072 "delay\n", pipe);
2073 break;
2074 }
2075 }
2076 }
2077
2078 temp = I915_READ(transconf_reg);
2079 /* BPC in transcoder is consistent with that in pipeconf */
2080 temp &= ~PIPE_BPC_MASK;
2081 temp |= pipe_bpc;
2082 I915_WRITE(transconf_reg, temp);
2083 I915_READ(transconf_reg);
2084 udelay(100);
2085
2086 if (HAS_PCH_CPT(dev)) {
2087 /* disable TRANS_DP_CTL */
2088 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2089 int reg;
2090
2091 reg = I915_READ(trans_dp_ctl);
2092 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2093 I915_WRITE(trans_dp_ctl, reg);
2094 POSTING_READ(trans_dp_ctl);
2095
2096 /* disable DPLL_SEL */
2097 temp = I915_READ(PCH_DPLL_SEL);
2098 if (trans_dpll_sel == 0)
2099 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2100 else
2101 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2102 I915_WRITE(PCH_DPLL_SEL, temp);
2103 I915_READ(PCH_DPLL_SEL);
2104
2105 }
2106
2107 /* disable PCH DPLL */
2108 temp = I915_READ(pch_dpll_reg);
2109 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2110 I915_READ(pch_dpll_reg);
2111
2112 if (HAS_eDP) {
2113 ironlake_disable_pll_edp(crtc);
2114 }
2115
2116 /* Switch from PCDclk to Rawclk */
2117 temp = I915_READ(fdi_rx_reg);
2118 temp &= ~FDI_SEL_PCDCLK;
2119 I915_WRITE(fdi_rx_reg, temp);
2120 I915_READ(fdi_rx_reg);
2121
2122 /* Disable CPU FDI TX PLL */
2123 temp = I915_READ(fdi_tx_reg);
2124 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2125 I915_READ(fdi_tx_reg);
2126 udelay(100);
2127
2128 temp = I915_READ(fdi_rx_reg);
2129 temp &= ~FDI_RX_PLL_ENABLE;
2130 I915_WRITE(fdi_rx_reg, temp);
2131 I915_READ(fdi_rx_reg);
2132
2133 /* Wait for the clocks to turn off. */
2134 udelay(100);
2135 break;
2136 }
2137 }
2138
2139 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2140 {
2141 struct intel_overlay *overlay;
2142 int ret;
2143
2144 if (!enable && intel_crtc->overlay) {
2145 overlay = intel_crtc->overlay;
2146 mutex_lock(&overlay->dev->struct_mutex);
2147 for (;;) {
2148 ret = intel_overlay_switch_off(overlay);
2149 if (ret == 0)
2150 break;
2151
2152 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2153 if (ret != 0) {
2154 /* overlay doesn't react anymore. Usually
2155 * results in a black screen and an unkillable
2156 * X server. */
2157 BUG();
2158 overlay->hw_wedged = HW_WEDGED;
2159 break;
2160 }
2161 }
2162 mutex_unlock(&overlay->dev->struct_mutex);
2163 }
2164 /* Let userspace switch the overlay on again. In most cases userspace
2165 * has to recompute where to put it anyway. */
2166
2167 return;
2168 }
2169
2170 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2171 {
2172 struct drm_device *dev = crtc->dev;
2173 struct drm_i915_private *dev_priv = dev->dev_private;
2174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2175 int pipe = intel_crtc->pipe;
2176 int plane = intel_crtc->plane;
2177 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2178 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2179 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2180 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2181 u32 temp;
2182
2183 /* XXX: When our outputs are all unaware of DPMS modes other than off
2184 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2185 */
2186 switch (mode) {
2187 case DRM_MODE_DPMS_ON:
2188 case DRM_MODE_DPMS_STANDBY:
2189 case DRM_MODE_DPMS_SUSPEND:
2190 intel_update_watermarks(dev);
2191
2192 /* Enable the DPLL */
2193 temp = I915_READ(dpll_reg);
2194 if ((temp & DPLL_VCO_ENABLE) == 0) {
2195 I915_WRITE(dpll_reg, temp);
2196 I915_READ(dpll_reg);
2197 /* Wait for the clocks to stabilize. */
2198 udelay(150);
2199 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2200 I915_READ(dpll_reg);
2201 /* Wait for the clocks to stabilize. */
2202 udelay(150);
2203 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2204 I915_READ(dpll_reg);
2205 /* Wait for the clocks to stabilize. */
2206 udelay(150);
2207 }
2208
2209 /* Enable the pipe */
2210 temp = I915_READ(pipeconf_reg);
2211 if ((temp & PIPEACONF_ENABLE) == 0)
2212 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2213
2214 /* Enable the plane */
2215 temp = I915_READ(dspcntr_reg);
2216 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2217 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2218 /* Flush the plane changes */
2219 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2220 }
2221
2222 intel_crtc_load_lut(crtc);
2223
2224 if ((IS_I965G(dev) || plane == 0))
2225 intel_update_fbc(crtc, &crtc->mode);
2226
2227 /* Give the overlay scaler a chance to enable if it's on this pipe */
2228 intel_crtc_dpms_overlay(intel_crtc, true);
2229 break;
2230 case DRM_MODE_DPMS_OFF:
2231 intel_update_watermarks(dev);
2232
2233 /* Give the overlay scaler a chance to disable if it's on this pipe */
2234 intel_crtc_dpms_overlay(intel_crtc, false);
2235 drm_vblank_off(dev, pipe);
2236
2237 if (dev_priv->cfb_plane == plane &&
2238 dev_priv->display.disable_fbc)
2239 dev_priv->display.disable_fbc(dev);
2240
2241 /* Disable the VGA plane that we never use */
2242 i915_disable_vga(dev);
2243
2244 /* Disable display plane */
2245 temp = I915_READ(dspcntr_reg);
2246 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2247 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2248 /* Flush the plane changes */
2249 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2250 I915_READ(dspbase_reg);
2251 }
2252
2253 if (!IS_I9XX(dev)) {
2254 /* Wait for vblank for the disable to take effect */
2255 intel_wait_for_vblank(dev);
2256 }
2257
2258 /* Next, disable display pipes */
2259 temp = I915_READ(pipeconf_reg);
2260 if ((temp & PIPEACONF_ENABLE) != 0) {
2261 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2262 I915_READ(pipeconf_reg);
2263 }
2264
2265 /* Wait for vblank for the disable to take effect. */
2266 intel_wait_for_vblank(dev);
2267
2268 temp = I915_READ(dpll_reg);
2269 if ((temp & DPLL_VCO_ENABLE) != 0) {
2270 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2271 I915_READ(dpll_reg);
2272 }
2273
2274 /* Wait for the clocks to turn off. */
2275 udelay(150);
2276 break;
2277 }
2278 }
2279
2280 /**
2281 * Sets the power management mode of the pipe and plane.
2282 *
2283 * This code should probably grow support for turning the cursor off and back
2284 * on appropriately at the same time as we're turning the pipe off/on.
2285 */
2286 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2287 {
2288 struct drm_device *dev = crtc->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct drm_i915_master_private *master_priv;
2291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2292 int pipe = intel_crtc->pipe;
2293 bool enabled;
2294
2295 dev_priv->display.dpms(crtc, mode);
2296
2297 intel_crtc->dpms_mode = mode;
2298
2299 if (!dev->primary->master)
2300 return;
2301
2302 master_priv = dev->primary->master->driver_priv;
2303 if (!master_priv->sarea_priv)
2304 return;
2305
2306 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2307
2308 switch (pipe) {
2309 case 0:
2310 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2311 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2312 break;
2313 case 1:
2314 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2315 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2316 break;
2317 default:
2318 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2319 break;
2320 }
2321 }
2322
2323 static void intel_crtc_prepare (struct drm_crtc *crtc)
2324 {
2325 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2326 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2327 }
2328
2329 static void intel_crtc_commit (struct drm_crtc *crtc)
2330 {
2331 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2332 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2333 }
2334
2335 void intel_encoder_prepare (struct drm_encoder *encoder)
2336 {
2337 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2338 /* lvds has its own version of prepare see intel_lvds_prepare */
2339 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2340 }
2341
2342 void intel_encoder_commit (struct drm_encoder *encoder)
2343 {
2344 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2345 /* lvds has its own version of commit see intel_lvds_commit */
2346 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2347 }
2348
2349 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2350 struct drm_display_mode *mode,
2351 struct drm_display_mode *adjusted_mode)
2352 {
2353 struct drm_device *dev = crtc->dev;
2354 if (HAS_PCH_SPLIT(dev)) {
2355 /* FDI link clock is fixed at 2.7G */
2356 if (mode->clock * 3 > 27000 * 4)
2357 return MODE_CLOCK_HIGH;
2358 }
2359
2360 drm_mode_set_crtcinfo(adjusted_mode, 0);
2361 return true;
2362 }
2363
2364 static int i945_get_display_clock_speed(struct drm_device *dev)
2365 {
2366 return 400000;
2367 }
2368
2369 static int i915_get_display_clock_speed(struct drm_device *dev)
2370 {
2371 return 333000;
2372 }
2373
2374 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2375 {
2376 return 200000;
2377 }
2378
2379 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2380 {
2381 u16 gcfgc = 0;
2382
2383 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2384
2385 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2386 return 133000;
2387 else {
2388 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2389 case GC_DISPLAY_CLOCK_333_MHZ:
2390 return 333000;
2391 default:
2392 case GC_DISPLAY_CLOCK_190_200_MHZ:
2393 return 190000;
2394 }
2395 }
2396 }
2397
2398 static int i865_get_display_clock_speed(struct drm_device *dev)
2399 {
2400 return 266000;
2401 }
2402
2403 static int i855_get_display_clock_speed(struct drm_device *dev)
2404 {
2405 u16 hpllcc = 0;
2406 /* Assume that the hardware is in the high speed state. This
2407 * should be the default.
2408 */
2409 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2410 case GC_CLOCK_133_200:
2411 case GC_CLOCK_100_200:
2412 return 200000;
2413 case GC_CLOCK_166_250:
2414 return 250000;
2415 case GC_CLOCK_100_133:
2416 return 133000;
2417 }
2418
2419 /* Shouldn't happen */
2420 return 0;
2421 }
2422
2423 static int i830_get_display_clock_speed(struct drm_device *dev)
2424 {
2425 return 133000;
2426 }
2427
2428 /**
2429 * Return the pipe currently connected to the panel fitter,
2430 * or -1 if the panel fitter is not present or not in use
2431 */
2432 int intel_panel_fitter_pipe (struct drm_device *dev)
2433 {
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 u32 pfit_control;
2436
2437 /* i830 doesn't have a panel fitter */
2438 if (IS_I830(dev))
2439 return -1;
2440
2441 pfit_control = I915_READ(PFIT_CONTROL);
2442
2443 /* See if the panel fitter is in use */
2444 if ((pfit_control & PFIT_ENABLE) == 0)
2445 return -1;
2446
2447 /* 965 can place panel fitter on either pipe */
2448 if (IS_I965G(dev))
2449 return (pfit_control >> 29) & 0x3;
2450
2451 /* older chips can only use pipe 1 */
2452 return 1;
2453 }
2454
2455 struct fdi_m_n {
2456 u32 tu;
2457 u32 gmch_m;
2458 u32 gmch_n;
2459 u32 link_m;
2460 u32 link_n;
2461 };
2462
2463 static void
2464 fdi_reduce_ratio(u32 *num, u32 *den)
2465 {
2466 while (*num > 0xffffff || *den > 0xffffff) {
2467 *num >>= 1;
2468 *den >>= 1;
2469 }
2470 }
2471
2472 #define DATA_N 0x800000
2473 #define LINK_N 0x80000
2474
2475 static void
2476 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2477 int link_clock, struct fdi_m_n *m_n)
2478 {
2479 u64 temp;
2480
2481 m_n->tu = 64; /* default size */
2482
2483 temp = (u64) DATA_N * pixel_clock;
2484 temp = div_u64(temp, link_clock);
2485 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2486 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2487 m_n->gmch_n = DATA_N;
2488 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2489
2490 temp = (u64) LINK_N * pixel_clock;
2491 m_n->link_m = div_u64(temp, link_clock);
2492 m_n->link_n = LINK_N;
2493 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2494 }
2495
2496
2497 struct intel_watermark_params {
2498 unsigned long fifo_size;
2499 unsigned long max_wm;
2500 unsigned long default_wm;
2501 unsigned long guard_size;
2502 unsigned long cacheline_size;
2503 };
2504
2505 /* Pineview has different values for various configs */
2506 static struct intel_watermark_params pineview_display_wm = {
2507 PINEVIEW_DISPLAY_FIFO,
2508 PINEVIEW_MAX_WM,
2509 PINEVIEW_DFT_WM,
2510 PINEVIEW_GUARD_WM,
2511 PINEVIEW_FIFO_LINE_SIZE
2512 };
2513 static struct intel_watermark_params pineview_display_hplloff_wm = {
2514 PINEVIEW_DISPLAY_FIFO,
2515 PINEVIEW_MAX_WM,
2516 PINEVIEW_DFT_HPLLOFF_WM,
2517 PINEVIEW_GUARD_WM,
2518 PINEVIEW_FIFO_LINE_SIZE
2519 };
2520 static struct intel_watermark_params pineview_cursor_wm = {
2521 PINEVIEW_CURSOR_FIFO,
2522 PINEVIEW_CURSOR_MAX_WM,
2523 PINEVIEW_CURSOR_DFT_WM,
2524 PINEVIEW_CURSOR_GUARD_WM,
2525 PINEVIEW_FIFO_LINE_SIZE,
2526 };
2527 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2528 PINEVIEW_CURSOR_FIFO,
2529 PINEVIEW_CURSOR_MAX_WM,
2530 PINEVIEW_CURSOR_DFT_WM,
2531 PINEVIEW_CURSOR_GUARD_WM,
2532 PINEVIEW_FIFO_LINE_SIZE
2533 };
2534 static struct intel_watermark_params g4x_wm_info = {
2535 G4X_FIFO_SIZE,
2536 G4X_MAX_WM,
2537 G4X_MAX_WM,
2538 2,
2539 G4X_FIFO_LINE_SIZE,
2540 };
2541 static struct intel_watermark_params i945_wm_info = {
2542 I945_FIFO_SIZE,
2543 I915_MAX_WM,
2544 1,
2545 2,
2546 I915_FIFO_LINE_SIZE
2547 };
2548 static struct intel_watermark_params i915_wm_info = {
2549 I915_FIFO_SIZE,
2550 I915_MAX_WM,
2551 1,
2552 2,
2553 I915_FIFO_LINE_SIZE
2554 };
2555 static struct intel_watermark_params i855_wm_info = {
2556 I855GM_FIFO_SIZE,
2557 I915_MAX_WM,
2558 1,
2559 2,
2560 I830_FIFO_LINE_SIZE
2561 };
2562 static struct intel_watermark_params i830_wm_info = {
2563 I830_FIFO_SIZE,
2564 I915_MAX_WM,
2565 1,
2566 2,
2567 I830_FIFO_LINE_SIZE
2568 };
2569
2570 static struct intel_watermark_params ironlake_display_wm_info = {
2571 ILK_DISPLAY_FIFO,
2572 ILK_DISPLAY_MAXWM,
2573 ILK_DISPLAY_DFTWM,
2574 2,
2575 ILK_FIFO_LINE_SIZE
2576 };
2577
2578 static struct intel_watermark_params ironlake_display_srwm_info = {
2579 ILK_DISPLAY_SR_FIFO,
2580 ILK_DISPLAY_MAX_SRWM,
2581 ILK_DISPLAY_DFT_SRWM,
2582 2,
2583 ILK_FIFO_LINE_SIZE
2584 };
2585
2586 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2587 ILK_CURSOR_SR_FIFO,
2588 ILK_CURSOR_MAX_SRWM,
2589 ILK_CURSOR_DFT_SRWM,
2590 2,
2591 ILK_FIFO_LINE_SIZE
2592 };
2593
2594 /**
2595 * intel_calculate_wm - calculate watermark level
2596 * @clock_in_khz: pixel clock
2597 * @wm: chip FIFO params
2598 * @pixel_size: display pixel size
2599 * @latency_ns: memory latency for the platform
2600 *
2601 * Calculate the watermark level (the level at which the display plane will
2602 * start fetching from memory again). Each chip has a different display
2603 * FIFO size and allocation, so the caller needs to figure that out and pass
2604 * in the correct intel_watermark_params structure.
2605 *
2606 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2607 * on the pixel size. When it reaches the watermark level, it'll start
2608 * fetching FIFO line sized based chunks from memory until the FIFO fills
2609 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2610 * will occur, and a display engine hang could result.
2611 */
2612 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2613 struct intel_watermark_params *wm,
2614 int pixel_size,
2615 unsigned long latency_ns)
2616 {
2617 long entries_required, wm_size;
2618
2619 /*
2620 * Note: we need to make sure we don't overflow for various clock &
2621 * latency values.
2622 * clocks go from a few thousand to several hundred thousand.
2623 * latency is usually a few thousand
2624 */
2625 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2626 1000;
2627 entries_required /= wm->cacheline_size;
2628
2629 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2630
2631 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2632
2633 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2634
2635 /* Don't promote wm_size to unsigned... */
2636 if (wm_size > (long)wm->max_wm)
2637 wm_size = wm->max_wm;
2638 if (wm_size <= 0)
2639 wm_size = wm->default_wm;
2640 return wm_size;
2641 }
2642
2643 struct cxsr_latency {
2644 int is_desktop;
2645 int is_ddr3;
2646 unsigned long fsb_freq;
2647 unsigned long mem_freq;
2648 unsigned long display_sr;
2649 unsigned long display_hpll_disable;
2650 unsigned long cursor_sr;
2651 unsigned long cursor_hpll_disable;
2652 };
2653
2654 static struct cxsr_latency cxsr_latency_table[] = {
2655 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2656 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2657 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2658 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2659 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2660
2661 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2662 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2663 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2664 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2665 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2666
2667 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2668 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2669 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2670 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2671 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2672
2673 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2674 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2675 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2676 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2677 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2678
2679 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2680 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2681 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2682 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2683 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2684
2685 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2686 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2687 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2688 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2689 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2690 };
2691
2692 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2693 int fsb, int mem)
2694 {
2695 int i;
2696 struct cxsr_latency *latency;
2697
2698 if (fsb == 0 || mem == 0)
2699 return NULL;
2700
2701 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2702 latency = &cxsr_latency_table[i];
2703 if (is_desktop == latency->is_desktop &&
2704 is_ddr3 == latency->is_ddr3 &&
2705 fsb == latency->fsb_freq && mem == latency->mem_freq)
2706 return latency;
2707 }
2708
2709 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2710
2711 return NULL;
2712 }
2713
2714 static void pineview_disable_cxsr(struct drm_device *dev)
2715 {
2716 struct drm_i915_private *dev_priv = dev->dev_private;
2717 u32 reg;
2718
2719 /* deactivate cxsr */
2720 reg = I915_READ(DSPFW3);
2721 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2722 I915_WRITE(DSPFW3, reg);
2723 DRM_INFO("Big FIFO is disabled\n");
2724 }
2725
2726 /*
2727 * Latency for FIFO fetches is dependent on several factors:
2728 * - memory configuration (speed, channels)
2729 * - chipset
2730 * - current MCH state
2731 * It can be fairly high in some situations, so here we assume a fairly
2732 * pessimal value. It's a tradeoff between extra memory fetches (if we
2733 * set this value too high, the FIFO will fetch frequently to stay full)
2734 * and power consumption (set it too low to save power and we might see
2735 * FIFO underruns and display "flicker").
2736 *
2737 * A value of 5us seems to be a good balance; safe for very low end
2738 * platforms but not overly aggressive on lower latency configs.
2739 */
2740 static const int latency_ns = 5000;
2741
2742 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2743 {
2744 struct drm_i915_private *dev_priv = dev->dev_private;
2745 uint32_t dsparb = I915_READ(DSPARB);
2746 int size;
2747
2748 if (plane == 0)
2749 size = dsparb & 0x7f;
2750 else
2751 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2752 (dsparb & 0x7f);
2753
2754 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2755 plane ? "B" : "A", size);
2756
2757 return size;
2758 }
2759
2760 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2761 {
2762 struct drm_i915_private *dev_priv = dev->dev_private;
2763 uint32_t dsparb = I915_READ(DSPARB);
2764 int size;
2765
2766 if (plane == 0)
2767 size = dsparb & 0x1ff;
2768 else
2769 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2770 (dsparb & 0x1ff);
2771 size >>= 1; /* Convert to cachelines */
2772
2773 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2774 plane ? "B" : "A", size);
2775
2776 return size;
2777 }
2778
2779 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2780 {
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 uint32_t dsparb = I915_READ(DSPARB);
2783 int size;
2784
2785 size = dsparb & 0x7f;
2786 size >>= 2; /* Convert to cachelines */
2787
2788 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2789 plane ? "B" : "A",
2790 size);
2791
2792 return size;
2793 }
2794
2795 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2796 {
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2798 uint32_t dsparb = I915_READ(DSPARB);
2799 int size;
2800
2801 size = dsparb & 0x7f;
2802 size >>= 1; /* Convert to cachelines */
2803
2804 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2805 plane ? "B" : "A", size);
2806
2807 return size;
2808 }
2809
2810 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2811 int planeb_clock, int sr_hdisplay, int pixel_size)
2812 {
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 u32 reg;
2815 unsigned long wm;
2816 struct cxsr_latency *latency;
2817 int sr_clock;
2818
2819 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2820 dev_priv->fsb_freq, dev_priv->mem_freq);
2821 if (!latency) {
2822 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2823 pineview_disable_cxsr(dev);
2824 return;
2825 }
2826
2827 if (!planea_clock || !planeb_clock) {
2828 sr_clock = planea_clock ? planea_clock : planeb_clock;
2829
2830 /* Display SR */
2831 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2832 pixel_size, latency->display_sr);
2833 reg = I915_READ(DSPFW1);
2834 reg &= ~DSPFW_SR_MASK;
2835 reg |= wm << DSPFW_SR_SHIFT;
2836 I915_WRITE(DSPFW1, reg);
2837 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2838
2839 /* cursor SR */
2840 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2841 pixel_size, latency->cursor_sr);
2842 reg = I915_READ(DSPFW3);
2843 reg &= ~DSPFW_CURSOR_SR_MASK;
2844 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2845 I915_WRITE(DSPFW3, reg);
2846
2847 /* Display HPLL off SR */
2848 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2849 pixel_size, latency->display_hpll_disable);
2850 reg = I915_READ(DSPFW3);
2851 reg &= ~DSPFW_HPLL_SR_MASK;
2852 reg |= wm & DSPFW_HPLL_SR_MASK;
2853 I915_WRITE(DSPFW3, reg);
2854
2855 /* cursor HPLL off SR */
2856 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2857 pixel_size, latency->cursor_hpll_disable);
2858 reg = I915_READ(DSPFW3);
2859 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2860 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2861 I915_WRITE(DSPFW3, reg);
2862 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2863
2864 /* activate cxsr */
2865 reg = I915_READ(DSPFW3);
2866 reg |= PINEVIEW_SELF_REFRESH_EN;
2867 I915_WRITE(DSPFW3, reg);
2868 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2869 } else {
2870 pineview_disable_cxsr(dev);
2871 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2872 }
2873 }
2874
2875 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2876 int planeb_clock, int sr_hdisplay, int pixel_size)
2877 {
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 int total_size, cacheline_size;
2880 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2881 struct intel_watermark_params planea_params, planeb_params;
2882 unsigned long line_time_us;
2883 int sr_clock, sr_entries = 0, entries_required;
2884
2885 /* Create copies of the base settings for each pipe */
2886 planea_params = planeb_params = g4x_wm_info;
2887
2888 /* Grab a couple of global values before we overwrite them */
2889 total_size = planea_params.fifo_size;
2890 cacheline_size = planea_params.cacheline_size;
2891
2892 /*
2893 * Note: we need to make sure we don't overflow for various clock &
2894 * latency values.
2895 * clocks go from a few thousand to several hundred thousand.
2896 * latency is usually a few thousand
2897 */
2898 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2899 1000;
2900 entries_required /= G4X_FIFO_LINE_SIZE;
2901 planea_wm = entries_required + planea_params.guard_size;
2902
2903 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2904 1000;
2905 entries_required /= G4X_FIFO_LINE_SIZE;
2906 planeb_wm = entries_required + planeb_params.guard_size;
2907
2908 cursora_wm = cursorb_wm = 16;
2909 cursor_sr = 32;
2910
2911 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2912
2913 /* Calc sr entries for one plane configs */
2914 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2915 /* self-refresh has much higher latency */
2916 static const int sr_latency_ns = 12000;
2917
2918 sr_clock = planea_clock ? planea_clock : planeb_clock;
2919 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2920
2921 /* Use ns/us then divide to preserve precision */
2922 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2923 pixel_size * sr_hdisplay) / 1000;
2924 sr_entries = roundup(sr_entries / cacheline_size, 1);
2925 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2926 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2927 } else {
2928 /* Turn off self refresh if both pipes are enabled */
2929 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2930 & ~FW_BLC_SELF_EN);
2931 }
2932
2933 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2934 planea_wm, planeb_wm, sr_entries);
2935
2936 planea_wm &= 0x3f;
2937 planeb_wm &= 0x3f;
2938
2939 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2940 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2941 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2942 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2943 (cursora_wm << DSPFW_CURSORA_SHIFT));
2944 /* HPLL off in SR has some issues on G4x... disable it */
2945 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2946 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2947 }
2948
2949 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2950 int planeb_clock, int sr_hdisplay, int pixel_size)
2951 {
2952 struct drm_i915_private *dev_priv = dev->dev_private;
2953 unsigned long line_time_us;
2954 int sr_clock, sr_entries, srwm = 1;
2955
2956 /* Calc sr entries for one plane configs */
2957 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2958 /* self-refresh has much higher latency */
2959 static const int sr_latency_ns = 12000;
2960
2961 sr_clock = planea_clock ? planea_clock : planeb_clock;
2962 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2963
2964 /* Use ns/us then divide to preserve precision */
2965 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2966 pixel_size * sr_hdisplay) / 1000;
2967 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2968 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2969 srwm = I945_FIFO_SIZE - sr_entries;
2970 if (srwm < 0)
2971 srwm = 1;
2972 srwm &= 0x3f;
2973 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2974 } else {
2975 /* Turn off self refresh if both pipes are enabled */
2976 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2977 & ~FW_BLC_SELF_EN);
2978 }
2979
2980 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2981 srwm);
2982
2983 /* 965 has limitations... */
2984 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2985 (8 << 0));
2986 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2987 }
2988
2989 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2990 int planeb_clock, int sr_hdisplay, int pixel_size)
2991 {
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2993 uint32_t fwater_lo;
2994 uint32_t fwater_hi;
2995 int total_size, cacheline_size, cwm, srwm = 1;
2996 int planea_wm, planeb_wm;
2997 struct intel_watermark_params planea_params, planeb_params;
2998 unsigned long line_time_us;
2999 int sr_clock, sr_entries = 0;
3000
3001 /* Create copies of the base settings for each pipe */
3002 if (IS_I965GM(dev) || IS_I945GM(dev))
3003 planea_params = planeb_params = i945_wm_info;
3004 else if (IS_I9XX(dev))
3005 planea_params = planeb_params = i915_wm_info;
3006 else
3007 planea_params = planeb_params = i855_wm_info;
3008
3009 /* Grab a couple of global values before we overwrite them */
3010 total_size = planea_params.fifo_size;
3011 cacheline_size = planea_params.cacheline_size;
3012
3013 /* Update per-plane FIFO sizes */
3014 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3015 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3016
3017 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3018 pixel_size, latency_ns);
3019 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3020 pixel_size, latency_ns);
3021 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3022
3023 /*
3024 * Overlay gets an aggressive default since video jitter is bad.
3025 */
3026 cwm = 2;
3027
3028 /* Calc sr entries for one plane configs */
3029 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3030 (!planea_clock || !planeb_clock)) {
3031 /* self-refresh has much higher latency */
3032 static const int sr_latency_ns = 6000;
3033
3034 sr_clock = planea_clock ? planea_clock : planeb_clock;
3035 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3036
3037 /* Use ns/us then divide to preserve precision */
3038 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3039 pixel_size * sr_hdisplay) / 1000;
3040 sr_entries = roundup(sr_entries / cacheline_size, 1);
3041 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3042 srwm = total_size - sr_entries;
3043 if (srwm < 0)
3044 srwm = 1;
3045
3046 if (IS_I945G(dev) || IS_I945GM(dev))
3047 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3048 else if (IS_I915GM(dev)) {
3049 /* 915M has a smaller SRWM field */
3050 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3051 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3052 }
3053 } else {
3054 /* Turn off self refresh if both pipes are enabled */
3055 if (IS_I945G(dev) || IS_I945GM(dev)) {
3056 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3057 & ~FW_BLC_SELF_EN);
3058 } else if (IS_I915GM(dev)) {
3059 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3060 }
3061 }
3062
3063 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3064 planea_wm, planeb_wm, cwm, srwm);
3065
3066 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3067 fwater_hi = (cwm & 0x1f);
3068
3069 /* Set request length to 8 cachelines per fetch */
3070 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3071 fwater_hi = fwater_hi | (1 << 8);
3072
3073 I915_WRITE(FW_BLC, fwater_lo);
3074 I915_WRITE(FW_BLC2, fwater_hi);
3075 }
3076
3077 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3078 int unused2, int pixel_size)
3079 {
3080 struct drm_i915_private *dev_priv = dev->dev_private;
3081 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3082 int planea_wm;
3083
3084 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3085
3086 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3087 pixel_size, latency_ns);
3088 fwater_lo |= (3<<8) | planea_wm;
3089
3090 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3091
3092 I915_WRITE(FW_BLC, fwater_lo);
3093 }
3094
3095 #define ILK_LP0_PLANE_LATENCY 700
3096
3097 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3098 int planeb_clock, int sr_hdisplay, int pixel_size)
3099 {
3100 struct drm_i915_private *dev_priv = dev->dev_private;
3101 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3102 int sr_wm, cursor_wm;
3103 unsigned long line_time_us;
3104 int sr_clock, entries_required;
3105 u32 reg_value;
3106
3107 /* Calculate and update the watermark for plane A */
3108 if (planea_clock) {
3109 entries_required = ((planea_clock / 1000) * pixel_size *
3110 ILK_LP0_PLANE_LATENCY) / 1000;
3111 entries_required = DIV_ROUND_UP(entries_required,
3112 ironlake_display_wm_info.cacheline_size);
3113 planea_wm = entries_required +
3114 ironlake_display_wm_info.guard_size;
3115
3116 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3117 planea_wm = ironlake_display_wm_info.max_wm;
3118
3119 cursora_wm = 16;
3120 reg_value = I915_READ(WM0_PIPEA_ILK);
3121 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3122 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3123 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3124 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3125 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3126 "cursor: %d\n", planea_wm, cursora_wm);
3127 }
3128 /* Calculate and update the watermark for plane B */
3129 if (planeb_clock) {
3130 entries_required = ((planeb_clock / 1000) * pixel_size *
3131 ILK_LP0_PLANE_LATENCY) / 1000;
3132 entries_required = DIV_ROUND_UP(entries_required,
3133 ironlake_display_wm_info.cacheline_size);
3134 planeb_wm = entries_required +
3135 ironlake_display_wm_info.guard_size;
3136
3137 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3138 planeb_wm = ironlake_display_wm_info.max_wm;
3139
3140 cursorb_wm = 16;
3141 reg_value = I915_READ(WM0_PIPEB_ILK);
3142 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3143 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3144 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3145 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3146 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3147 "cursor: %d\n", planeb_wm, cursorb_wm);
3148 }
3149
3150 /*
3151 * Calculate and update the self-refresh watermark only when one
3152 * display plane is used.
3153 */
3154 if (!planea_clock || !planeb_clock) {
3155 int line_count;
3156 /* Read the self-refresh latency. The unit is 0.5us */
3157 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3158
3159 sr_clock = planea_clock ? planea_clock : planeb_clock;
3160 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3161
3162 /* Use ns/us then divide to preserve precision */
3163 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3164 / 1000;
3165
3166 /* calculate the self-refresh watermark for display plane */
3167 entries_required = line_count * sr_hdisplay * pixel_size;
3168 entries_required = DIV_ROUND_UP(entries_required,
3169 ironlake_display_srwm_info.cacheline_size);
3170 sr_wm = entries_required +
3171 ironlake_display_srwm_info.guard_size;
3172
3173 /* calculate the self-refresh watermark for display cursor */
3174 entries_required = line_count * pixel_size * 64;
3175 entries_required = DIV_ROUND_UP(entries_required,
3176 ironlake_cursor_srwm_info.cacheline_size);
3177 cursor_wm = entries_required +
3178 ironlake_cursor_srwm_info.guard_size;
3179
3180 /* configure watermark and enable self-refresh */
3181 reg_value = I915_READ(WM1_LP_ILK);
3182 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3183 WM1_LP_CURSOR_MASK);
3184 reg_value |= WM1_LP_SR_EN |
3185 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3186 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3187
3188 I915_WRITE(WM1_LP_ILK, reg_value);
3189 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3190 "cursor %d\n", sr_wm, cursor_wm);
3191
3192 } else {
3193 /* Turn off self refresh if both pipes are enabled */
3194 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3195 }
3196 }
3197 /**
3198 * intel_update_watermarks - update FIFO watermark values based on current modes
3199 *
3200 * Calculate watermark values for the various WM regs based on current mode
3201 * and plane configuration.
3202 *
3203 * There are several cases to deal with here:
3204 * - normal (i.e. non-self-refresh)
3205 * - self-refresh (SR) mode
3206 * - lines are large relative to FIFO size (buffer can hold up to 2)
3207 * - lines are small relative to FIFO size (buffer can hold more than 2
3208 * lines), so need to account for TLB latency
3209 *
3210 * The normal calculation is:
3211 * watermark = dotclock * bytes per pixel * latency
3212 * where latency is platform & configuration dependent (we assume pessimal
3213 * values here).
3214 *
3215 * The SR calculation is:
3216 * watermark = (trunc(latency/line time)+1) * surface width *
3217 * bytes per pixel
3218 * where
3219 * line time = htotal / dotclock
3220 * and latency is assumed to be high, as above.
3221 *
3222 * The final value programmed to the register should always be rounded up,
3223 * and include an extra 2 entries to account for clock crossings.
3224 *
3225 * We don't use the sprite, so we can ignore that. And on Crestline we have
3226 * to set the non-SR watermarks to 8.
3227 */
3228 static void intel_update_watermarks(struct drm_device *dev)
3229 {
3230 struct drm_i915_private *dev_priv = dev->dev_private;
3231 struct drm_crtc *crtc;
3232 struct intel_crtc *intel_crtc;
3233 int sr_hdisplay = 0;
3234 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3235 int enabled = 0, pixel_size = 0;
3236
3237 if (!dev_priv->display.update_wm)
3238 return;
3239
3240 /* Get the clock config from both planes */
3241 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3242 intel_crtc = to_intel_crtc(crtc);
3243 if (crtc->enabled) {
3244 enabled++;
3245 if (intel_crtc->plane == 0) {
3246 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3247 intel_crtc->pipe, crtc->mode.clock);
3248 planea_clock = crtc->mode.clock;
3249 } else {
3250 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3251 intel_crtc->pipe, crtc->mode.clock);
3252 planeb_clock = crtc->mode.clock;
3253 }
3254 sr_hdisplay = crtc->mode.hdisplay;
3255 sr_clock = crtc->mode.clock;
3256 if (crtc->fb)
3257 pixel_size = crtc->fb->bits_per_pixel / 8;
3258 else
3259 pixel_size = 4; /* by default */
3260 }
3261 }
3262
3263 if (enabled <= 0)
3264 return;
3265
3266 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3267 sr_hdisplay, pixel_size);
3268 }
3269
3270 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3271 struct drm_display_mode *mode,
3272 struct drm_display_mode *adjusted_mode,
3273 int x, int y,
3274 struct drm_framebuffer *old_fb)
3275 {
3276 struct drm_device *dev = crtc->dev;
3277 struct drm_i915_private *dev_priv = dev->dev_private;
3278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3279 int pipe = intel_crtc->pipe;
3280 int plane = intel_crtc->plane;
3281 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3282 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3283 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3284 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3285 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3286 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3287 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3288 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3289 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3290 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3291 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3292 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3293 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3294 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3295 int refclk, num_connectors = 0;
3296 intel_clock_t clock, reduced_clock;
3297 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3298 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3299 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3300 bool is_edp = false;
3301 struct drm_mode_config *mode_config = &dev->mode_config;
3302 struct drm_encoder *encoder;
3303 struct intel_encoder *intel_encoder = NULL;
3304 const intel_limit_t *limit;
3305 int ret;
3306 struct fdi_m_n m_n = {0};
3307 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3308 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3309 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3310 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3311 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3312 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3313 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3314 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3315 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3316 int lvds_reg = LVDS;
3317 u32 temp;
3318 int sdvo_pixel_multiply;
3319 int target_clock;
3320
3321 drm_vblank_pre_modeset(dev, pipe);
3322
3323 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3324
3325 if (!encoder || encoder->crtc != crtc)
3326 continue;
3327
3328 intel_encoder = enc_to_intel_encoder(encoder);
3329
3330 switch (intel_encoder->type) {
3331 case INTEL_OUTPUT_LVDS:
3332 is_lvds = true;
3333 break;
3334 case INTEL_OUTPUT_SDVO:
3335 case INTEL_OUTPUT_HDMI:
3336 is_sdvo = true;
3337 if (intel_encoder->needs_tv_clock)
3338 is_tv = true;
3339 break;
3340 case INTEL_OUTPUT_DVO:
3341 is_dvo = true;
3342 break;
3343 case INTEL_OUTPUT_TVOUT:
3344 is_tv = true;
3345 break;
3346 case INTEL_OUTPUT_ANALOG:
3347 is_crt = true;
3348 break;
3349 case INTEL_OUTPUT_DISPLAYPORT:
3350 is_dp = true;
3351 break;
3352 case INTEL_OUTPUT_EDP:
3353 is_edp = true;
3354 break;
3355 }
3356
3357 num_connectors++;
3358 }
3359
3360 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3361 refclk = dev_priv->lvds_ssc_freq * 1000;
3362 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3363 refclk / 1000);
3364 } else if (IS_I9XX(dev)) {
3365 refclk = 96000;
3366 if (HAS_PCH_SPLIT(dev))
3367 refclk = 120000; /* 120Mhz refclk */
3368 } else {
3369 refclk = 48000;
3370 }
3371
3372
3373 /*
3374 * Returns a set of divisors for the desired target clock with the given
3375 * refclk, or FALSE. The returned values represent the clock equation:
3376 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3377 */
3378 limit = intel_limit(crtc);
3379 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3380 if (!ok) {
3381 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3382 drm_vblank_post_modeset(dev, pipe);
3383 return -EINVAL;
3384 }
3385
3386 if (is_lvds && dev_priv->lvds_downclock_avail) {
3387 has_reduced_clock = limit->find_pll(limit, crtc,
3388 dev_priv->lvds_downclock,
3389 refclk,
3390 &reduced_clock);
3391 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3392 /*
3393 * If the different P is found, it means that we can't
3394 * switch the display clock by using the FP0/FP1.
3395 * In such case we will disable the LVDS downclock
3396 * feature.
3397 */
3398 DRM_DEBUG_KMS("Different P is found for "
3399 "LVDS clock/downclock\n");
3400 has_reduced_clock = 0;
3401 }
3402 }
3403 /* SDVO TV has fixed PLL values depend on its clock range,
3404 this mirrors vbios setting. */
3405 if (is_sdvo && is_tv) {
3406 if (adjusted_mode->clock >= 100000
3407 && adjusted_mode->clock < 140500) {
3408 clock.p1 = 2;
3409 clock.p2 = 10;
3410 clock.n = 3;
3411 clock.m1 = 16;
3412 clock.m2 = 8;
3413 } else if (adjusted_mode->clock >= 140500
3414 && adjusted_mode->clock <= 200000) {
3415 clock.p1 = 1;
3416 clock.p2 = 10;
3417 clock.n = 6;
3418 clock.m1 = 12;
3419 clock.m2 = 8;
3420 }
3421 }
3422
3423 /* FDI link */
3424 if (HAS_PCH_SPLIT(dev)) {
3425 int lane = 0, link_bw, bpp;
3426 /* eDP doesn't require FDI link, so just set DP M/N
3427 according to current link config */
3428 if (is_edp) {
3429 target_clock = mode->clock;
3430 intel_edp_link_config(intel_encoder,
3431 &lane, &link_bw);
3432 } else {
3433 /* DP over FDI requires target mode clock
3434 instead of link clock */
3435 if (is_dp)
3436 target_clock = mode->clock;
3437 else
3438 target_clock = adjusted_mode->clock;
3439 link_bw = 270000;
3440 }
3441
3442 /* determine panel color depth */
3443 temp = I915_READ(pipeconf_reg);
3444 temp &= ~PIPE_BPC_MASK;
3445 if (is_lvds) {
3446 int lvds_reg = I915_READ(PCH_LVDS);
3447 /* the BPC will be 6 if it is 18-bit LVDS panel */
3448 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3449 temp |= PIPE_8BPC;
3450 else
3451 temp |= PIPE_6BPC;
3452 } else if (is_edp) {
3453 switch (dev_priv->edp_bpp/3) {
3454 case 8:
3455 temp |= PIPE_8BPC;
3456 break;
3457 case 10:
3458 temp |= PIPE_10BPC;
3459 break;
3460 case 6:
3461 temp |= PIPE_6BPC;
3462 break;
3463 case 12:
3464 temp |= PIPE_12BPC;
3465 break;
3466 }
3467 } else
3468 temp |= PIPE_8BPC;
3469 I915_WRITE(pipeconf_reg, temp);
3470 I915_READ(pipeconf_reg);
3471
3472 switch (temp & PIPE_BPC_MASK) {
3473 case PIPE_8BPC:
3474 bpp = 24;
3475 break;
3476 case PIPE_10BPC:
3477 bpp = 30;
3478 break;
3479 case PIPE_6BPC:
3480 bpp = 18;
3481 break;
3482 case PIPE_12BPC:
3483 bpp = 36;
3484 break;
3485 default:
3486 DRM_ERROR("unknown pipe bpc value\n");
3487 bpp = 24;
3488 }
3489
3490 if (!lane) {
3491 /*
3492 * Account for spread spectrum to avoid
3493 * oversubscribing the link. Max center spread
3494 * is 2.5%; use 5% for safety's sake.
3495 */
3496 u32 bps = target_clock * bpp * 21 / 20;
3497 lane = bps / (link_bw * 8) + 1;
3498 }
3499
3500 intel_crtc->fdi_lanes = lane;
3501
3502 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3503 }
3504
3505 /* Ironlake: try to setup display ref clock before DPLL
3506 * enabling. This is only under driver's control after
3507 * PCH B stepping, previous chipset stepping should be
3508 * ignoring this setting.
3509 */
3510 if (HAS_PCH_SPLIT(dev)) {
3511 temp = I915_READ(PCH_DREF_CONTROL);
3512 /* Always enable nonspread source */
3513 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3514 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3515 I915_WRITE(PCH_DREF_CONTROL, temp);
3516 POSTING_READ(PCH_DREF_CONTROL);
3517
3518 temp &= ~DREF_SSC_SOURCE_MASK;
3519 temp |= DREF_SSC_SOURCE_ENABLE;
3520 I915_WRITE(PCH_DREF_CONTROL, temp);
3521 POSTING_READ(PCH_DREF_CONTROL);
3522
3523 udelay(200);
3524
3525 if (is_edp) {
3526 if (dev_priv->lvds_use_ssc) {
3527 temp |= DREF_SSC1_ENABLE;
3528 I915_WRITE(PCH_DREF_CONTROL, temp);
3529 POSTING_READ(PCH_DREF_CONTROL);
3530
3531 udelay(200);
3532
3533 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3534 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3535 I915_WRITE(PCH_DREF_CONTROL, temp);
3536 POSTING_READ(PCH_DREF_CONTROL);
3537 } else {
3538 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3539 I915_WRITE(PCH_DREF_CONTROL, temp);
3540 POSTING_READ(PCH_DREF_CONTROL);
3541 }
3542 }
3543 }
3544
3545 if (IS_PINEVIEW(dev)) {
3546 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3547 if (has_reduced_clock)
3548 fp2 = (1 << reduced_clock.n) << 16 |
3549 reduced_clock.m1 << 8 | reduced_clock.m2;
3550 } else {
3551 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3552 if (has_reduced_clock)
3553 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3554 reduced_clock.m2;
3555 }
3556
3557 if (!HAS_PCH_SPLIT(dev))
3558 dpll = DPLL_VGA_MODE_DIS;
3559
3560 if (IS_I9XX(dev)) {
3561 if (is_lvds)
3562 dpll |= DPLLB_MODE_LVDS;
3563 else
3564 dpll |= DPLLB_MODE_DAC_SERIAL;
3565 if (is_sdvo) {
3566 dpll |= DPLL_DVO_HIGH_SPEED;
3567 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3568 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3569 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3570 else if (HAS_PCH_SPLIT(dev))
3571 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3572 }
3573 if (is_dp)
3574 dpll |= DPLL_DVO_HIGH_SPEED;
3575
3576 /* compute bitmask from p1 value */
3577 if (IS_PINEVIEW(dev))
3578 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3579 else {
3580 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3581 /* also FPA1 */
3582 if (HAS_PCH_SPLIT(dev))
3583 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3584 if (IS_G4X(dev) && has_reduced_clock)
3585 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3586 }
3587 switch (clock.p2) {
3588 case 5:
3589 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3590 break;
3591 case 7:
3592 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3593 break;
3594 case 10:
3595 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3596 break;
3597 case 14:
3598 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3599 break;
3600 }
3601 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3602 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3603 } else {
3604 if (is_lvds) {
3605 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3606 } else {
3607 if (clock.p1 == 2)
3608 dpll |= PLL_P1_DIVIDE_BY_TWO;
3609 else
3610 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3611 if (clock.p2 == 4)
3612 dpll |= PLL_P2_DIVIDE_BY_4;
3613 }
3614 }
3615
3616 if (is_sdvo && is_tv)
3617 dpll |= PLL_REF_INPUT_TVCLKINBC;
3618 else if (is_tv)
3619 /* XXX: just matching BIOS for now */
3620 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3621 dpll |= 3;
3622 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3623 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3624 else
3625 dpll |= PLL_REF_INPUT_DREFCLK;
3626
3627 /* setup pipeconf */
3628 pipeconf = I915_READ(pipeconf_reg);
3629
3630 /* Set up the display plane register */
3631 dspcntr = DISPPLANE_GAMMA_ENABLE;
3632
3633 /* Ironlake's plane is forced to pipe, bit 24 is to
3634 enable color space conversion */
3635 if (!HAS_PCH_SPLIT(dev)) {
3636 if (pipe == 0)
3637 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3638 else
3639 dspcntr |= DISPPLANE_SEL_PIPE_B;
3640 }
3641
3642 if (pipe == 0 && !IS_I965G(dev)) {
3643 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3644 * core speed.
3645 *
3646 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3647 * pipe == 0 check?
3648 */
3649 if (mode->clock >
3650 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3651 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3652 else
3653 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3654 }
3655
3656 /* Disable the panel fitter if it was on our pipe */
3657 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3658 I915_WRITE(PFIT_CONTROL, 0);
3659
3660 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3661 drm_mode_debug_printmodeline(mode);
3662
3663 /* assign to Ironlake registers */
3664 if (HAS_PCH_SPLIT(dev)) {
3665 fp_reg = pch_fp_reg;
3666 dpll_reg = pch_dpll_reg;
3667 }
3668
3669 if (is_edp) {
3670 ironlake_disable_pll_edp(crtc);
3671 } else if ((dpll & DPLL_VCO_ENABLE)) {
3672 I915_WRITE(fp_reg, fp);
3673 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3674 I915_READ(dpll_reg);
3675 udelay(150);
3676 }
3677
3678 /* enable transcoder DPLL */
3679 if (HAS_PCH_CPT(dev)) {
3680 temp = I915_READ(PCH_DPLL_SEL);
3681 if (trans_dpll_sel == 0)
3682 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3683 else
3684 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3685 I915_WRITE(PCH_DPLL_SEL, temp);
3686 I915_READ(PCH_DPLL_SEL);
3687 udelay(150);
3688 }
3689
3690 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3691 * This is an exception to the general rule that mode_set doesn't turn
3692 * things on.
3693 */
3694 if (is_lvds) {
3695 u32 lvds;
3696
3697 if (HAS_PCH_SPLIT(dev))
3698 lvds_reg = PCH_LVDS;
3699
3700 lvds = I915_READ(lvds_reg);
3701 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3702 if (pipe == 1) {
3703 if (HAS_PCH_CPT(dev))
3704 lvds |= PORT_TRANS_B_SEL_CPT;
3705 else
3706 lvds |= LVDS_PIPEB_SELECT;
3707 } else {
3708 if (HAS_PCH_CPT(dev))
3709 lvds &= ~PORT_TRANS_SEL_MASK;
3710 else
3711 lvds &= ~LVDS_PIPEB_SELECT;
3712 }
3713 /* set the corresponsding LVDS_BORDER bit */
3714 lvds |= dev_priv->lvds_border_bits;
3715 /* Set the B0-B3 data pairs corresponding to whether we're going to
3716 * set the DPLLs for dual-channel mode or not.
3717 */
3718 if (clock.p2 == 7)
3719 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3720 else
3721 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3722
3723 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3724 * appropriately here, but we need to look more thoroughly into how
3725 * panels behave in the two modes.
3726 */
3727 /* set the dithering flag */
3728 if (IS_I965G(dev)) {
3729 if (dev_priv->lvds_dither) {
3730 if (HAS_PCH_SPLIT(dev)) {
3731 pipeconf |= PIPE_ENABLE_DITHER;
3732 pipeconf |= PIPE_DITHER_TYPE_ST01;
3733 } else
3734 lvds |= LVDS_ENABLE_DITHER;
3735 } else {
3736 if (HAS_PCH_SPLIT(dev)) {
3737 pipeconf &= ~PIPE_ENABLE_DITHER;
3738 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3739 } else
3740 lvds &= ~LVDS_ENABLE_DITHER;
3741 }
3742 }
3743 I915_WRITE(lvds_reg, lvds);
3744 I915_READ(lvds_reg);
3745 }
3746 if (is_dp)
3747 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3748 else if (HAS_PCH_SPLIT(dev)) {
3749 /* For non-DP output, clear any trans DP clock recovery setting.*/
3750 if (pipe == 0) {
3751 I915_WRITE(TRANSA_DATA_M1, 0);
3752 I915_WRITE(TRANSA_DATA_N1, 0);
3753 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3754 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3755 } else {
3756 I915_WRITE(TRANSB_DATA_M1, 0);
3757 I915_WRITE(TRANSB_DATA_N1, 0);
3758 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3759 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3760 }
3761 }
3762
3763 if (!is_edp) {
3764 I915_WRITE(fp_reg, fp);
3765 I915_WRITE(dpll_reg, dpll);
3766 I915_READ(dpll_reg);
3767 /* Wait for the clocks to stabilize. */
3768 udelay(150);
3769
3770 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3771 if (is_sdvo) {
3772 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3773 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3774 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3775 } else
3776 I915_WRITE(dpll_md_reg, 0);
3777 } else {
3778 /* write it again -- the BIOS does, after all */
3779 I915_WRITE(dpll_reg, dpll);
3780 }
3781 I915_READ(dpll_reg);
3782 /* Wait for the clocks to stabilize. */
3783 udelay(150);
3784 }
3785
3786 if (is_lvds && has_reduced_clock && i915_powersave) {
3787 I915_WRITE(fp_reg + 4, fp2);
3788 intel_crtc->lowfreq_avail = true;
3789 if (HAS_PIPE_CXSR(dev)) {
3790 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3791 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3792 }
3793 } else {
3794 I915_WRITE(fp_reg + 4, fp);
3795 intel_crtc->lowfreq_avail = false;
3796 if (HAS_PIPE_CXSR(dev)) {
3797 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3798 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3799 }
3800 }
3801
3802 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3803 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3804 /* the chip adds 2 halflines automatically */
3805 adjusted_mode->crtc_vdisplay -= 1;
3806 adjusted_mode->crtc_vtotal -= 1;
3807 adjusted_mode->crtc_vblank_start -= 1;
3808 adjusted_mode->crtc_vblank_end -= 1;
3809 adjusted_mode->crtc_vsync_end -= 1;
3810 adjusted_mode->crtc_vsync_start -= 1;
3811 } else
3812 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
3813
3814 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3815 ((adjusted_mode->crtc_htotal - 1) << 16));
3816 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3817 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3818 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3819 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3820 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3821 ((adjusted_mode->crtc_vtotal - 1) << 16));
3822 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3823 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3824 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3825 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3826 /* pipesrc and dspsize control the size that is scaled from, which should
3827 * always be the user's requested size.
3828 */
3829 if (!HAS_PCH_SPLIT(dev)) {
3830 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3831 (mode->hdisplay - 1));
3832 I915_WRITE(dsppos_reg, 0);
3833 }
3834 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3835
3836 if (HAS_PCH_SPLIT(dev)) {
3837 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3838 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3839 I915_WRITE(link_m1_reg, m_n.link_m);
3840 I915_WRITE(link_n1_reg, m_n.link_n);
3841
3842 if (is_edp) {
3843 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3844 } else {
3845 /* enable FDI RX PLL too */
3846 temp = I915_READ(fdi_rx_reg);
3847 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3848 I915_READ(fdi_rx_reg);
3849 udelay(200);
3850
3851 /* enable FDI TX PLL too */
3852 temp = I915_READ(fdi_tx_reg);
3853 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3854 I915_READ(fdi_tx_reg);
3855
3856 /* enable FDI RX PCDCLK */
3857 temp = I915_READ(fdi_rx_reg);
3858 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3859 I915_READ(fdi_rx_reg);
3860 udelay(200);
3861 }
3862 }
3863
3864 I915_WRITE(pipeconf_reg, pipeconf);
3865 I915_READ(pipeconf_reg);
3866
3867 intel_wait_for_vblank(dev);
3868
3869 if (IS_IRONLAKE(dev)) {
3870 /* enable address swizzle for tiling buffer */
3871 temp = I915_READ(DISP_ARB_CTL);
3872 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3873 }
3874
3875 I915_WRITE(dspcntr_reg, dspcntr);
3876
3877 /* Flush the plane changes */
3878 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3879
3880 if ((IS_I965G(dev) || plane == 0))
3881 intel_update_fbc(crtc, &crtc->mode);
3882
3883 intel_update_watermarks(dev);
3884
3885 drm_vblank_post_modeset(dev, pipe);
3886
3887 return ret;
3888 }
3889
3890 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3891 void intel_crtc_load_lut(struct drm_crtc *crtc)
3892 {
3893 struct drm_device *dev = crtc->dev;
3894 struct drm_i915_private *dev_priv = dev->dev_private;
3895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3896 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3897 int i;
3898
3899 /* The clocks have to be on to load the palette. */
3900 if (!crtc->enabled)
3901 return;
3902
3903 /* use legacy palette for Ironlake */
3904 if (HAS_PCH_SPLIT(dev))
3905 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3906 LGC_PALETTE_B;
3907
3908 for (i = 0; i < 256; i++) {
3909 I915_WRITE(palreg + 4 * i,
3910 (intel_crtc->lut_r[i] << 16) |
3911 (intel_crtc->lut_g[i] << 8) |
3912 intel_crtc->lut_b[i]);
3913 }
3914 }
3915
3916 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3917 struct drm_file *file_priv,
3918 uint32_t handle,
3919 uint32_t width, uint32_t height)
3920 {
3921 struct drm_device *dev = crtc->dev;
3922 struct drm_i915_private *dev_priv = dev->dev_private;
3923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3924 struct drm_gem_object *bo;
3925 struct drm_i915_gem_object *obj_priv;
3926 int pipe = intel_crtc->pipe;
3927 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3928 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3929 uint32_t temp = I915_READ(control);
3930 size_t addr;
3931 int ret;
3932
3933 DRM_DEBUG_KMS("\n");
3934
3935 /* if we want to turn off the cursor ignore width and height */
3936 if (!handle) {
3937 DRM_DEBUG_KMS("cursor off\n");
3938 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3939 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3940 temp |= CURSOR_MODE_DISABLE;
3941 } else {
3942 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3943 }
3944 addr = 0;
3945 bo = NULL;
3946 mutex_lock(&dev->struct_mutex);
3947 goto finish;
3948 }
3949
3950 /* Currently we only support 64x64 cursors */
3951 if (width != 64 || height != 64) {
3952 DRM_ERROR("we currently only support 64x64 cursors\n");
3953 return -EINVAL;
3954 }
3955
3956 bo = drm_gem_object_lookup(dev, file_priv, handle);
3957 if (!bo)
3958 return -ENOENT;
3959
3960 obj_priv = to_intel_bo(bo);
3961
3962 if (bo->size < width * height * 4) {
3963 DRM_ERROR("buffer is to small\n");
3964 ret = -ENOMEM;
3965 goto fail;
3966 }
3967
3968 /* we only need to pin inside GTT if cursor is non-phy */
3969 mutex_lock(&dev->struct_mutex);
3970 if (!dev_priv->info->cursor_needs_physical) {
3971 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3972 if (ret) {
3973 DRM_ERROR("failed to pin cursor bo\n");
3974 goto fail_locked;
3975 }
3976
3977 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
3978 if (ret) {
3979 DRM_ERROR("failed to move cursor bo into the GTT\n");
3980 goto fail_unpin;
3981 }
3982
3983 addr = obj_priv->gtt_offset;
3984 } else {
3985 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3986 if (ret) {
3987 DRM_ERROR("failed to attach phys object\n");
3988 goto fail_locked;
3989 }
3990 addr = obj_priv->phys_obj->handle->busaddr;
3991 }
3992
3993 if (!IS_I9XX(dev))
3994 I915_WRITE(CURSIZE, (height << 12) | width);
3995
3996 /* Hooray for CUR*CNTR differences */
3997 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3998 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3999 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4000 temp |= (pipe << 28); /* Connect to correct pipe */
4001 } else {
4002 temp &= ~(CURSOR_FORMAT_MASK);
4003 temp |= CURSOR_ENABLE;
4004 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4005 }
4006
4007 finish:
4008 I915_WRITE(control, temp);
4009 I915_WRITE(base, addr);
4010
4011 if (intel_crtc->cursor_bo) {
4012 if (dev_priv->info->cursor_needs_physical) {
4013 if (intel_crtc->cursor_bo != bo)
4014 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4015 } else
4016 i915_gem_object_unpin(intel_crtc->cursor_bo);
4017 drm_gem_object_unreference(intel_crtc->cursor_bo);
4018 }
4019
4020 mutex_unlock(&dev->struct_mutex);
4021
4022 intel_crtc->cursor_addr = addr;
4023 intel_crtc->cursor_bo = bo;
4024
4025 return 0;
4026 fail_unpin:
4027 i915_gem_object_unpin(bo);
4028 fail_locked:
4029 mutex_unlock(&dev->struct_mutex);
4030 fail:
4031 drm_gem_object_unreference_unlocked(bo);
4032 return ret;
4033 }
4034
4035 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4036 {
4037 struct drm_device *dev = crtc->dev;
4038 struct drm_i915_private *dev_priv = dev->dev_private;
4039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4040 struct intel_framebuffer *intel_fb;
4041 int pipe = intel_crtc->pipe;
4042 uint32_t temp = 0;
4043 uint32_t adder;
4044
4045 if (crtc->fb) {
4046 intel_fb = to_intel_framebuffer(crtc->fb);
4047 intel_mark_busy(dev, intel_fb->obj);
4048 }
4049
4050 if (x < 0) {
4051 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4052 x = -x;
4053 }
4054 if (y < 0) {
4055 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4056 y = -y;
4057 }
4058
4059 temp |= x << CURSOR_X_SHIFT;
4060 temp |= y << CURSOR_Y_SHIFT;
4061
4062 adder = intel_crtc->cursor_addr;
4063 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
4064 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
4065
4066 return 0;
4067 }
4068
4069 /** Sets the color ramps on behalf of RandR */
4070 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4071 u16 blue, int regno)
4072 {
4073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4074
4075 intel_crtc->lut_r[regno] = red >> 8;
4076 intel_crtc->lut_g[regno] = green >> 8;
4077 intel_crtc->lut_b[regno] = blue >> 8;
4078 }
4079
4080 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4081 u16 *blue, int regno)
4082 {
4083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4084
4085 *red = intel_crtc->lut_r[regno] << 8;
4086 *green = intel_crtc->lut_g[regno] << 8;
4087 *blue = intel_crtc->lut_b[regno] << 8;
4088 }
4089
4090 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4091 u16 *blue, uint32_t size)
4092 {
4093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4094 int i;
4095
4096 if (size != 256)
4097 return;
4098
4099 for (i = 0; i < 256; i++) {
4100 intel_crtc->lut_r[i] = red[i] >> 8;
4101 intel_crtc->lut_g[i] = green[i] >> 8;
4102 intel_crtc->lut_b[i] = blue[i] >> 8;
4103 }
4104
4105 intel_crtc_load_lut(crtc);
4106 }
4107
4108 /**
4109 * Get a pipe with a simple mode set on it for doing load-based monitor
4110 * detection.
4111 *
4112 * It will be up to the load-detect code to adjust the pipe as appropriate for
4113 * its requirements. The pipe will be connected to no other encoders.
4114 *
4115 * Currently this code will only succeed if there is a pipe with no encoders
4116 * configured for it. In the future, it could choose to temporarily disable
4117 * some outputs to free up a pipe for its use.
4118 *
4119 * \return crtc, or NULL if no pipes are available.
4120 */
4121
4122 /* VESA 640x480x72Hz mode to set on the pipe */
4123 static struct drm_display_mode load_detect_mode = {
4124 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4125 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4126 };
4127
4128 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4129 struct drm_connector *connector,
4130 struct drm_display_mode *mode,
4131 int *dpms_mode)
4132 {
4133 struct intel_crtc *intel_crtc;
4134 struct drm_crtc *possible_crtc;
4135 struct drm_crtc *supported_crtc =NULL;
4136 struct drm_encoder *encoder = &intel_encoder->enc;
4137 struct drm_crtc *crtc = NULL;
4138 struct drm_device *dev = encoder->dev;
4139 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4140 struct drm_crtc_helper_funcs *crtc_funcs;
4141 int i = -1;
4142
4143 /*
4144 * Algorithm gets a little messy:
4145 * - if the connector already has an assigned crtc, use it (but make
4146 * sure it's on first)
4147 * - try to find the first unused crtc that can drive this connector,
4148 * and use that if we find one
4149 * - if there are no unused crtcs available, try to use the first
4150 * one we found that supports the connector
4151 */
4152
4153 /* See if we already have a CRTC for this connector */
4154 if (encoder->crtc) {
4155 crtc = encoder->crtc;
4156 /* Make sure the crtc and connector are running */
4157 intel_crtc = to_intel_crtc(crtc);
4158 *dpms_mode = intel_crtc->dpms_mode;
4159 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4160 crtc_funcs = crtc->helper_private;
4161 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4162 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4163 }
4164 return crtc;
4165 }
4166
4167 /* Find an unused one (if possible) */
4168 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4169 i++;
4170 if (!(encoder->possible_crtcs & (1 << i)))
4171 continue;
4172 if (!possible_crtc->enabled) {
4173 crtc = possible_crtc;
4174 break;
4175 }
4176 if (!supported_crtc)
4177 supported_crtc = possible_crtc;
4178 }
4179
4180 /*
4181 * If we didn't find an unused CRTC, don't use any.
4182 */
4183 if (!crtc) {
4184 return NULL;
4185 }
4186
4187 encoder->crtc = crtc;
4188 connector->encoder = encoder;
4189 intel_encoder->load_detect_temp = true;
4190
4191 intel_crtc = to_intel_crtc(crtc);
4192 *dpms_mode = intel_crtc->dpms_mode;
4193
4194 if (!crtc->enabled) {
4195 if (!mode)
4196 mode = &load_detect_mode;
4197 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4198 } else {
4199 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4200 crtc_funcs = crtc->helper_private;
4201 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4202 }
4203
4204 /* Add this connector to the crtc */
4205 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4206 encoder_funcs->commit(encoder);
4207 }
4208 /* let the connector get through one full cycle before testing */
4209 intel_wait_for_vblank(dev);
4210
4211 return crtc;
4212 }
4213
4214 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4215 struct drm_connector *connector, int dpms_mode)
4216 {
4217 struct drm_encoder *encoder = &intel_encoder->enc;
4218 struct drm_device *dev = encoder->dev;
4219 struct drm_crtc *crtc = encoder->crtc;
4220 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4221 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4222
4223 if (intel_encoder->load_detect_temp) {
4224 encoder->crtc = NULL;
4225 connector->encoder = NULL;
4226 intel_encoder->load_detect_temp = false;
4227 crtc->enabled = drm_helper_crtc_in_use(crtc);
4228 drm_helper_disable_unused_functions(dev);
4229 }
4230
4231 /* Switch crtc and encoder back off if necessary */
4232 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4233 if (encoder->crtc == crtc)
4234 encoder_funcs->dpms(encoder, dpms_mode);
4235 crtc_funcs->dpms(crtc, dpms_mode);
4236 }
4237 }
4238
4239 /* Returns the clock of the currently programmed mode of the given pipe. */
4240 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4241 {
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4244 int pipe = intel_crtc->pipe;
4245 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4246 u32 fp;
4247 intel_clock_t clock;
4248
4249 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4250 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4251 else
4252 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4253
4254 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4255 if (IS_PINEVIEW(dev)) {
4256 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4257 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4258 } else {
4259 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4260 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4261 }
4262
4263 if (IS_I9XX(dev)) {
4264 if (IS_PINEVIEW(dev))
4265 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4266 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4267 else
4268 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4269 DPLL_FPA01_P1_POST_DIV_SHIFT);
4270
4271 switch (dpll & DPLL_MODE_MASK) {
4272 case DPLLB_MODE_DAC_SERIAL:
4273 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4274 5 : 10;
4275 break;
4276 case DPLLB_MODE_LVDS:
4277 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4278 7 : 14;
4279 break;
4280 default:
4281 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4282 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4283 return 0;
4284 }
4285
4286 /* XXX: Handle the 100Mhz refclk */
4287 intel_clock(dev, 96000, &clock);
4288 } else {
4289 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4290
4291 if (is_lvds) {
4292 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4293 DPLL_FPA01_P1_POST_DIV_SHIFT);
4294 clock.p2 = 14;
4295
4296 if ((dpll & PLL_REF_INPUT_MASK) ==
4297 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4298 /* XXX: might not be 66MHz */
4299 intel_clock(dev, 66000, &clock);
4300 } else
4301 intel_clock(dev, 48000, &clock);
4302 } else {
4303 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4304 clock.p1 = 2;
4305 else {
4306 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4307 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4308 }
4309 if (dpll & PLL_P2_DIVIDE_BY_4)
4310 clock.p2 = 4;
4311 else
4312 clock.p2 = 2;
4313
4314 intel_clock(dev, 48000, &clock);
4315 }
4316 }
4317
4318 /* XXX: It would be nice to validate the clocks, but we can't reuse
4319 * i830PllIsValid() because it relies on the xf86_config connector
4320 * configuration being accurate, which it isn't necessarily.
4321 */
4322
4323 return clock.dot;
4324 }
4325
4326 /** Returns the currently programmed mode of the given pipe. */
4327 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4328 struct drm_crtc *crtc)
4329 {
4330 struct drm_i915_private *dev_priv = dev->dev_private;
4331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4332 int pipe = intel_crtc->pipe;
4333 struct drm_display_mode *mode;
4334 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4335 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4336 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4337 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4338
4339 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4340 if (!mode)
4341 return NULL;
4342
4343 mode->clock = intel_crtc_clock_get(dev, crtc);
4344 mode->hdisplay = (htot & 0xffff) + 1;
4345 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4346 mode->hsync_start = (hsync & 0xffff) + 1;
4347 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4348 mode->vdisplay = (vtot & 0xffff) + 1;
4349 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4350 mode->vsync_start = (vsync & 0xffff) + 1;
4351 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4352
4353 drm_mode_set_name(mode);
4354 drm_mode_set_crtcinfo(mode, 0);
4355
4356 return mode;
4357 }
4358
4359 #define GPU_IDLE_TIMEOUT 500 /* ms */
4360
4361 /* When this timer fires, we've been idle for awhile */
4362 static void intel_gpu_idle_timer(unsigned long arg)
4363 {
4364 struct drm_device *dev = (struct drm_device *)arg;
4365 drm_i915_private_t *dev_priv = dev->dev_private;
4366
4367 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4368
4369 dev_priv->busy = false;
4370
4371 queue_work(dev_priv->wq, &dev_priv->idle_work);
4372 }
4373
4374 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4375
4376 static void intel_crtc_idle_timer(unsigned long arg)
4377 {
4378 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4379 struct drm_crtc *crtc = &intel_crtc->base;
4380 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4381
4382 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4383
4384 intel_crtc->busy = false;
4385
4386 queue_work(dev_priv->wq, &dev_priv->idle_work);
4387 }
4388
4389 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4390 {
4391 struct drm_device *dev = crtc->dev;
4392 drm_i915_private_t *dev_priv = dev->dev_private;
4393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4394 int pipe = intel_crtc->pipe;
4395 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4396 int dpll = I915_READ(dpll_reg);
4397
4398 if (HAS_PCH_SPLIT(dev))
4399 return;
4400
4401 if (!dev_priv->lvds_downclock_avail)
4402 return;
4403
4404 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4405 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4406
4407 /* Unlock panel regs */
4408 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4409
4410 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4411 I915_WRITE(dpll_reg, dpll);
4412 dpll = I915_READ(dpll_reg);
4413 intel_wait_for_vblank(dev);
4414 dpll = I915_READ(dpll_reg);
4415 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4416 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4417
4418 /* ...and lock them again */
4419 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4420 }
4421
4422 /* Schedule downclock */
4423 if (schedule)
4424 mod_timer(&intel_crtc->idle_timer, jiffies +
4425 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4426 }
4427
4428 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4429 {
4430 struct drm_device *dev = crtc->dev;
4431 drm_i915_private_t *dev_priv = dev->dev_private;
4432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4433 int pipe = intel_crtc->pipe;
4434 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4435 int dpll = I915_READ(dpll_reg);
4436
4437 if (HAS_PCH_SPLIT(dev))
4438 return;
4439
4440 if (!dev_priv->lvds_downclock_avail)
4441 return;
4442
4443 /*
4444 * Since this is called by a timer, we should never get here in
4445 * the manual case.
4446 */
4447 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4448 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4449
4450 /* Unlock panel regs */
4451 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4452
4453 dpll |= DISPLAY_RATE_SELECT_FPA1;
4454 I915_WRITE(dpll_reg, dpll);
4455 dpll = I915_READ(dpll_reg);
4456 intel_wait_for_vblank(dev);
4457 dpll = I915_READ(dpll_reg);
4458 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4459 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4460
4461 /* ...and lock them again */
4462 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4463 }
4464
4465 }
4466
4467 /**
4468 * intel_idle_update - adjust clocks for idleness
4469 * @work: work struct
4470 *
4471 * Either the GPU or display (or both) went idle. Check the busy status
4472 * here and adjust the CRTC and GPU clocks as necessary.
4473 */
4474 static void intel_idle_update(struct work_struct *work)
4475 {
4476 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4477 idle_work);
4478 struct drm_device *dev = dev_priv->dev;
4479 struct drm_crtc *crtc;
4480 struct intel_crtc *intel_crtc;
4481
4482 if (!i915_powersave)
4483 return;
4484
4485 mutex_lock(&dev->struct_mutex);
4486
4487 i915_update_gfx_val(dev_priv);
4488
4489 if (IS_I945G(dev) || IS_I945GM(dev)) {
4490 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4491 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4492 }
4493
4494 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4495 /* Skip inactive CRTCs */
4496 if (!crtc->fb)
4497 continue;
4498
4499 intel_crtc = to_intel_crtc(crtc);
4500 if (!intel_crtc->busy)
4501 intel_decrease_pllclock(crtc);
4502 }
4503
4504 mutex_unlock(&dev->struct_mutex);
4505 }
4506
4507 /**
4508 * intel_mark_busy - mark the GPU and possibly the display busy
4509 * @dev: drm device
4510 * @obj: object we're operating on
4511 *
4512 * Callers can use this function to indicate that the GPU is busy processing
4513 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4514 * buffer), we'll also mark the display as busy, so we know to increase its
4515 * clock frequency.
4516 */
4517 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4518 {
4519 drm_i915_private_t *dev_priv = dev->dev_private;
4520 struct drm_crtc *crtc = NULL;
4521 struct intel_framebuffer *intel_fb;
4522 struct intel_crtc *intel_crtc;
4523
4524 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4525 return;
4526
4527 if (!dev_priv->busy) {
4528 if (IS_I945G(dev) || IS_I945GM(dev)) {
4529 u32 fw_blc_self;
4530
4531 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4532 fw_blc_self = I915_READ(FW_BLC_SELF);
4533 fw_blc_self &= ~FW_BLC_SELF_EN;
4534 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4535 }
4536 dev_priv->busy = true;
4537 } else
4538 mod_timer(&dev_priv->idle_timer, jiffies +
4539 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4540
4541 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4542 if (!crtc->fb)
4543 continue;
4544
4545 intel_crtc = to_intel_crtc(crtc);
4546 intel_fb = to_intel_framebuffer(crtc->fb);
4547 if (intel_fb->obj == obj) {
4548 if (!intel_crtc->busy) {
4549 if (IS_I945G(dev) || IS_I945GM(dev)) {
4550 u32 fw_blc_self;
4551
4552 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4553 fw_blc_self = I915_READ(FW_BLC_SELF);
4554 fw_blc_self &= ~FW_BLC_SELF_EN;
4555 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4556 }
4557 /* Non-busy -> busy, upclock */
4558 intel_increase_pllclock(crtc, true);
4559 intel_crtc->busy = true;
4560 } else {
4561 /* Busy -> busy, put off timer */
4562 mod_timer(&intel_crtc->idle_timer, jiffies +
4563 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4564 }
4565 }
4566 }
4567 }
4568
4569 static void intel_crtc_destroy(struct drm_crtc *crtc)
4570 {
4571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4572
4573 drm_crtc_cleanup(crtc);
4574 kfree(intel_crtc);
4575 }
4576
4577 struct intel_unpin_work {
4578 struct work_struct work;
4579 struct drm_device *dev;
4580 struct drm_gem_object *old_fb_obj;
4581 struct drm_gem_object *pending_flip_obj;
4582 struct drm_pending_vblank_event *event;
4583 int pending;
4584 };
4585
4586 static void intel_unpin_work_fn(struct work_struct *__work)
4587 {
4588 struct intel_unpin_work *work =
4589 container_of(__work, struct intel_unpin_work, work);
4590
4591 mutex_lock(&work->dev->struct_mutex);
4592 i915_gem_object_unpin(work->old_fb_obj);
4593 drm_gem_object_unreference(work->pending_flip_obj);
4594 drm_gem_object_unreference(work->old_fb_obj);
4595 mutex_unlock(&work->dev->struct_mutex);
4596 kfree(work);
4597 }
4598
4599 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4600 {
4601 drm_i915_private_t *dev_priv = dev->dev_private;
4602 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4604 struct intel_unpin_work *work;
4605 struct drm_i915_gem_object *obj_priv;
4606 struct drm_pending_vblank_event *e;
4607 struct timeval now;
4608 unsigned long flags;
4609
4610 /* Ignore early vblank irqs */
4611 if (intel_crtc == NULL)
4612 return;
4613
4614 spin_lock_irqsave(&dev->event_lock, flags);
4615 work = intel_crtc->unpin_work;
4616 if (work == NULL || !work->pending) {
4617 spin_unlock_irqrestore(&dev->event_lock, flags);
4618 return;
4619 }
4620
4621 intel_crtc->unpin_work = NULL;
4622 drm_vblank_put(dev, intel_crtc->pipe);
4623
4624 if (work->event) {
4625 e = work->event;
4626 do_gettimeofday(&now);
4627 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4628 e->event.tv_sec = now.tv_sec;
4629 e->event.tv_usec = now.tv_usec;
4630 list_add_tail(&e->base.link,
4631 &e->base.file_priv->event_list);
4632 wake_up_interruptible(&e->base.file_priv->event_wait);
4633 }
4634
4635 spin_unlock_irqrestore(&dev->event_lock, flags);
4636
4637 obj_priv = to_intel_bo(work->pending_flip_obj);
4638
4639 /* Initial scanout buffer will have a 0 pending flip count */
4640 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4641 atomic_dec_and_test(&obj_priv->pending_flip))
4642 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4643 schedule_work(&work->work);
4644 }
4645
4646 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4647 {
4648 drm_i915_private_t *dev_priv = dev->dev_private;
4649 struct intel_crtc *intel_crtc =
4650 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4651 unsigned long flags;
4652
4653 spin_lock_irqsave(&dev->event_lock, flags);
4654 if (intel_crtc->unpin_work) {
4655 intel_crtc->unpin_work->pending = 1;
4656 } else {
4657 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4658 }
4659 spin_unlock_irqrestore(&dev->event_lock, flags);
4660 }
4661
4662 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4663 struct drm_framebuffer *fb,
4664 struct drm_pending_vblank_event *event)
4665 {
4666 struct drm_device *dev = crtc->dev;
4667 struct drm_i915_private *dev_priv = dev->dev_private;
4668 struct intel_framebuffer *intel_fb;
4669 struct drm_i915_gem_object *obj_priv;
4670 struct drm_gem_object *obj;
4671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4672 struct intel_unpin_work *work;
4673 unsigned long flags;
4674 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4675 int ret, pipesrc;
4676
4677 work = kzalloc(sizeof *work, GFP_KERNEL);
4678 if (work == NULL)
4679 return -ENOMEM;
4680
4681 work->event = event;
4682 work->dev = crtc->dev;
4683 intel_fb = to_intel_framebuffer(crtc->fb);
4684 work->old_fb_obj = intel_fb->obj;
4685 INIT_WORK(&work->work, intel_unpin_work_fn);
4686
4687 /* We borrow the event spin lock for protecting unpin_work */
4688 spin_lock_irqsave(&dev->event_lock, flags);
4689 if (intel_crtc->unpin_work) {
4690 spin_unlock_irqrestore(&dev->event_lock, flags);
4691 kfree(work);
4692
4693 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4694 return -EBUSY;
4695 }
4696 intel_crtc->unpin_work = work;
4697 spin_unlock_irqrestore(&dev->event_lock, flags);
4698
4699 intel_fb = to_intel_framebuffer(fb);
4700 obj = intel_fb->obj;
4701
4702 mutex_lock(&dev->struct_mutex);
4703 ret = intel_pin_and_fence_fb_obj(dev, obj);
4704 if (ret != 0) {
4705 mutex_unlock(&dev->struct_mutex);
4706
4707 spin_lock_irqsave(&dev->event_lock, flags);
4708 intel_crtc->unpin_work = NULL;
4709 spin_unlock_irqrestore(&dev->event_lock, flags);
4710
4711 kfree(work);
4712
4713 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4714 to_intel_bo(obj));
4715 return ret;
4716 }
4717
4718 /* Reference the objects for the scheduled work. */
4719 drm_gem_object_reference(work->old_fb_obj);
4720 drm_gem_object_reference(obj);
4721
4722 crtc->fb = fb;
4723 i915_gem_object_flush_write_domain(obj);
4724 drm_vblank_get(dev, intel_crtc->pipe);
4725 obj_priv = to_intel_bo(obj);
4726 atomic_inc(&obj_priv->pending_flip);
4727 work->pending_flip_obj = obj;
4728
4729 BEGIN_LP_RING(4);
4730 OUT_RING(MI_DISPLAY_FLIP |
4731 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4732 OUT_RING(fb->pitch);
4733 if (IS_I965G(dev)) {
4734 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4735 pipesrc = I915_READ(pipesrc_reg);
4736 OUT_RING(pipesrc & 0x0fff0fff);
4737 } else {
4738 OUT_RING(obj_priv->gtt_offset);
4739 OUT_RING(MI_NOOP);
4740 }
4741 ADVANCE_LP_RING();
4742
4743 mutex_unlock(&dev->struct_mutex);
4744
4745 return 0;
4746 }
4747
4748 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4749 .dpms = intel_crtc_dpms,
4750 .mode_fixup = intel_crtc_mode_fixup,
4751 .mode_set = intel_crtc_mode_set,
4752 .mode_set_base = intel_pipe_set_base,
4753 .prepare = intel_crtc_prepare,
4754 .commit = intel_crtc_commit,
4755 .load_lut = intel_crtc_load_lut,
4756 };
4757
4758 static const struct drm_crtc_funcs intel_crtc_funcs = {
4759 .cursor_set = intel_crtc_cursor_set,
4760 .cursor_move = intel_crtc_cursor_move,
4761 .gamma_set = intel_crtc_gamma_set,
4762 .set_config = drm_crtc_helper_set_config,
4763 .destroy = intel_crtc_destroy,
4764 .page_flip = intel_crtc_page_flip,
4765 };
4766
4767
4768 static void intel_crtc_init(struct drm_device *dev, int pipe)
4769 {
4770 drm_i915_private_t *dev_priv = dev->dev_private;
4771 struct intel_crtc *intel_crtc;
4772 int i;
4773
4774 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4775 if (intel_crtc == NULL)
4776 return;
4777
4778 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4779
4780 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4781 intel_crtc->pipe = pipe;
4782 intel_crtc->plane = pipe;
4783 for (i = 0; i < 256; i++) {
4784 intel_crtc->lut_r[i] = i;
4785 intel_crtc->lut_g[i] = i;
4786 intel_crtc->lut_b[i] = i;
4787 }
4788
4789 /* Swap pipes & planes for FBC on pre-965 */
4790 intel_crtc->pipe = pipe;
4791 intel_crtc->plane = pipe;
4792 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4793 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4794 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4795 }
4796
4797 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4798 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4799 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4800 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4801
4802 intel_crtc->cursor_addr = 0;
4803 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4804 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4805
4806 intel_crtc->busy = false;
4807
4808 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4809 (unsigned long)intel_crtc);
4810 }
4811
4812 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4813 struct drm_file *file_priv)
4814 {
4815 drm_i915_private_t *dev_priv = dev->dev_private;
4816 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4817 struct drm_mode_object *drmmode_obj;
4818 struct intel_crtc *crtc;
4819
4820 if (!dev_priv) {
4821 DRM_ERROR("called with no initialization\n");
4822 return -EINVAL;
4823 }
4824
4825 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4826 DRM_MODE_OBJECT_CRTC);
4827
4828 if (!drmmode_obj) {
4829 DRM_ERROR("no such CRTC id\n");
4830 return -EINVAL;
4831 }
4832
4833 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4834 pipe_from_crtc_id->pipe = crtc->pipe;
4835
4836 return 0;
4837 }
4838
4839 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4840 {
4841 struct drm_crtc *crtc = NULL;
4842
4843 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4845 if (intel_crtc->pipe == pipe)
4846 break;
4847 }
4848 return crtc;
4849 }
4850
4851 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4852 {
4853 int index_mask = 0;
4854 struct drm_encoder *encoder;
4855 int entry = 0;
4856
4857 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4858 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4859 if (type_mask & intel_encoder->clone_mask)
4860 index_mask |= (1 << entry);
4861 entry++;
4862 }
4863 return index_mask;
4864 }
4865
4866
4867 static void intel_setup_outputs(struct drm_device *dev)
4868 {
4869 struct drm_i915_private *dev_priv = dev->dev_private;
4870 struct drm_encoder *encoder;
4871
4872 intel_crt_init(dev);
4873
4874 /* Set up integrated LVDS */
4875 if (IS_MOBILE(dev) && !IS_I830(dev))
4876 intel_lvds_init(dev);
4877
4878 if (HAS_PCH_SPLIT(dev)) {
4879 int found;
4880
4881 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4882 intel_dp_init(dev, DP_A);
4883
4884 if (I915_READ(HDMIB) & PORT_DETECTED) {
4885 /* PCH SDVOB multiplex with HDMIB */
4886 found = intel_sdvo_init(dev, PCH_SDVOB);
4887 if (!found)
4888 intel_hdmi_init(dev, HDMIB);
4889 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4890 intel_dp_init(dev, PCH_DP_B);
4891 }
4892
4893 if (I915_READ(HDMIC) & PORT_DETECTED)
4894 intel_hdmi_init(dev, HDMIC);
4895
4896 if (I915_READ(HDMID) & PORT_DETECTED)
4897 intel_hdmi_init(dev, HDMID);
4898
4899 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4900 intel_dp_init(dev, PCH_DP_C);
4901
4902 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4903 intel_dp_init(dev, PCH_DP_D);
4904
4905 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4906 bool found = false;
4907
4908 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4909 DRM_DEBUG_KMS("probing SDVOB\n");
4910 found = intel_sdvo_init(dev, SDVOB);
4911 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4912 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4913 intel_hdmi_init(dev, SDVOB);
4914 }
4915
4916 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4917 DRM_DEBUG_KMS("probing DP_B\n");
4918 intel_dp_init(dev, DP_B);
4919 }
4920 }
4921
4922 /* Before G4X SDVOC doesn't have its own detect register */
4923
4924 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4925 DRM_DEBUG_KMS("probing SDVOC\n");
4926 found = intel_sdvo_init(dev, SDVOC);
4927 }
4928
4929 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4930
4931 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4932 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4933 intel_hdmi_init(dev, SDVOC);
4934 }
4935 if (SUPPORTS_INTEGRATED_DP(dev)) {
4936 DRM_DEBUG_KMS("probing DP_C\n");
4937 intel_dp_init(dev, DP_C);
4938 }
4939 }
4940
4941 if (SUPPORTS_INTEGRATED_DP(dev) &&
4942 (I915_READ(DP_D) & DP_DETECTED)) {
4943 DRM_DEBUG_KMS("probing DP_D\n");
4944 intel_dp_init(dev, DP_D);
4945 }
4946 } else if (IS_GEN2(dev))
4947 intel_dvo_init(dev);
4948
4949 if (SUPPORTS_TV(dev))
4950 intel_tv_init(dev);
4951
4952 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4953 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4954
4955 encoder->possible_crtcs = intel_encoder->crtc_mask;
4956 encoder->possible_clones = intel_encoder_clones(dev,
4957 intel_encoder->clone_mask);
4958 }
4959 }
4960
4961 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4962 {
4963 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4964
4965 drm_framebuffer_cleanup(fb);
4966 drm_gem_object_unreference_unlocked(intel_fb->obj);
4967
4968 kfree(intel_fb);
4969 }
4970
4971 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4972 struct drm_file *file_priv,
4973 unsigned int *handle)
4974 {
4975 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4976 struct drm_gem_object *object = intel_fb->obj;
4977
4978 return drm_gem_handle_create(file_priv, object, handle);
4979 }
4980
4981 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4982 .destroy = intel_user_framebuffer_destroy,
4983 .create_handle = intel_user_framebuffer_create_handle,
4984 };
4985
4986 int intel_framebuffer_init(struct drm_device *dev,
4987 struct intel_framebuffer *intel_fb,
4988 struct drm_mode_fb_cmd *mode_cmd,
4989 struct drm_gem_object *obj)
4990 {
4991 int ret;
4992
4993 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4994 if (ret) {
4995 DRM_ERROR("framebuffer init failed %d\n", ret);
4996 return ret;
4997 }
4998
4999 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5000 intel_fb->obj = obj;
5001 return 0;
5002 }
5003
5004 static struct drm_framebuffer *
5005 intel_user_framebuffer_create(struct drm_device *dev,
5006 struct drm_file *filp,
5007 struct drm_mode_fb_cmd *mode_cmd)
5008 {
5009 struct drm_gem_object *obj;
5010 struct intel_framebuffer *intel_fb;
5011 int ret;
5012
5013 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5014 if (!obj)
5015 return NULL;
5016
5017 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5018 if (!intel_fb)
5019 return NULL;
5020
5021 ret = intel_framebuffer_init(dev, intel_fb,
5022 mode_cmd, obj);
5023 if (ret) {
5024 drm_gem_object_unreference_unlocked(obj);
5025 kfree(intel_fb);
5026 return NULL;
5027 }
5028
5029 return &intel_fb->base;
5030 }
5031
5032 static const struct drm_mode_config_funcs intel_mode_funcs = {
5033 .fb_create = intel_user_framebuffer_create,
5034 .output_poll_changed = intel_fb_output_poll_changed,
5035 };
5036
5037 static struct drm_gem_object *
5038 intel_alloc_power_context(struct drm_device *dev)
5039 {
5040 struct drm_gem_object *pwrctx;
5041 int ret;
5042
5043 pwrctx = i915_gem_alloc_object(dev, 4096);
5044 if (!pwrctx) {
5045 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5046 return NULL;
5047 }
5048
5049 mutex_lock(&dev->struct_mutex);
5050 ret = i915_gem_object_pin(pwrctx, 4096);
5051 if (ret) {
5052 DRM_ERROR("failed to pin power context: %d\n", ret);
5053 goto err_unref;
5054 }
5055
5056 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5057 if (ret) {
5058 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5059 goto err_unpin;
5060 }
5061 mutex_unlock(&dev->struct_mutex);
5062
5063 return pwrctx;
5064
5065 err_unpin:
5066 i915_gem_object_unpin(pwrctx);
5067 err_unref:
5068 drm_gem_object_unreference(pwrctx);
5069 mutex_unlock(&dev->struct_mutex);
5070 return NULL;
5071 }
5072
5073 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5074 {
5075 struct drm_i915_private *dev_priv = dev->dev_private;
5076 u16 rgvswctl;
5077
5078 rgvswctl = I915_READ16(MEMSWCTL);
5079 if (rgvswctl & MEMCTL_CMD_STS) {
5080 DRM_DEBUG("gpu busy, RCS change rejected\n");
5081 return false; /* still busy with another command */
5082 }
5083
5084 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5085 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5086 I915_WRITE16(MEMSWCTL, rgvswctl);
5087 POSTING_READ16(MEMSWCTL);
5088
5089 rgvswctl |= MEMCTL_CMD_STS;
5090 I915_WRITE16(MEMSWCTL, rgvswctl);
5091
5092 return true;
5093 }
5094
5095 void ironlake_enable_drps(struct drm_device *dev)
5096 {
5097 struct drm_i915_private *dev_priv = dev->dev_private;
5098 u32 rgvmodectl = I915_READ(MEMMODECTL);
5099 u8 fmax, fmin, fstart, vstart;
5100 int i = 0;
5101
5102 /* 100ms RC evaluation intervals */
5103 I915_WRITE(RCUPEI, 100000);
5104 I915_WRITE(RCDNEI, 100000);
5105
5106 /* Set max/min thresholds to 90ms and 80ms respectively */
5107 I915_WRITE(RCBMAXAVG, 90000);
5108 I915_WRITE(RCBMINAVG, 80000);
5109
5110 I915_WRITE(MEMIHYST, 1);
5111
5112 /* Set up min, max, and cur for interrupt handling */
5113 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5114 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5115 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5116 MEMMODE_FSTART_SHIFT;
5117 fstart = fmax;
5118
5119 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5120 PXVFREQ_PX_SHIFT;
5121
5122 dev_priv->fmax = fstart; /* IPS callback will increase this */
5123 dev_priv->fstart = fstart;
5124
5125 dev_priv->max_delay = fmax;
5126 dev_priv->min_delay = fmin;
5127 dev_priv->cur_delay = fstart;
5128
5129 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5130 fstart);
5131
5132 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5133
5134 /*
5135 * Interrupts will be enabled in ironlake_irq_postinstall
5136 */
5137
5138 I915_WRITE(VIDSTART, vstart);
5139 POSTING_READ(VIDSTART);
5140
5141 rgvmodectl |= MEMMODE_SWMODE_EN;
5142 I915_WRITE(MEMMODECTL, rgvmodectl);
5143
5144 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5145 if (i++ > 100) {
5146 DRM_ERROR("stuck trying to change perf mode\n");
5147 break;
5148 }
5149 msleep(1);
5150 }
5151 msleep(1);
5152
5153 ironlake_set_drps(dev, fstart);
5154
5155 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5156 I915_READ(0x112e0);
5157 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5158 dev_priv->last_count2 = I915_READ(0x112f4);
5159 getrawmonotonic(&dev_priv->last_time2);
5160 }
5161
5162 void ironlake_disable_drps(struct drm_device *dev)
5163 {
5164 struct drm_i915_private *dev_priv = dev->dev_private;
5165 u16 rgvswctl = I915_READ16(MEMSWCTL);
5166
5167 /* Ack interrupts, disable EFC interrupt */
5168 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5169 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5170 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5171 I915_WRITE(DEIIR, DE_PCU_EVENT);
5172 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5173
5174 /* Go back to the starting frequency */
5175 ironlake_set_drps(dev, dev_priv->fstart);
5176 msleep(1);
5177 rgvswctl |= MEMCTL_CMD_STS;
5178 I915_WRITE(MEMSWCTL, rgvswctl);
5179 msleep(1);
5180
5181 }
5182
5183 static unsigned long intel_pxfreq(u32 vidfreq)
5184 {
5185 unsigned long freq;
5186 int div = (vidfreq & 0x3f0000) >> 16;
5187 int post = (vidfreq & 0x3000) >> 12;
5188 int pre = (vidfreq & 0x7);
5189
5190 if (!pre)
5191 return 0;
5192
5193 freq = ((div * 133333) / ((1<<post) * pre));
5194
5195 return freq;
5196 }
5197
5198 void intel_init_emon(struct drm_device *dev)
5199 {
5200 struct drm_i915_private *dev_priv = dev->dev_private;
5201 u32 lcfuse;
5202 u8 pxw[16];
5203 int i;
5204
5205 /* Disable to program */
5206 I915_WRITE(ECR, 0);
5207 POSTING_READ(ECR);
5208
5209 /* Program energy weights for various events */
5210 I915_WRITE(SDEW, 0x15040d00);
5211 I915_WRITE(CSIEW0, 0x007f0000);
5212 I915_WRITE(CSIEW1, 0x1e220004);
5213 I915_WRITE(CSIEW2, 0x04000004);
5214
5215 for (i = 0; i < 5; i++)
5216 I915_WRITE(PEW + (i * 4), 0);
5217 for (i = 0; i < 3; i++)
5218 I915_WRITE(DEW + (i * 4), 0);
5219
5220 /* Program P-state weights to account for frequency power adjustment */
5221 for (i = 0; i < 16; i++) {
5222 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5223 unsigned long freq = intel_pxfreq(pxvidfreq);
5224 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5225 PXVFREQ_PX_SHIFT;
5226 unsigned long val;
5227
5228 val = vid * vid;
5229 val *= (freq / 1000);
5230 val *= 255;
5231 val /= (127*127*900);
5232 if (val > 0xff)
5233 DRM_ERROR("bad pxval: %ld\n", val);
5234 pxw[i] = val;
5235 }
5236 /* Render standby states get 0 weight */
5237 pxw[14] = 0;
5238 pxw[15] = 0;
5239
5240 for (i = 0; i < 4; i++) {
5241 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5242 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5243 I915_WRITE(PXW + (i * 4), val);
5244 }
5245
5246 /* Adjust magic regs to magic values (more experimental results) */
5247 I915_WRITE(OGW0, 0);
5248 I915_WRITE(OGW1, 0);
5249 I915_WRITE(EG0, 0x00007f00);
5250 I915_WRITE(EG1, 0x0000000e);
5251 I915_WRITE(EG2, 0x000e0000);
5252 I915_WRITE(EG3, 0x68000300);
5253 I915_WRITE(EG4, 0x42000000);
5254 I915_WRITE(EG5, 0x00140031);
5255 I915_WRITE(EG6, 0);
5256 I915_WRITE(EG7, 0);
5257
5258 for (i = 0; i < 8; i++)
5259 I915_WRITE(PXWL + (i * 4), 0);
5260
5261 /* Enable PMON + select events */
5262 I915_WRITE(ECR, 0x80000019);
5263
5264 lcfuse = I915_READ(LCFUSE02);
5265
5266 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5267 }
5268
5269 void intel_init_clock_gating(struct drm_device *dev)
5270 {
5271 struct drm_i915_private *dev_priv = dev->dev_private;
5272
5273 /*
5274 * Disable clock gating reported to work incorrectly according to the
5275 * specs, but enable as much else as we can.
5276 */
5277 if (HAS_PCH_SPLIT(dev)) {
5278 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5279
5280 if (IS_IRONLAKE(dev)) {
5281 /* Required for FBC */
5282 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5283 /* Required for CxSR */
5284 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5285
5286 I915_WRITE(PCH_3DCGDIS0,
5287 MARIUNIT_CLOCK_GATE_DISABLE |
5288 SVSMUNIT_CLOCK_GATE_DISABLE);
5289 }
5290
5291 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5292
5293 /*
5294 * According to the spec the following bits should be set in
5295 * order to enable memory self-refresh
5296 * The bit 22/21 of 0x42004
5297 * The bit 5 of 0x42020
5298 * The bit 15 of 0x45000
5299 */
5300 if (IS_IRONLAKE(dev)) {
5301 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5302 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5303 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5304 I915_WRITE(ILK_DSPCLK_GATE,
5305 (I915_READ(ILK_DSPCLK_GATE) |
5306 ILK_DPARB_CLK_GATE));
5307 I915_WRITE(DISP_ARB_CTL,
5308 (I915_READ(DISP_ARB_CTL) |
5309 DISP_FBC_WM_DIS));
5310 }
5311 return;
5312 } else if (IS_G4X(dev)) {
5313 uint32_t dspclk_gate;
5314 I915_WRITE(RENCLK_GATE_D1, 0);
5315 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5316 GS_UNIT_CLOCK_GATE_DISABLE |
5317 CL_UNIT_CLOCK_GATE_DISABLE);
5318 I915_WRITE(RAMCLK_GATE_D, 0);
5319 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5320 OVRUNIT_CLOCK_GATE_DISABLE |
5321 OVCUNIT_CLOCK_GATE_DISABLE;
5322 if (IS_GM45(dev))
5323 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5324 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5325 } else if (IS_I965GM(dev)) {
5326 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5327 I915_WRITE(RENCLK_GATE_D2, 0);
5328 I915_WRITE(DSPCLK_GATE_D, 0);
5329 I915_WRITE(RAMCLK_GATE_D, 0);
5330 I915_WRITE16(DEUC, 0);
5331 } else if (IS_I965G(dev)) {
5332 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5333 I965_RCC_CLOCK_GATE_DISABLE |
5334 I965_RCPB_CLOCK_GATE_DISABLE |
5335 I965_ISC_CLOCK_GATE_DISABLE |
5336 I965_FBC_CLOCK_GATE_DISABLE);
5337 I915_WRITE(RENCLK_GATE_D2, 0);
5338 } else if (IS_I9XX(dev)) {
5339 u32 dstate = I915_READ(D_STATE);
5340
5341 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5342 DSTATE_DOT_CLOCK_GATING;
5343 I915_WRITE(D_STATE, dstate);
5344 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5345 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5346 } else if (IS_I830(dev)) {
5347 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5348 }
5349
5350 /*
5351 * GPU can automatically power down the render unit if given a page
5352 * to save state.
5353 */
5354 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5355 struct drm_i915_gem_object *obj_priv = NULL;
5356
5357 if (dev_priv->pwrctx) {
5358 obj_priv = to_intel_bo(dev_priv->pwrctx);
5359 } else {
5360 struct drm_gem_object *pwrctx;
5361
5362 pwrctx = intel_alloc_power_context(dev);
5363 if (pwrctx) {
5364 dev_priv->pwrctx = pwrctx;
5365 obj_priv = to_intel_bo(pwrctx);
5366 }
5367 }
5368
5369 if (obj_priv) {
5370 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5371 I915_WRITE(MCHBAR_RENDER_STANDBY,
5372 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5373 }
5374 }
5375 }
5376
5377 /* Set up chip specific display functions */
5378 static void intel_init_display(struct drm_device *dev)
5379 {
5380 struct drm_i915_private *dev_priv = dev->dev_private;
5381
5382 /* We always want a DPMS function */
5383 if (HAS_PCH_SPLIT(dev))
5384 dev_priv->display.dpms = ironlake_crtc_dpms;
5385 else
5386 dev_priv->display.dpms = i9xx_crtc_dpms;
5387
5388 if (I915_HAS_FBC(dev)) {
5389 if (IS_GM45(dev)) {
5390 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5391 dev_priv->display.enable_fbc = g4x_enable_fbc;
5392 dev_priv->display.disable_fbc = g4x_disable_fbc;
5393 } else if (IS_I965GM(dev)) {
5394 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5395 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5396 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5397 }
5398 /* 855GM needs testing */
5399 }
5400
5401 /* Returns the core display clock speed */
5402 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5403 dev_priv->display.get_display_clock_speed =
5404 i945_get_display_clock_speed;
5405 else if (IS_I915G(dev))
5406 dev_priv->display.get_display_clock_speed =
5407 i915_get_display_clock_speed;
5408 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5409 dev_priv->display.get_display_clock_speed =
5410 i9xx_misc_get_display_clock_speed;
5411 else if (IS_I915GM(dev))
5412 dev_priv->display.get_display_clock_speed =
5413 i915gm_get_display_clock_speed;
5414 else if (IS_I865G(dev))
5415 dev_priv->display.get_display_clock_speed =
5416 i865_get_display_clock_speed;
5417 else if (IS_I85X(dev))
5418 dev_priv->display.get_display_clock_speed =
5419 i855_get_display_clock_speed;
5420 else /* 852, 830 */
5421 dev_priv->display.get_display_clock_speed =
5422 i830_get_display_clock_speed;
5423
5424 /* For FIFO watermark updates */
5425 if (HAS_PCH_SPLIT(dev)) {
5426 if (IS_IRONLAKE(dev)) {
5427 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5428 dev_priv->display.update_wm = ironlake_update_wm;
5429 else {
5430 DRM_DEBUG_KMS("Failed to get proper latency. "
5431 "Disable CxSR\n");
5432 dev_priv->display.update_wm = NULL;
5433 }
5434 } else
5435 dev_priv->display.update_wm = NULL;
5436 } else if (IS_PINEVIEW(dev)) {
5437 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5438 dev_priv->is_ddr3,
5439 dev_priv->fsb_freq,
5440 dev_priv->mem_freq)) {
5441 DRM_INFO("failed to find known CxSR latency "
5442 "(found ddr%s fsb freq %d, mem freq %d), "
5443 "disabling CxSR\n",
5444 (dev_priv->is_ddr3 == 1) ? "3": "2",
5445 dev_priv->fsb_freq, dev_priv->mem_freq);
5446 /* Disable CxSR and never update its watermark again */
5447 pineview_disable_cxsr(dev);
5448 dev_priv->display.update_wm = NULL;
5449 } else
5450 dev_priv->display.update_wm = pineview_update_wm;
5451 } else if (IS_G4X(dev))
5452 dev_priv->display.update_wm = g4x_update_wm;
5453 else if (IS_I965G(dev))
5454 dev_priv->display.update_wm = i965_update_wm;
5455 else if (IS_I9XX(dev)) {
5456 dev_priv->display.update_wm = i9xx_update_wm;
5457 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5458 } else if (IS_I85X(dev)) {
5459 dev_priv->display.update_wm = i9xx_update_wm;
5460 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5461 } else {
5462 dev_priv->display.update_wm = i830_update_wm;
5463 if (IS_845G(dev))
5464 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5465 else
5466 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5467 }
5468 }
5469
5470 void intel_modeset_init(struct drm_device *dev)
5471 {
5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473 int num_pipe;
5474 int i;
5475
5476 drm_mode_config_init(dev);
5477
5478 dev->mode_config.min_width = 0;
5479 dev->mode_config.min_height = 0;
5480
5481 dev->mode_config.funcs = (void *)&intel_mode_funcs;
5482
5483 intel_init_display(dev);
5484
5485 if (IS_I965G(dev)) {
5486 dev->mode_config.max_width = 8192;
5487 dev->mode_config.max_height = 8192;
5488 } else if (IS_I9XX(dev)) {
5489 dev->mode_config.max_width = 4096;
5490 dev->mode_config.max_height = 4096;
5491 } else {
5492 dev->mode_config.max_width = 2048;
5493 dev->mode_config.max_height = 2048;
5494 }
5495
5496 /* set memory base */
5497 if (IS_I9XX(dev))
5498 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5499 else
5500 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5501
5502 if (IS_MOBILE(dev) || IS_I9XX(dev))
5503 num_pipe = 2;
5504 else
5505 num_pipe = 1;
5506 DRM_DEBUG_KMS("%d display pipe%s available.\n",
5507 num_pipe, num_pipe > 1 ? "s" : "");
5508
5509 for (i = 0; i < num_pipe; i++) {
5510 intel_crtc_init(dev, i);
5511 }
5512
5513 intel_setup_outputs(dev);
5514
5515 intel_init_clock_gating(dev);
5516
5517 if (IS_IRONLAKE_M(dev)) {
5518 ironlake_enable_drps(dev);
5519 intel_init_emon(dev);
5520 }
5521
5522 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5523 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5524 (unsigned long)dev);
5525
5526 intel_setup_overlay(dev);
5527 }
5528
5529 void intel_modeset_cleanup(struct drm_device *dev)
5530 {
5531 struct drm_i915_private *dev_priv = dev->dev_private;
5532 struct drm_crtc *crtc;
5533 struct intel_crtc *intel_crtc;
5534
5535 mutex_lock(&dev->struct_mutex);
5536
5537 drm_kms_helper_poll_fini(dev);
5538 intel_fbdev_fini(dev);
5539
5540 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5541 /* Skip inactive CRTCs */
5542 if (!crtc->fb)
5543 continue;
5544
5545 intel_crtc = to_intel_crtc(crtc);
5546 intel_increase_pllclock(crtc, false);
5547 del_timer_sync(&intel_crtc->idle_timer);
5548 }
5549
5550 del_timer_sync(&dev_priv->idle_timer);
5551
5552 if (dev_priv->display.disable_fbc)
5553 dev_priv->display.disable_fbc(dev);
5554
5555 if (dev_priv->pwrctx) {
5556 struct drm_i915_gem_object *obj_priv;
5557
5558 obj_priv = to_intel_bo(dev_priv->pwrctx);
5559 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5560 I915_READ(PWRCTXA);
5561 i915_gem_object_unpin(dev_priv->pwrctx);
5562 drm_gem_object_unreference(dev_priv->pwrctx);
5563 }
5564
5565 if (IS_IRONLAKE_M(dev))
5566 ironlake_disable_drps(dev);
5567
5568 mutex_unlock(&dev->struct_mutex);
5569
5570 drm_mode_config_cleanup(dev);
5571 }
5572
5573
5574 /*
5575 * Return which encoder is currently attached for connector.
5576 */
5577 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5578 {
5579 struct drm_mode_object *obj;
5580 struct drm_encoder *encoder;
5581 int i;
5582
5583 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5584 if (connector->encoder_ids[i] == 0)
5585 break;
5586
5587 obj = drm_mode_object_find(connector->dev,
5588 connector->encoder_ids[i],
5589 DRM_MODE_OBJECT_ENCODER);
5590 if (!obj)
5591 continue;
5592
5593 encoder = obj_to_encoder(obj);
5594 return encoder;
5595 }
5596 return NULL;
5597 }
5598
5599 /*
5600 * set vga decode state - true == enable VGA decode
5601 */
5602 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5603 {
5604 struct drm_i915_private *dev_priv = dev->dev_private;
5605 u16 gmch_ctrl;
5606
5607 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5608 if (state)
5609 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5610 else
5611 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5612 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5613 return 0;
5614 }
Linux with added FPC-III support