arch/arc/include/asm/arcregs.h

   1 /*
   2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef _ASM_ARC_ARCREGS_H
  10 #define _ASM_ARC_ARCREGS_H
  11
  12 /* Build Configuration Registers */
  13 #define ARC_REG_AUX_DCCM        0x18    /* DCCM Base Addr ARCv2 */
  14 #define ARC_REG_DCCM_BASE_BUILD 0x61    /* DCCM Base Addr ARCompact */
  15 #define ARC_REG_CRC_BCR         0x62
  16 #define ARC_REG_VECBASE_BCR     0x68
  17 #define ARC_REG_PERIBASE_BCR    0x69
  18 #define ARC_REG_FP_BCR          0x6B    /* ARCompact: Single-Precision FPU */
  19 #define ARC_REG_DPFP_BCR        0x6C    /* ARCompact: Dbl Precision FPU */
  20 #define ARC_REG_FP_V2_BCR       0xc8    /* ARCv2 FPU */
  21 #define ARC_REG_SLC_BCR         0xce
  22 #define ARC_REG_DCCM_BUILD      0x74    /* DCCM size (common) */
  23 #define ARC_REG_TIMERS_BCR      0x75
  24 #define ARC_REG_AP_BCR          0x76
  25 #define ARC_REG_ICCM_BUILD      0x78    /* ICCM size (common) */
  26 #define ARC_REG_XY_MEM_BCR      0x79
  27 #define ARC_REG_MAC_BCR         0x7a
  28 #define ARC_REG_MUL_BCR         0x7b
  29 #define ARC_REG_SWAP_BCR        0x7c
  30 #define ARC_REG_NORM_BCR        0x7d
  31 #define ARC_REG_MIXMAX_BCR      0x7e
  32 #define ARC_REG_BARREL_BCR      0x7f
  33 #define ARC_REG_D_UNCACH_BCR    0x6A
  34 #define ARC_REG_BPU_BCR         0xc0
  35 #define ARC_REG_ISA_CFG_BCR     0xc1
  36 #define ARC_REG_RTT_BCR         0xF2
  37 #define ARC_REG_IRQ_BCR         0xF3
  38 #define ARC_REG_SMART_BCR       0xFF
  39 #define ARC_REG_CLUSTER_BCR     0xcf
  40 #define ARC_REG_AUX_ICCM        0x208   /* ICCM Base Addr (ARCv2) */
  41
  42 /* status32 Bits Positions */
  43 #define STATUS_AE_BIT           5       /* Exception active */
  44 #define STATUS_DE_BIT           6       /* PC is in delay slot */
  45 #define STATUS_U_BIT            7       /* User/Kernel mode */
  46 #define STATUS_Z_BIT            11
  47 #define STATUS_L_BIT            12      /* Loop inhibit */
  48
  49 /* These masks correspond to the status word(STATUS_32) bits */
  50 #define STATUS_AE_MASK          (1<<STATUS_AE_BIT)
  51 #define STATUS_DE_MASK          (1<<STATUS_DE_BIT)
  52 #define STATUS_U_MASK           (1<<STATUS_U_BIT)
  53 #define STATUS_Z_MASK           (1<<STATUS_Z_BIT)
  54 #define STATUS_L_MASK           (1<<STATUS_L_BIT)
  55
  56 /*
  57  * ECR: Exception Cause Reg bits-n-pieces
  58  * [23:16] = Exception Vector
  59  * [15: 8] = Exception Cause Code
  60  * [ 7: 0] = Exception Parameters (for certain types only)
  61  */
  62 #ifdef CONFIG_ISA_ARCOMPACT
  63 #define ECR_V_MEM_ERR                   0x01
  64 #define ECR_V_INSN_ERR                  0x02
  65 #define ECR_V_MACH_CHK                  0x20
  66 #define ECR_V_ITLB_MISS                 0x21
  67 #define ECR_V_DTLB_MISS                 0x22
  68 #define ECR_V_PROTV                     0x23
  69 #define ECR_V_TRAP                      0x25
  70 #else
  71 #define ECR_V_MEM_ERR                   0x01
  72 #define ECR_V_INSN_ERR                  0x02
  73 #define ECR_V_MACH_CHK                  0x03
  74 #define ECR_V_ITLB_MISS                 0x04
  75 #define ECR_V_DTLB_MISS                 0x05
  76 #define ECR_V_PROTV                     0x06
  77 #define ECR_V_TRAP                      0x09
  78 #endif
  79
  80 /* DTLB Miss and Protection Violation Cause Codes */
  81
  82 #define ECR_C_PROTV_INST_FETCH          0x00
  83 #define ECR_C_PROTV_LOAD                0x01
  84 #define ECR_C_PROTV_STORE               0x02
  85 #define ECR_C_PROTV_XCHG                0x03
  86 #define ECR_C_PROTV_MISALIG_DATA        0x04
  87
  88 #define ECR_C_BIT_PROTV_MISALIG_DATA    10
  89
  90 /* Machine Check Cause Code Values */
  91 #define ECR_C_MCHK_DUP_TLB              0x01
  92
  93 /* DTLB Miss Exception Cause Code Values */
  94 #define ECR_C_BIT_DTLB_LD_MISS          8
  95 #define ECR_C_BIT_DTLB_ST_MISS          9
  96
  97 /* Auxiliary registers */
  98 #define AUX_IDENTITY            4
  99 #define AUX_INTR_VEC_BASE       0x25
 100 #define AUX_VOL                 0x5e
 101
 102 /*
 103  * Floating Pt Registers
 104  * Status regs are read-only (build-time) so need not be saved/restored
 105  */
 106 #define ARC_AUX_FP_STAT         0x300
 107 #define ARC_AUX_DPFP_1L         0x301
 108 #define ARC_AUX_DPFP_1H         0x302
 109 #define ARC_AUX_DPFP_2L         0x303
 110 #define ARC_AUX_DPFP_2H         0x304
 111 #define ARC_AUX_DPFP_STAT       0x305
 112
 113 #ifndef __ASSEMBLY__
 114
 115 /*
 116  ******************************************************************
 117  *      Inline ASM macros to read/write AUX Regs
 118  *      Essentially invocation of lr/sr insns from "C"
 119  */
 120
 121 #if 1
 122
 123 #define read_aux_reg(reg)       __builtin_arc_lr(reg)
 124
 125 /* gcc builtin sr needs reg param to be long immediate */
 126 #define write_aux_reg(reg_immed, val)           \
 127                 __builtin_arc_sr((unsigned int)(val), reg_immed)
 128
 129 #else
 130
 131 #define read_aux_reg(reg)               \
 132 ({                                      \
 133         unsigned int __ret;             \
 134         __asm__ __volatile__(           \
 135         "       lr    %0, [%1]"         \
 136         : "=r"(__ret)                   \
 137         : "i"(reg));                    \
 138         __ret;                          \
 139 })
 140
 141 /*
 142  * Aux Reg address is specified as long immediate by caller
 143  * e.g.
 144  *    write_aux_reg(0x69, some_val);
 145  * This generates tightest code.
 146  */
 147 #define write_aux_reg(reg_imm, val)     \
 148 ({                                      \
 149         __asm__ __volatile__(           \
 150         "       sr   %0, [%1]   \n"     \
 151         :                               \
 152         : "ir"(val), "i"(reg_imm));     \
 153 })
 154
 155 /*
 156  * Aux Reg address is specified in a variable
 157  *  * e.g.
 158  *      reg_num = 0x69
 159  *      write_aux_reg2(reg_num, some_val);
 160  * This has to generate glue code to load the reg num from
 161  *  memory to a reg hence not recommended.
 162  */
 163 #define write_aux_reg2(reg_in_var, val)         \
 164 ({                                              \
 165         unsigned int tmp;                       \
 166                                                 \
 167         __asm__ __volatile__(                   \
 168         "       ld   %0, [%2]   \n\t"           \
 169         "       sr   %1, [%0]   \n\t"           \
 170         : "=&r"(tmp)                            \
 171         : "r"(val), "memory"(&reg_in_var));     \
 172 })
 173
 174 #endif
 175
 176 #define READ_BCR(reg, into)                             \
 177 {                                                       \
 178         unsigned int tmp;                               \
 179         tmp = read_aux_reg(reg);                        \
 180         if (sizeof(tmp) == sizeof(into)) {              \
 181                 into = *((typeof(into) *)&tmp);         \
 182         } else {                                        \
 183                 extern void bogus_undefined(void);      \
 184                 bogus_undefined();                      \
 185         }                                               \
 186 }
 187
 188 #define WRITE_AUX(reg, into)                            \
 189 {                                                       \
 190         unsigned int tmp;                               \
 191         if (sizeof(tmp) == sizeof(into)) {              \
 192                 tmp = (*(unsigned int *)&(into));       \
 193                 write_aux_reg(reg, tmp);                \
 194         } else  {                                       \
 195                 extern void bogus_undefined(void);      \
 196                 bogus_undefined();                      \
 197         }                                               \
 198 }
 199
 200 /* Helpers */
 201 #define TO_KB(bytes)            ((bytes) >> 10)
 202 #define TO_MB(bytes)            (TO_KB(bytes) >> 10)
 203 #define PAGES_TO_KB(n_pages)    ((n_pages) << (PAGE_SHIFT - 10))
 204 #define PAGES_TO_MB(n_pages)    (PAGES_TO_KB(n_pages) >> 10)
 205
 206
 207 /*
 208  ***************************************************************
 209  * Build Configuration Registers, with encoded hardware config
 210  */
 211 struct bcr_identity {
 212 #ifdef CONFIG_CPU_BIG_ENDIAN
 213         unsigned int chip_id:16, cpu_id:8, family:8;
 214 #else
 215         unsigned int family:8, cpu_id:8, chip_id:16;
 216 #endif
 217 };
 218
 219 struct bcr_isa {
 220 #ifdef CONFIG_CPU_BIG_ENDIAN
 221         unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
 222                      pad1:11, atomic1:1, ver:8;
 223 #else
 224         unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
 225                      ldd:1, pad2:4, div_rem:4;
 226 #endif
 227 };
 228
 229 struct bcr_mpy {
 230 #ifdef CONFIG_CPU_BIG_ENDIAN
 231         unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
 232 #else
 233         unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
 234 #endif
 235 };
 236
 237 struct bcr_extn_xymem {
 238 #ifdef CONFIG_CPU_BIG_ENDIAN
 239         unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
 240 #else
 241         unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
 242 #endif
 243 };
 244
 245 struct bcr_iccm_arcompact {
 246 #ifdef CONFIG_CPU_BIG_ENDIAN
 247         unsigned int base:16, pad:5, sz:3, ver:8;
 248 #else
 249         unsigned int ver:8, sz:3, pad:5, base:16;
 250 #endif
 251 };
 252
 253 struct bcr_iccm_arcv2 {
 254 #ifdef CONFIG_CPU_BIG_ENDIAN
 255         unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
 256 #else
 257         unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
 258 #endif
 259 };
 260
 261 struct bcr_dccm_arcompact {
 262 #ifdef CONFIG_CPU_BIG_ENDIAN
 263         unsigned int res:21, sz:3, ver:8;
 264 #else
 265         unsigned int ver:8, sz:3, res:21;
 266 #endif
 267 };
 268
 269 struct bcr_dccm_arcv2 {
 270 #ifdef CONFIG_CPU_BIG_ENDIAN
 271         unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
 272 #else
 273         unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
 274 #endif
 275 };
 276
 277 /* ARCompact: Both SP and DP FPU BCRs have same format */
 278 struct bcr_fp_arcompact {
 279 #ifdef CONFIG_CPU_BIG_ENDIAN
 280         unsigned int fast:1, ver:8;
 281 #else
 282         unsigned int ver:8, fast:1;
 283 #endif
 284 };
 285
 286 struct bcr_fp_arcv2 {
 287 #ifdef CONFIG_CPU_BIG_ENDIAN
 288         unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
 289 #else
 290         unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
 291 #endif
 292 };
 293
 294 struct bcr_timer {
 295 #ifdef CONFIG_CPU_BIG_ENDIAN
 296         unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
 297 #else
 298         unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
 299 #endif
 300 };
 301
 302 struct bcr_bpu_arcompact {
 303 #ifdef CONFIG_CPU_BIG_ENDIAN
 304         unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
 305 #else
 306         unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
 307 #endif
 308 };
 309
 310 struct bcr_bpu_arcv2 {
 311 #ifdef CONFIG_CPU_BIG_ENDIAN
 312         unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
 313 #else
 314         unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
 315 #endif
 316 };
 317
 318 struct bcr_generic {
 319 #ifdef CONFIG_CPU_BIG_ENDIAN
 320         unsigned int info:24, ver:8;
 321 #else
 322         unsigned int ver:8, info:24;
 323 #endif
 324 };
 325
 326 /*
 327  *******************************************************************
 328  * Generic structures to hold build configuration used at runtime
 329  */
 330
 331 struct cpuinfo_arc_mmu {
 332         unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
 333         unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
 334 };
 335
 336 struct cpuinfo_arc_cache {
 337         unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1;
 338 };
 339
 340 struct cpuinfo_arc_bpu {
 341         unsigned int ver, full, num_cache, num_pred;
 342 };
 343
 344 struct cpuinfo_arc_ccm {
 345         unsigned int base_addr, sz;
 346 };
 347
 348 struct cpuinfo_arc {
 349         struct cpuinfo_arc_cache icache, dcache, slc;
 350         struct cpuinfo_arc_mmu mmu;
 351         struct cpuinfo_arc_bpu bpu;
 352         struct bcr_identity core;
 353         struct bcr_isa isa;
 354         const char *details, *name;
 355         unsigned int vec_base;
 356         struct cpuinfo_arc_ccm iccm, dccm;
 357         struct {
 358                 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
 359                              fpu_sp:1, fpu_dp:1, pad2:6,
 360                              debug:1, ap:1, smart:1, rtt:1, pad3:4,
 361                              timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
 362         } extn;
 363         struct bcr_mpy extn_mpy;
 364         struct bcr_extn_xymem extn_xymem;
 365 };
 366
 367 extern struct cpuinfo_arc cpuinfo_arc700[];
 368
 369 static inline int is_isa_arcv2(void)
 370 {
 371         return IS_ENABLED(CONFIG_ISA_ARCV2);
 372 }
 373
 374 static inline int is_isa_arcompact(void)
 375 {
 376         return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
 377 }
 378
 379 #endif /* __ASEMBLY__ */
 380
 381 #endif /* _ASM_ARC_ARCREGS_H */