| blob | d58d8dcb8245318a14cbb9819aaae6b72cde6aec |
1 /*
2 * linux/arch/x86_64/entry.S
3 *
4 * Copyright (C) 1991, 1992 Linus Torvalds
5 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
7 *
8 * entry.S contains the system-call and fault low-level handling routines.
9 *
10 * Some of this is documented in Documentation/x86/entry_64.txt
11 *
12 * A note on terminology:
13 * - iret frame: Architecture defined interrupt frame from SS to RIP
14 * at the top of the kernel process stack.
15 *
16 * Some macro usage:
17 * - ENTRY/END: Define functions in the symbol table.
18 * - TRACE_IRQ_*: Trace hardirq state for lock debugging.
19 * - idtentry: Define exception entry points.
20 */
21 #include <linux/linkage.h>
22 #include <asm/segment.h>
23 #include <asm/cache.h>
24 #include <asm/errno.h>
25 #include "calling.h"
26 #include <asm/asm-offsets.h>
27 #include <asm/msr.h>
28 #include <asm/unistd.h>
29 #include <asm/thread_info.h>
30 #include <asm/hw_irq.h>
31 #include <asm/page_types.h>
32 #include <asm/irqflags.h>
33 #include <asm/paravirt.h>
34 #include <asm/percpu.h>
35 #include <asm/asm.h>
36 #include <asm/smap.h>
37 #include <asm/pgtable_types.h>
38 #include <asm/export.h>
39 #include <asm/kaiser.h>
40 #include <asm/nospec-branch.h>
41 #include <linux/err.h>
43 /* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */
44 #include <linux/elf-em.h>
45 #define AUDIT_ARCH_X86_64 (EM_X86_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
46 #define __AUDIT_ARCH_64BIT 0x80000000
47 #define __AUDIT_ARCH_LE 0x40000000
49 .code64
50 .section .entry.text, "ax"
52 #ifdef CONFIG_PARAVIRT
53 ENTRY(native_usergs_sysret64)
54 swapgs
55 sysretq
56 ENDPROC(native_usergs_sysret64)
57 #endif /* CONFIG_PARAVIRT */
59 .macro TRACE_IRQS_IRETQ
60 #ifdef CONFIG_TRACE_IRQFLAGS
61 bt $9, EFLAGS(%rsp) /* interrupts off? */
62 jnc 1f
63 TRACE_IRQS_ON
64 1:
65 #endif
66 .endm
68 /*
69 * When dynamic function tracer is enabled it will add a breakpoint
70 * to all locations that it is about to modify, sync CPUs, update
71 * all the code, sync CPUs, then remove the breakpoints. In this time
72 * if lockdep is enabled, it might jump back into the debug handler
73 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF).
74 *
75 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to
76 * make sure the stack pointer does not get reset back to the top
77 * of the debug stack, and instead just reuses the current stack.
78 */
79 #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS)
81 .macro TRACE_IRQS_OFF_DEBUG
82 call debug_stack_set_zero
83 TRACE_IRQS_OFF
84 call debug_stack_reset
85 .endm
87 .macro TRACE_IRQS_ON_DEBUG
88 call debug_stack_set_zero
89 TRACE_IRQS_ON
90 call debug_stack_reset
91 .endm
93 .macro TRACE_IRQS_IRETQ_DEBUG
94 bt $9, EFLAGS(%rsp) /* interrupts off? */
95 jnc 1f
96 TRACE_IRQS_ON_DEBUG
97 1:
98 .endm
100 #else
101 # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF
102 # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON
103 # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ
104 #endif
106 /*
107 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
108 *
109 * This is the only entry point used for 64-bit system calls. The
110 * hardware interface is reasonably well designed and the register to
111 * argument mapping Linux uses fits well with the registers that are
112 * available when SYSCALL is used.
113 *
114 * SYSCALL instructions can be found inlined in libc implementations as
115 * well as some other programs and libraries. There are also a handful
116 * of SYSCALL instructions in the vDSO used, for example, as a
117 * clock_gettimeofday fallback.
118 *
119 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
120 * then loads new ss, cs, and rip from previously programmed MSRs.
121 * rflags gets masked by a value from another MSR (so CLD and CLAC
122 * are not needed). SYSCALL does not save anything on the stack
123 * and does not change rsp.
124 *
125 * Registers on entry:
126 * rax system call number
127 * rcx return address
128 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
129 * rdi arg0
130 * rsi arg1
131 * rdx arg2
132 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
133 * r8 arg4
134 * r9 arg5
135 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
136 *
137 * Only called from user space.
138 *
139 * When user can change pt_regs->foo always force IRET. That is because
140 * it deals with uncanonical addresses better. SYSRET has trouble
141 * with them due to bugs in both AMD and Intel CPUs.
142 */
144 ENTRY(entry_SYSCALL_64)
145 /*
146 * Interrupts are off on entry.
147 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON,
148 * it is too small to ever cause noticeable irq latency.
149 */
150 SWAPGS_UNSAFE_STACK
151 SWITCH_KERNEL_CR3_NO_STACK
152 /*
153 * A hypervisor implementation might want to use a label
154 * after the swapgs, so that it can do the swapgs
155 * for the guest and jump here on syscall.
156 */
157 GLOBAL(entry_SYSCALL_64_after_swapgs)
159 movq %rsp, PER_CPU_VAR(rsp_scratch)
160 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
162 TRACE_IRQS_OFF
164 /* Construct struct pt_regs on stack */
165 pushq $__USER_DS /* pt_regs->ss */
166 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */
167 pushq %r11 /* pt_regs->flags */
168 pushq $__USER_CS /* pt_regs->cs */
169 pushq %rcx /* pt_regs->ip */
170 pushq %rax /* pt_regs->orig_ax */
171 pushq %rdi /* pt_regs->di */
172 pushq %rsi /* pt_regs->si */
173 pushq %rdx /* pt_regs->dx */
174 pushq %rcx /* pt_regs->cx */
175 pushq $-ENOSYS /* pt_regs->ax */
176 pushq %r8 /* pt_regs->r8 */
177 pushq %r9 /* pt_regs->r9 */
178 pushq %r10 /* pt_regs->r10 */
179 /*
180 * Clear extra registers that a speculation attack might
181 * otherwise want to exploit. Interleave XOR with PUSH
182 * for better uop scheduling:
183 */
184 xorq %r10, %r10 /* nospec r10 */
185 pushq %r11 /* pt_regs->r11 */
186 xorq %r11, %r11 /* nospec r11 */
187 pushq %rbx /* pt_regs->rbx */
188 xorl %ebx, %ebx /* nospec rbx */
189 pushq %rbp /* pt_regs->rbp */
190 xorl %ebp, %ebp /* nospec rbp */
191 pushq %r12 /* pt_regs->r12 */
192 xorq %r12, %r12 /* nospec r12 */
193 pushq %r13 /* pt_regs->r13 */
194 xorq %r13, %r13 /* nospec r13 */
195 pushq %r14 /* pt_regs->r14 */
196 xorq %r14, %r14 /* nospec r14 */
197 pushq %r15 /* pt_regs->r15 */
198 xorq %r15, %r15 /* nospec r15 */
200 /* IRQs are off. */
201 movq %rsp, %rdi
202 call do_syscall_64 /* returns with IRQs disabled */
204 RESTORE_EXTRA_REGS
205 TRACE_IRQS_IRETQ /* we're about to change IF */
207 /*
208 * Try to use SYSRET instead of IRET if we're returning to
209 * a completely clean 64-bit userspace context.
210 */
211 movq RCX(%rsp), %rcx
212 movq RIP(%rsp), %r11
213 cmpq %rcx, %r11 /* RCX == RIP */
214 jne opportunistic_sysret_failed
216 /*
217 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
218 * in kernel space. This essentially lets the user take over
219 * the kernel, since userspace controls RSP.
220 *
221 * If width of "canonical tail" ever becomes variable, this will need
222 * to be updated to remain correct on both old and new CPUs.
223 */
224 .ifne __VIRTUAL_MASK_SHIFT - 47
225 .error "virtual address width changed -- SYSRET checks need update"
226 .endif
228 /* Change top 16 bits to be the sign-extension of 47th bit */
229 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
230 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
232 /* If this changed %rcx, it was not canonical */
233 cmpq %rcx, %r11
234 jne opportunistic_sysret_failed
236 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
237 jne opportunistic_sysret_failed
239 movq R11(%rsp), %r11
240 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
241 jne opportunistic_sysret_failed
243 /*
244 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
245 * restore RF properly. If the slowpath sets it for whatever reason, we
246 * need to restore it correctly.
247 *
248 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
249 * trap from userspace immediately after SYSRET. This would cause an
250 * infinite loop whenever #DB happens with register state that satisfies
251 * the opportunistic SYSRET conditions. For example, single-stepping
252 * this user code:
253 *
254 * movq $stuck_here, %rcx
255 * pushfq
256 * popq %r11
257 * stuck_here:
258 *
259 * would never get past 'stuck_here'.
260 */
261 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
262 jnz opportunistic_sysret_failed
264 /* nothing to check for RSP */
266 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
267 jne opportunistic_sysret_failed
269 /*
270 * We win! This label is here just for ease of understanding
271 * perf profiles. Nothing jumps here.
272 */
273 syscall_return_via_sysret:
274 /* rcx and r11 are already restored (see code above) */
275 RESTORE_C_REGS_EXCEPT_RCX_R11
277 /*
278 * This opens a window where we have a user CR3, but are
279 * running in the kernel. This makes using the CS
280 * register useless for telling whether or not we need to
281 * switch CR3 in NMIs. Normal interrupts are OK because
282 * they are off here.
283 */
284 SWITCH_USER_CR3
285 movq RSP(%rsp), %rsp
286 USERGS_SYSRET64
288 opportunistic_sysret_failed:
289 /*
290 * This opens a window where we have a user CR3, but are
291 * running in the kernel. This makes using the CS
292 * register useless for telling whether or not we need to
293 * switch CR3 in NMIs. Normal interrupts are OK because
294 * they are off here.
295 */
296 SWITCH_USER_CR3
297 SWAPGS
298 jmp restore_c_regs_and_iret
299 END(entry_SYSCALL_64)
301 /*
302 * %rdi: prev task
303 * %rsi: next task
304 */
305 ENTRY(__switch_to_asm)
306 /*
307 * Save callee-saved registers
308 * This must match the order in inactive_task_frame
309 */
310 pushq %rbp
311 pushq %rbx
312 pushq %r12
313 pushq %r13
314 pushq %r14
315 pushq %r15
317 /* switch stack */
318 movq %rsp, TASK_threadsp(%rdi)
319 movq TASK_threadsp(%rsi), %rsp
321 #ifdef CONFIG_CC_STACKPROTECTOR
322 movq TASK_stack_canary(%rsi), %rbx
323 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset
324 #endif
326 #ifdef CONFIG_RETPOLINE
327 /*
328 * When switching from a shallower to a deeper call stack
329 * the RSB may either underflow or use entries populated
330 * with userspace addresses. On CPUs where those concerns
331 * exist, overwrite the RSB with entries which capture
332 * speculative execution to prevent attack.
333 */
334 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
335 #endif
337 /* restore callee-saved registers */
338 popq %r15
339 popq %r14
340 popq %r13
341 popq %r12
342 popq %rbx
343 popq %rbp
345 jmp __switch_to
346 END(__switch_to_asm)
348 /*
349 * A newly forked process directly context switches into this address.
350 *
351 * rax: prev task we switched from
352 * rbx: kernel thread func (NULL for user thread)
353 * r12: kernel thread arg
354 */
355 ENTRY(ret_from_fork)
356 movq %rax, %rdi
357 call schedule_tail /* rdi: 'prev' task parameter */
359 testq %rbx, %rbx /* from kernel_thread? */
360 jnz 1f /* kernel threads are uncommon */
362 2:
363 movq %rsp, %rdi
364 call syscall_return_slowpath /* returns with IRQs disabled */
365 TRACE_IRQS_ON /* user mode is traced as IRQS on */
366 SWITCH_USER_CR3
367 SWAPGS
368 jmp restore_regs_and_iret
370 1:
371 /* kernel thread */
372 movq %r12, %rdi
373 CALL_NOSPEC %rbx
374 /*
375 * A kernel thread is allowed to return here after successfully
376 * calling do_execve(). Exit to userspace to complete the execve()
377 * syscall.
378 */
379 movq $0, RAX(%rsp)
380 jmp 2b
381 END(ret_from_fork)
383 /*
384 * Build the entry stubs with some assembler magic.
385 * We pack 1 stub into every 8-byte block.
386 */
387 .align 8
388 ENTRY(irq_entries_start)
389 vector=FIRST_EXTERNAL_VECTOR
390 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
391 pushq $(~vector+0x80) /* Note: always in signed byte range */
392 vector=vector+1
393 jmp common_interrupt
394 .align 8
395 .endr
396 END(irq_entries_start)
398 /*
399 * Interrupt entry/exit.
400 *
401 * Interrupt entry points save only callee clobbered registers in fast path.
402 *
403 * Entry runs with interrupts off.
404 */
406 /* 0(%rsp): ~(interrupt number) */
407 .macro interrupt func
408 cld
409 ALLOC_PT_GPREGS_ON_STACK
410 SAVE_C_REGS
411 SAVE_EXTRA_REGS
413 testb $3, CS(%rsp)
414 jz 1f
416 /*
417 * IRQ from user mode. Switch to kernel gsbase and inform context
418 * tracking that we're in kernel mode.
419 */
420 SWAPGS
421 SWITCH_KERNEL_CR3
423 /*
424 * We need to tell lockdep that IRQs are off. We can't do this until
425 * we fix gsbase, and we should do it before enter_from_user_mode
426 * (which can take locks). Since TRACE_IRQS_OFF idempotent,
427 * the simplest way to handle it is to just call it twice if
428 * we enter from user mode. There's no reason to optimize this since
429 * TRACE_IRQS_OFF is a no-op if lockdep is off.
430 */
431 TRACE_IRQS_OFF
433 CALL_enter_from_user_mode
435 1:
436 /*
437 * Save previous stack pointer, optionally switch to interrupt stack.
438 * irq_count is used to check if a CPU is already on an interrupt stack
439 * or not. While this is essentially redundant with preempt_count it is
440 * a little cheaper to use a separate counter in the PDA (short of
441 * moving irq_enter into assembly, which would be too much work)
442 */
443 movq %rsp, %rdi
444 incl PER_CPU_VAR(irq_count)
445 cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp
446 pushq %rdi
447 /* We entered an interrupt context - irqs are off: */
448 TRACE_IRQS_OFF
450 call \func /* rdi points to pt_regs */
451 .endm
453 /*
454 * The interrupt stubs push (~vector+0x80) onto the stack and
455 * then jump to common_interrupt.
456 */
457 .p2align CONFIG_X86_L1_CACHE_SHIFT
458 common_interrupt:
459 ASM_CLAC
460 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
461 interrupt do_IRQ
462 /* 0(%rsp): old RSP */
463 ret_from_intr:
464 DISABLE_INTERRUPTS(CLBR_NONE)
465 TRACE_IRQS_OFF
466 decl PER_CPU_VAR(irq_count)
468 /* Restore saved previous stack */
469 popq %rsp
471 testb $3, CS(%rsp)
472 jz retint_kernel
474 /* Interrupt came from user space */
475 GLOBAL(retint_user)
476 mov %rsp,%rdi
477 call prepare_exit_to_usermode
478 TRACE_IRQS_IRETQ
479 SWITCH_USER_CR3
480 SWAPGS
481 jmp restore_regs_and_iret
483 /* Returning to kernel space */
484 retint_kernel:
485 #ifdef CONFIG_PREEMPT
486 /* Interrupts are off */
487 /* Check if we need preemption */
488 bt $9, EFLAGS(%rsp) /* were interrupts off? */
489 jnc 1f
490 0: cmpl $0, PER_CPU_VAR(__preempt_count)
491 jnz 1f
492 call preempt_schedule_irq
493 jmp 0b
494 1:
495 #endif
496 /*
497 * The iretq could re-enable interrupts:
498 */
499 TRACE_IRQS_IRETQ
501 /*
502 * At this label, code paths which return to kernel and to user,
503 * which come from interrupts/exception and from syscalls, merge.
504 */
505 GLOBAL(restore_regs_and_iret)
506 RESTORE_EXTRA_REGS
507 restore_c_regs_and_iret:
508 RESTORE_C_REGS
509 REMOVE_PT_GPREGS_FROM_STACK 8
510 INTERRUPT_RETURN
512 ENTRY(native_iret)
513 /*
514 * Are we returning to a stack segment from the LDT? Note: in
515 * 64-bit mode SS:RSP on the exception stack is always valid.
516 */
517 #ifdef CONFIG_X86_ESPFIX64
518 testb $4, (SS-RIP)(%rsp)
519 jnz native_irq_return_ldt
520 #endif
522 .global native_irq_return_iret
523 native_irq_return_iret:
524 /*
525 * This may fault. Non-paranoid faults on return to userspace are
526 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
527 * Double-faults due to espfix64 are handled in do_double_fault.
528 * Other faults here are fatal.
529 */
530 iretq
532 #ifdef CONFIG_X86_ESPFIX64
533 native_irq_return_ldt:
534 /*
535 * We are running with user GSBASE. All GPRs contain their user
536 * values. We have a percpu ESPFIX stack that is eight slots
537 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
538 * of the ESPFIX stack.
539 *
540 * We clobber RAX and RDI in this code. We stash RDI on the
541 * normal stack and RAX on the ESPFIX stack.
542 *
543 * The ESPFIX stack layout we set up looks like this:
544 *
545 * --- top of ESPFIX stack ---
546 * SS
547 * RSP
548 * RFLAGS
549 * CS
550 * RIP <-- RSP points here when we're done
551 * RAX <-- espfix_waddr points here
552 * --- bottom of ESPFIX stack ---
553 */
555 pushq %rdi /* Stash user RDI */
556 SWAPGS
557 SWITCH_KERNEL_CR3
558 movq PER_CPU_VAR(espfix_waddr), %rdi
559 movq %rax, (0*8)(%rdi) /* user RAX */
560 movq (1*8)(%rsp), %rax /* user RIP */
561 movq %rax, (1*8)(%rdi)
562 movq (2*8)(%rsp), %rax /* user CS */
563 movq %rax, (2*8)(%rdi)
564 movq (3*8)(%rsp), %rax /* user RFLAGS */
565 movq %rax, (3*8)(%rdi)
566 movq (5*8)(%rsp), %rax /* user SS */
567 movq %rax, (5*8)(%rdi)
568 movq (4*8)(%rsp), %rax /* user RSP */
569 movq %rax, (4*8)(%rdi)
570 /* Now RAX == RSP. */
572 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
573 popq %rdi /* Restore user RDI */
575 /*
576 * espfix_stack[31:16] == 0. The page tables are set up such that
577 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
578 * espfix_waddr for any X. That is, there are 65536 RO aliases of
579 * the same page. Set up RSP so that RSP[31:16] contains the
580 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
581 * still points to an RO alias of the ESPFIX stack.
582 */
583 orq PER_CPU_VAR(espfix_stack), %rax
584 SWITCH_USER_CR3
585 SWAPGS
586 movq %rax, %rsp
588 /*
589 * At this point, we cannot write to the stack any more, but we can
590 * still read.
591 */
592 popq %rax /* Restore user RAX */
594 /*
595 * RSP now points to an ordinary IRET frame, except that the page
596 * is read-only and RSP[31:16] are preloaded with the userspace
597 * values. We can now IRET back to userspace.
598 */
599 jmp native_irq_return_iret
600 #endif
601 END(common_interrupt)
603 /*
604 * APIC interrupts.
605 */
606 .macro apicinterrupt3 num sym do_sym
607 ENTRY(\sym)
608 ASM_CLAC
609 pushq $~(\num)
610 .Lcommon_\sym:
611 interrupt \do_sym
612 jmp ret_from_intr
613 END(\sym)
614 .endm
616 #ifdef CONFIG_TRACING
617 #define trace(sym) trace_##sym
618 #define smp_trace(sym) smp_trace_##sym
620 .macro trace_apicinterrupt num sym
621 apicinterrupt3 \num trace(\sym) smp_trace(\sym)
622 .endm
623 #else
624 .macro trace_apicinterrupt num sym do_sym
625 .endm
626 #endif
628 /* Make sure APIC interrupt handlers end up in the irqentry section: */
629 #if defined(CONFIG_FUNCTION_GRAPH_TRACER) || defined(CONFIG_KASAN)
630 # define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax"
631 # define POP_SECTION_IRQENTRY .popsection
632 #else
633 # define PUSH_SECTION_IRQENTRY
634 # define POP_SECTION_IRQENTRY
635 #endif
637 .macro apicinterrupt num sym do_sym
638 PUSH_SECTION_IRQENTRY
639 apicinterrupt3 \num \sym \do_sym
640 trace_apicinterrupt \num \sym
641 POP_SECTION_IRQENTRY
642 .endm
644 #ifdef CONFIG_SMP
645 apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt
646 apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt
647 #endif
649 #ifdef CONFIG_X86_UV
650 apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt
651 #endif
653 apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt
654 apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi
656 #ifdef CONFIG_HAVE_KVM
657 apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
658 apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi
659 #endif
661 #ifdef CONFIG_X86_MCE_THRESHOLD
662 apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt
663 #endif
665 #ifdef CONFIG_X86_MCE_AMD
666 apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt
667 #endif
669 #ifdef CONFIG_X86_THERMAL_VECTOR
670 apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt
671 #endif
673 #ifdef CONFIG_SMP
674 apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt
675 apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt
676 apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt
677 #endif
679 apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt
680 apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt
682 #ifdef CONFIG_IRQ_WORK
683 apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt
684 #endif
686 /*
687 * Exception entry points.
688 */
689 #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss) + (TSS_ist + ((x) - 1) * 8)
691 .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1
692 ENTRY(\sym)
693 /* Sanity check */
694 .if \shift_ist != -1 && \paranoid == 0
695 .error "using shift_ist requires paranoid=1"
696 .endif
698 ASM_CLAC
699 PARAVIRT_ADJUST_EXCEPTION_FRAME
701 .ifeq \has_error_code
702 pushq $-1 /* ORIG_RAX: no syscall to restart */
703 .endif
705 ALLOC_PT_GPREGS_ON_STACK
707 .if \paranoid
708 .if \paranoid == 1
709 testb $3, CS(%rsp) /* If coming from userspace, switch stacks */
710 jnz 1f
711 .endif
712 call paranoid_entry
713 .else
714 call error_entry
715 .endif
716 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */
718 .if \paranoid
719 .if \shift_ist != -1
720 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */
721 .else
722 TRACE_IRQS_OFF
723 .endif
724 .endif
726 movq %rsp, %rdi /* pt_regs pointer */
728 .if \has_error_code
729 movq ORIG_RAX(%rsp), %rsi /* get error code */
730 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
731 .else
732 xorl %esi, %esi /* no error code */
733 .endif
735 .if \shift_ist != -1
736 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
737 .endif
739 call \do_sym
741 .if \shift_ist != -1
742 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
743 .endif
745 /* these procedures expect "no swapgs" flag in ebx */
746 .if \paranoid
747 jmp paranoid_exit
748 .else
749 jmp error_exit
750 .endif
752 .if \paranoid == 1
753 /*
754 * Paranoid entry from userspace. Switch stacks and treat it
755 * as a normal entry. This means that paranoid handlers
756 * run in real process context if user_mode(regs).
757 */
758 1:
759 call error_entry
762 movq %rsp, %rdi /* pt_regs pointer */
763 call sync_regs
764 movq %rax, %rsp /* switch stack */
766 movq %rsp, %rdi /* pt_regs pointer */
768 .if \has_error_code
769 movq ORIG_RAX(%rsp), %rsi /* get error code */
770 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
771 .else
772 xorl %esi, %esi /* no error code */
773 .endif
775 call \do_sym
777 jmp error_exit /* %ebx: no swapgs flag */
778 .endif
779 END(\sym)
780 .endm
782 #ifdef CONFIG_TRACING
783 .macro trace_idtentry sym do_sym has_error_code:req
784 idtentry trace(\sym) trace(\do_sym) has_error_code=\has_error_code
785 idtentry \sym \do_sym has_error_code=\has_error_code
786 .endm
787 #else
788 .macro trace_idtentry sym do_sym has_error_code:req
789 idtentry \sym \do_sym has_error_code=\has_error_code
790 .endm
791 #endif
793 idtentry divide_error do_divide_error has_error_code=0
794 idtentry overflow do_overflow has_error_code=0
795 idtentry bounds do_bounds has_error_code=0
796 idtentry invalid_op do_invalid_op has_error_code=0
797 idtentry device_not_available do_device_not_available has_error_code=0
798 idtentry double_fault do_double_fault has_error_code=1 paranoid=2
799 idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
800 idtentry invalid_TSS do_invalid_TSS has_error_code=1
801 idtentry segment_not_present do_segment_not_present has_error_code=1
802 idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0
803 idtentry coprocessor_error do_coprocessor_error has_error_code=0
804 idtentry alignment_check do_alignment_check has_error_code=1
805 idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0
808 /*
809 * Reload gs selector with exception handling
810 * edi: new selector
811 */
812 ENTRY(native_load_gs_index)
813 pushfq
814 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI)
815 SWAPGS
816 .Lgs_change:
817 movl %edi, %gs
818 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
819 SWAPGS
820 popfq
821 ret
822 END(native_load_gs_index)
823 EXPORT_SYMBOL(native_load_gs_index)
825 _ASM_EXTABLE(.Lgs_change, bad_gs)
826 .section .fixup, "ax"
827 /* running with kernelgs */
828 bad_gs:
829 SWAPGS /* switch back to user gs */
830 .macro ZAP_GS
831 /* This can't be a string because the preprocessor needs to see it. */
832 movl $__USER_DS, %eax
833 movl %eax, %gs
834 .endm
835 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
836 xorl %eax, %eax
837 movl %eax, %gs
838 jmp 2b
839 .previous
841 /* Call softirq on interrupt stack. Interrupts are off. */
842 ENTRY(do_softirq_own_stack)
843 pushq %rbp
844 mov %rsp, %rbp
845 incl PER_CPU_VAR(irq_count)
846 cmove PER_CPU_VAR(irq_stack_ptr), %rsp
847 push %rbp /* frame pointer backlink */
848 call __do_softirq
849 leaveq
850 decl PER_CPU_VAR(irq_count)
851 ret
852 END(do_softirq_own_stack)
854 #ifdef CONFIG_XEN
855 idtentry xen_hypervisor_callback xen_do_hypervisor_callback has_error_code=0
857 /*
858 * A note on the "critical region" in our callback handler.
859 * We want to avoid stacking callback handlers due to events occurring
860 * during handling of the last event. To do this, we keep events disabled
861 * until we've done all processing. HOWEVER, we must enable events before
862 * popping the stack frame (can't be done atomically) and so it would still
863 * be possible to get enough handler activations to overflow the stack.
864 * Although unlikely, bugs of that kind are hard to track down, so we'd
865 * like to avoid the possibility.
866 * So, on entry to the handler we detect whether we interrupted an
867 * existing activation in its critical region -- if so, we pop the current
868 * activation and restart the handler using the previous one.
869 */
870 ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */
872 /*
873 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
874 * see the correct pointer to the pt_regs
875 */
876 movq %rdi, %rsp /* we don't return, adjust the stack frame */
877 11: incl PER_CPU_VAR(irq_count)
878 movq %rsp, %rbp
879 cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp
880 pushq %rbp /* frame pointer backlink */
881 call xen_evtchn_do_upcall
882 popq %rsp
883 decl PER_CPU_VAR(irq_count)
884 #ifndef CONFIG_PREEMPT
885 call xen_maybe_preempt_hcall
886 #endif
887 jmp error_exit
888 END(xen_do_hypervisor_callback)
890 /*
891 * Hypervisor uses this for application faults while it executes.
892 * We get here for two reasons:
893 * 1. Fault while reloading DS, ES, FS or GS
894 * 2. Fault while executing IRET
895 * Category 1 we do not need to fix up as Xen has already reloaded all segment
896 * registers that could be reloaded and zeroed the others.
897 * Category 2 we fix up by killing the current process. We cannot use the
898 * normal Linux return path in this case because if we use the IRET hypercall
899 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
900 * We distinguish between categories by comparing each saved segment register
901 * with its current contents: any discrepancy means we in category 1.
902 */
903 ENTRY(xen_failsafe_callback)
904 movl %ds, %ecx
905 cmpw %cx, 0x10(%rsp)
906 jne 1f
907 movl %es, %ecx
908 cmpw %cx, 0x18(%rsp)
909 jne 1f
910 movl %fs, %ecx
911 cmpw %cx, 0x20(%rsp)
912 jne 1f
913 movl %gs, %ecx
914 cmpw %cx, 0x28(%rsp)
915 jne 1f
916 /* All segments match their saved values => Category 2 (Bad IRET). */
917 movq (%rsp), %rcx
918 movq 8(%rsp), %r11
919 addq $0x30, %rsp
920 pushq $0 /* RIP */
921 pushq %r11
922 pushq %rcx
923 jmp general_protection
924 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
925 movq (%rsp), %rcx
926 movq 8(%rsp), %r11
927 addq $0x30, %rsp
928 pushq $-1 /* orig_ax = -1 => not a system call */
929 ALLOC_PT_GPREGS_ON_STACK
930 SAVE_C_REGS
931 SAVE_EXTRA_REGS
932 jmp error_exit
933 END(xen_failsafe_callback)
935 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
936 xen_hvm_callback_vector xen_evtchn_do_upcall
938 #endif /* CONFIG_XEN */
940 #if IS_ENABLED(CONFIG_HYPERV)
941 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
942 hyperv_callback_vector hyperv_vector_handler
943 #endif /* CONFIG_HYPERV */
945 idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
946 idtentry int3 do_int3 has_error_code=0
947 idtentry stack_segment do_stack_segment has_error_code=1
949 #ifdef CONFIG_XEN
950 idtentry xen_debug do_debug has_error_code=0
951 idtentry xen_int3 do_int3 has_error_code=0
952 idtentry xen_stack_segment do_stack_segment has_error_code=1
953 #endif
955 idtentry general_protection do_general_protection has_error_code=1
956 trace_idtentry page_fault do_page_fault has_error_code=1
958 #ifdef CONFIG_KVM_GUEST
959 idtentry async_page_fault do_async_page_fault has_error_code=1
960 #endif
962 #ifdef CONFIG_X86_MCE
963 idtentry machine_check do_mce has_error_code=0 paranoid=1
964 #endif
966 /*
967 * Save all registers in pt_regs, and switch gs if needed.
968 * Use slow, but surefire "are we in kernel?" check.
969 *
970 * Return: ebx=0: needs swapgs but not SWITCH_USER_CR3 in paranoid_exit
971 * ebx=1: needs neither swapgs nor SWITCH_USER_CR3 in paranoid_exit
972 * ebx=2: needs both swapgs and SWITCH_USER_CR3 in paranoid_exit
973 * ebx=3: needs SWITCH_USER_CR3 but not swapgs in paranoid_exit
974 */
975 ENTRY(paranoid_entry)
976 cld
977 SAVE_C_REGS 8
978 SAVE_EXTRA_REGS 8
979 movl $1, %ebx
980 movl $MSR_GS_BASE, %ecx
981 rdmsr
982 testl %edx, %edx
983 js 1f /* negative -> in kernel */
984 SWAPGS
985 xorl %ebx, %ebx
986 1:
987 #ifdef CONFIG_PAGE_TABLE_ISOLATION
988 /*
989 * We might have come in between a swapgs and a SWITCH_KERNEL_CR3
990 * on entry, or between a SWITCH_USER_CR3 and a swapgs on exit.
991 * Do a conditional SWITCH_KERNEL_CR3: this could safely be done
992 * unconditionally, but we need to find out whether the reverse
993 * should be done on return (conveyed to paranoid_exit in %ebx).
994 */
995 ALTERNATIVE "jmp 2f", "movq %cr3, %rax", X86_FEATURE_KAISER
996 testl $KAISER_SHADOW_PGD_OFFSET, %eax
997 jz 2f
998 orl $2, %ebx
999 andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
1000 /* If PCID enabled, set X86_CR3_PCID_NOFLUSH_BIT */
1001 ALTERNATIVE "", "bts $63, %rax", X86_FEATURE_PCID
1002 movq %rax, %cr3
1003 2:
1004 #endif
1005 ret
1006 END(paranoid_entry)
1008 /*
1009 * "Paranoid" exit path from exception stack. This is invoked
1010 * only on return from non-NMI IST interrupts that came
1011 * from kernel space.
1012 *
1013 * We may be returning to very strange contexts (e.g. very early
1014 * in syscall entry), so checking for preemption here would
1015 * be complicated. Fortunately, we there's no good reason
1016 * to try to handle preemption here.
1017 *
1018 * On entry: ebx=0: needs swapgs but not SWITCH_USER_CR3
1019 * ebx=1: needs neither swapgs nor SWITCH_USER_CR3
1020 * ebx=2: needs both swapgs and SWITCH_USER_CR3
1021 * ebx=3: needs SWITCH_USER_CR3 but not swapgs
1022 */
1023 ENTRY(paranoid_exit)
1024 DISABLE_INTERRUPTS(CLBR_NONE)
1025 TRACE_IRQS_OFF_DEBUG
1026 TRACE_IRQS_IRETQ_DEBUG
1027 #ifdef CONFIG_PAGE_TABLE_ISOLATION
1028 /* No ALTERNATIVE for X86_FEATURE_KAISER: paranoid_entry sets %ebx */
1029 testl $2, %ebx /* SWITCH_USER_CR3 needed? */
1030 jz paranoid_exit_no_switch
1031 SWITCH_USER_CR3
1032 paranoid_exit_no_switch:
1033 #endif
1034 testl $1, %ebx /* swapgs needed? */
1035 jnz paranoid_exit_no_swapgs
1036 SWAPGS_UNSAFE_STACK
1037 paranoid_exit_no_swapgs:
1038 RESTORE_EXTRA_REGS
1039 RESTORE_C_REGS
1040 REMOVE_PT_GPREGS_FROM_STACK 8
1041 INTERRUPT_RETURN
1042 END(paranoid_exit)
1044 /*
1045 * Save all registers in pt_regs, and switch gs if needed.
1046 * Return: EBX=0: came from user mode; EBX=1: otherwise
1047 */
1048 ENTRY(error_entry)
1049 cld
1050 SAVE_C_REGS 8
1051 SAVE_EXTRA_REGS 8
1052 /*
1053 * error_entry() always returns with a kernel gsbase and
1054 * CR3. We must also have a kernel CR3/gsbase before
1055 * calling TRACE_IRQS_*. Just unconditionally switch to
1056 * the kernel CR3 here.
1057 */
1058 SWITCH_KERNEL_CR3
1059 xorl %ebx, %ebx
1060 testb $3, CS+8(%rsp)
1061 jz .Lerror_kernelspace
1063 /*
1064 * We entered from user mode or we're pretending to have entered
1065 * from user mode due to an IRET fault.
1066 */
1067 SWAPGS
1069 .Lerror_entry_from_usermode_after_swapgs:
1070 /*
1071 * We need to tell lockdep that IRQs are off. We can't do this until
1072 * we fix gsbase, and we should do it before enter_from_user_mode
1073 * (which can take locks).
1074 */
1075 TRACE_IRQS_OFF
1076 CALL_enter_from_user_mode
1077 ret
1079 .Lerror_entry_done:
1080 TRACE_IRQS_OFF
1081 ret
1083 /*
1084 * There are two places in the kernel that can potentially fault with
1085 * usergs. Handle them here. B stepping K8s sometimes report a
1086 * truncated RIP for IRET exceptions returning to compat mode. Check
1087 * for these here too.
1088 */
1089 .Lerror_kernelspace:
1090 incl %ebx
1091 leaq native_irq_return_iret(%rip), %rcx
1092 cmpq %rcx, RIP+8(%rsp)
1093 je .Lerror_bad_iret
1094 movl %ecx, %eax /* zero extend */
1095 cmpq %rax, RIP+8(%rsp)
1096 je .Lbstep_iret
1097 cmpq $.Lgs_change, RIP+8(%rsp)
1098 jne .Lerror_entry_done
1100 /*
1101 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1102 * gsbase and proceed. We'll fix up the exception and land in
1103 * .Lgs_change's error handler with kernel gsbase.
1104 */
1105 SWAPGS
1106 jmp .Lerror_entry_done
1108 .Lbstep_iret:
1109 /* Fix truncated RIP */
1110 movq %rcx, RIP+8(%rsp)
1111 /* fall through */
1113 .Lerror_bad_iret:
1114 /*
1115 * We came from an IRET to user mode, so we have user gsbase.
1116 * Switch to kernel gsbase:
1117 */
1118 SWAPGS
1120 /*
1121 * Pretend that the exception came from user mode: set up pt_regs
1122 * as if we faulted immediately after IRET and clear EBX so that
1123 * error_exit knows that we will be returning to user mode.
1124 */
1125 mov %rsp, %rdi
1126 call fixup_bad_iret
1127 mov %rax, %rsp
1128 decl %ebx
1129 jmp .Lerror_entry_from_usermode_after_swapgs
1130 END(error_entry)
1133 /*
1134 * On entry, EBX is a "return to kernel mode" flag:
1135 * 1: already in kernel mode, don't need SWAPGS
1136 * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode
1137 */
1138 ENTRY(error_exit)
1139 movl %ebx, %eax
1140 DISABLE_INTERRUPTS(CLBR_NONE)
1141 TRACE_IRQS_OFF
1142 testl %eax, %eax
1143 jnz retint_kernel
1144 jmp retint_user
1145 END(error_exit)
1147 /* Runs on exception stack */
1148 ENTRY(nmi)
1149 /*
1150 * Fix up the exception frame if we're on Xen.
1151 * PARAVIRT_ADJUST_EXCEPTION_FRAME is guaranteed to push at most
1152 * one value to the stack on native, so it may clobber the rdx
1153 * scratch slot, but it won't clobber any of the important
1154 * slots past it.
1155 *
1156 * Xen is a different story, because the Xen frame itself overlaps
1157 * the "NMI executing" variable.
1158 */
1159 PARAVIRT_ADJUST_EXCEPTION_FRAME
1161 /*
1162 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1163 * the iretq it performs will take us out of NMI context.
1164 * This means that we can have nested NMIs where the next
1165 * NMI is using the top of the stack of the previous NMI. We
1166 * can't let it execute because the nested NMI will corrupt the
1167 * stack of the previous NMI. NMI handlers are not re-entrant
1168 * anyway.
1169 *
1170 * To handle this case we do the following:
1171 * Check the a special location on the stack that contains
1172 * a variable that is set when NMIs are executing.
1173 * The interrupted task's stack is also checked to see if it
1174 * is an NMI stack.
1175 * If the variable is not set and the stack is not the NMI
1176 * stack then:
1177 * o Set the special variable on the stack
1178 * o Copy the interrupt frame into an "outermost" location on the
1179 * stack
1180 * o Copy the interrupt frame into an "iret" location on the stack
1181 * o Continue processing the NMI
1182 * If the variable is set or the previous stack is the NMI stack:
1183 * o Modify the "iret" location to jump to the repeat_nmi
1184 * o return back to the first NMI
1185 *
1186 * Now on exit of the first NMI, we first clear the stack variable
1187 * The NMI stack will tell any nested NMIs at that point that it is
1188 * nested. Then we pop the stack normally with iret, and if there was
1189 * a nested NMI that updated the copy interrupt stack frame, a
1190 * jump will be made to the repeat_nmi code that will handle the second
1191 * NMI.
1192 *
1193 * However, espfix prevents us from directly returning to userspace
1194 * with a single IRET instruction. Similarly, IRET to user mode
1195 * can fault. We therefore handle NMIs from user space like
1196 * other IST entries.
1197 */
1199 ASM_CLAC
1201 /* Use %rdx as our temp variable throughout */
1202 pushq %rdx
1204 testb $3, CS-RIP+8(%rsp)
1205 jz .Lnmi_from_kernel
1207 /*
1208 * NMI from user mode. We need to run on the thread stack, but we
1209 * can't go through the normal entry paths: NMIs are masked, and
1210 * we don't want to enable interrupts, because then we'll end
1211 * up in an awkward situation in which IRQs are on but NMIs
1212 * are off.
1213 *
1214 * We also must not push anything to the stack before switching
1215 * stacks lest we corrupt the "NMI executing" variable.
1216 */
1218 SWAPGS_UNSAFE_STACK
1219 /*
1220 * percpu variables are mapped with user CR3, so no need
1221 * to switch CR3 here.
1222 */
1223 cld
1224 movq %rsp, %rdx
1225 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
1226 pushq 5*8(%rdx) /* pt_regs->ss */
1227 pushq 4*8(%rdx) /* pt_regs->rsp */
1228 pushq 3*8(%rdx) /* pt_regs->flags */
1229 pushq 2*8(%rdx) /* pt_regs->cs */
1230 pushq 1*8(%rdx) /* pt_regs->rip */
1231 pushq $-1 /* pt_regs->orig_ax */
1232 pushq %rdi /* pt_regs->di */
1233 pushq %rsi /* pt_regs->si */
1234 pushq (%rdx) /* pt_regs->dx */
1235 pushq %rcx /* pt_regs->cx */
1236 pushq %rax /* pt_regs->ax */
1237 pushq %r8 /* pt_regs->r8 */
1238 pushq %r9 /* pt_regs->r9 */
1239 pushq %r10 /* pt_regs->r10 */
1240 pushq %r11 /* pt_regs->r11 */
1241 pushq %rbx /* pt_regs->rbx */
1242 pushq %rbp /* pt_regs->rbp */
1243 pushq %r12 /* pt_regs->r12 */
1244 pushq %r13 /* pt_regs->r13 */
1245 pushq %r14 /* pt_regs->r14 */
1246 pushq %r15 /* pt_regs->r15 */
1248 /*
1249 * At this point we no longer need to worry about stack damage
1250 * due to nesting -- we're on the normal thread stack and we're
1251 * done with the NMI stack.
1252 */
1254 movq %rsp, %rdi
1255 movq $-1, %rsi
1256 #ifdef CONFIG_PAGE_TABLE_ISOLATION
1257 /* Unconditionally use kernel CR3 for do_nmi() */
1258 /* %rax is saved above, so OK to clobber here */
1259 ALTERNATIVE "jmp 2f", "movq %cr3, %rax", X86_FEATURE_KAISER
1260 /* If PCID enabled, NOFLUSH now and NOFLUSH on return */
1261 ALTERNATIVE "", "bts $63, %rax", X86_FEATURE_PCID
1262 pushq %rax
1263 /* mask off "user" bit of pgd address and 12 PCID bits: */
1264 andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
1265 movq %rax, %cr3
1266 2:
1267 #endif
1268 call do_nmi
1270 #ifdef CONFIG_PAGE_TABLE_ISOLATION
1271 /*
1272 * Unconditionally restore CR3. I know we return to
1273 * kernel code that needs user CR3, but do we ever return
1274 * to "user mode" where we need the kernel CR3?
1275 */
1276 ALTERNATIVE "", "popq %rax; movq %rax, %cr3", X86_FEATURE_KAISER
1277 #endif
1279 /*
1280 * Return back to user mode. We must *not* do the normal exit
1281 * work, because we don't want to enable interrupts. Do not
1282 * switch to user CR3: we might be going back to kernel code
1283 * that had a user CR3 set.
1284 */
1285 SWAPGS
1286 jmp restore_c_regs_and_iret
1288 .Lnmi_from_kernel:
1289 /*
1290 * Here's what our stack frame will look like:
1291 * +---------------------------------------------------------+
1292 * | original SS |
1293 * | original Return RSP |
1294 * | original RFLAGS |
1295 * | original CS |
1296 * | original RIP |
1297 * +---------------------------------------------------------+
1298 * | temp storage for rdx |
1299 * +---------------------------------------------------------+
1300 * | "NMI executing" variable |
1301 * +---------------------------------------------------------+
1302 * | iret SS } Copied from "outermost" frame |
1303 * | iret Return RSP } on each loop iteration; overwritten |
1304 * | iret RFLAGS } by a nested NMI to force another |
1305 * | iret CS } iteration if needed. |
1306 * | iret RIP } |
1307 * +---------------------------------------------------------+
1308 * | outermost SS } initialized in first_nmi; |
1309 * | outermost Return RSP } will not be changed before |
1310 * | outermost RFLAGS } NMI processing is done. |
1311 * | outermost CS } Copied to "iret" frame on each |
1312 * | outermost RIP } iteration. |
1313 * +---------------------------------------------------------+
1314 * | pt_regs |
1315 * +---------------------------------------------------------+
1316 *
1317 * The "original" frame is used by hardware. Before re-enabling
1318 * NMIs, we need to be done with it, and we need to leave enough
1319 * space for the asm code here.
1320 *
1321 * We return by executing IRET while RSP points to the "iret" frame.
1322 * That will either return for real or it will loop back into NMI
1323 * processing.
1324 *
1325 * The "outermost" frame is copied to the "iret" frame on each
1326 * iteration of the loop, so each iteration starts with the "iret"
1327 * frame pointing to the final return target.
1328 */
1330 /*
1331 * Determine whether we're a nested NMI.
1332 *
1333 * If we interrupted kernel code between repeat_nmi and
1334 * end_repeat_nmi, then we are a nested NMI. We must not
1335 * modify the "iret" frame because it's being written by
1336 * the outer NMI. That's okay; the outer NMI handler is
1337 * about to about to call do_nmi anyway, so we can just
1338 * resume the outer NMI.
1339 */
1341 movq $repeat_nmi, %rdx
1342 cmpq 8(%rsp), %rdx
1343 ja 1f
1344 movq $end_repeat_nmi, %rdx
1345 cmpq 8(%rsp), %rdx
1346 ja nested_nmi_out
1347 1:
1349 /*
1350 * Now check "NMI executing". If it's set, then we're nested.
1351 * This will not detect if we interrupted an outer NMI just
1352 * before IRET.
1353 */
1354 cmpl $1, -8(%rsp)
1355 je nested_nmi
1357 /*
1358 * Now test if the previous stack was an NMI stack. This covers
1359 * the case where we interrupt an outer NMI after it clears
1360 * "NMI executing" but before IRET. We need to be careful, though:
1361 * there is one case in which RSP could point to the NMI stack
1362 * despite there being no NMI active: naughty userspace controls
1363 * RSP at the very beginning of the SYSCALL targets. We can
1364 * pull a fast one on naughty userspace, though: we program
1365 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1366 * if it controls the kernel's RSP. We set DF before we clear
1367 * "NMI executing".
1368 */
1369 lea 6*8(%rsp), %rdx
1370 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1371 cmpq %rdx, 4*8(%rsp)
1372 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1373 ja first_nmi
1375 subq $EXCEPTION_STKSZ, %rdx
1376 cmpq %rdx, 4*8(%rsp)
1377 /* If it is below the NMI stack, it is a normal NMI */
1378 jb first_nmi
1380 /* Ah, it is within the NMI stack. */
1382 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1383 jz first_nmi /* RSP was user controlled. */
1385 /* This is a nested NMI. */
1387 nested_nmi:
1388 /*
1389 * Modify the "iret" frame to point to repeat_nmi, forcing another
1390 * iteration of NMI handling.
1391 */
1392 subq $8, %rsp
1393 leaq -10*8(%rsp), %rdx
1394 pushq $__KERNEL_DS
1395 pushq %rdx
1396 pushfq
1397 pushq $__KERNEL_CS
1398 pushq $repeat_nmi
1400 /* Put stack back */
1401 addq $(6*8), %rsp
1403 nested_nmi_out:
1404 popq %rdx
1406 /* We are returning to kernel mode, so this cannot result in a fault. */
1407 INTERRUPT_RETURN
1409 first_nmi:
1410 /* Restore rdx. */
1411 movq (%rsp), %rdx
1413 /* Make room for "NMI executing". */
1414 pushq $0
1416 /* Leave room for the "iret" frame */
1417 subq $(5*8), %rsp
1419 /* Copy the "original" frame to the "outermost" frame */
1420 .rept 5
1421 pushq 11*8(%rsp)
1422 .endr
1424 /* Everything up to here is safe from nested NMIs */
1426 #ifdef CONFIG_DEBUG_ENTRY
1427 /*
1428 * For ease of testing, unmask NMIs right away. Disabled by
1429 * default because IRET is very expensive.
1430 */
1431 pushq $0 /* SS */
1432 pushq %rsp /* RSP (minus 8 because of the previous push) */
1433 addq $8, (%rsp) /* Fix up RSP */
1434 pushfq /* RFLAGS */
1435 pushq $__KERNEL_CS /* CS */
1436 pushq $1f /* RIP */
1437 INTERRUPT_RETURN /* continues at repeat_nmi below */
1438 1:
1439 #endif
1441 repeat_nmi:
1442 /*
1443 * If there was a nested NMI, the first NMI's iret will return
1444 * here. But NMIs are still enabled and we can take another
1445 * nested NMI. The nested NMI checks the interrupted RIP to see
1446 * if it is between repeat_nmi and end_repeat_nmi, and if so
1447 * it will just return, as we are about to repeat an NMI anyway.
1448 * This makes it safe to copy to the stack frame that a nested
1449 * NMI will update.
1450 *
1451 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1452 * we're repeating an NMI, gsbase has the same value that it had on
1453 * the first iteration. paranoid_entry will load the kernel
1454 * gsbase if needed before we call do_nmi. "NMI executing"
1455 * is zero.
1456 */
1457 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1459 /*
1460 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1461 * here must not modify the "iret" frame while we're writing to
1462 * it or it will end up containing garbage.
1463 */
1464 addq $(10*8), %rsp
1465 .rept 5
1466 pushq -6*8(%rsp)
1467 .endr
1468 subq $(5*8), %rsp
1469 end_repeat_nmi:
1471 /*
1472 * Everything below this point can be preempted by a nested NMI.
1473 * If this happens, then the inner NMI will change the "iret"
1474 * frame to point back to repeat_nmi.
1475 */
1476 pushq $-1 /* ORIG_RAX: no syscall to restart */
1477 ALLOC_PT_GPREGS_ON_STACK
1479 /*
1480 * Use the same approach as paranoid_entry to handle SWAPGS, but
1481 * without CR3 handling since we do that differently in NMIs. No
1482 * need to use paranoid_exit as we should not be calling schedule
1483 * in NMI context. Even with normal interrupts enabled. An NMI
1484 * should not be setting NEED_RESCHED or anything that normal
1485 * interrupts and exceptions might do.
1486 */
1487 cld
1488 SAVE_C_REGS
1489 SAVE_EXTRA_REGS
1490 movl $1, %ebx
1491 movl $MSR_GS_BASE, %ecx
1492 rdmsr
1493 testl %edx, %edx
1494 js 1f /* negative -> in kernel */
1495 SWAPGS
1496 xorl %ebx, %ebx
1497 1:
1498 movq %rsp, %rdi
1499 movq $-1, %rsi
1500 #ifdef CONFIG_PAGE_TABLE_ISOLATION
1501 /* Unconditionally use kernel CR3 for do_nmi() */
1502 /* %rax is saved above, so OK to clobber here */
1503 ALTERNATIVE "jmp 2f", "movq %cr3, %rax", X86_FEATURE_KAISER
1504 /* If PCID enabled, NOFLUSH now and NOFLUSH on return */
1505 ALTERNATIVE "", "bts $63, %rax", X86_FEATURE_PCID
1506 pushq %rax
1507 /* mask off "user" bit of pgd address and 12 PCID bits: */
1508 andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
1509 movq %rax, %cr3
1510 2:
1511 #endif
1513 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */
1514 call do_nmi
1516 #ifdef CONFIG_PAGE_TABLE_ISOLATION
1517 /*
1518 * Unconditionally restore CR3. We might be returning to
1519 * kernel code that needs user CR3, like just just before
1520 * a sysret.
1521 */
1522 ALTERNATIVE "", "popq %rax; movq %rax, %cr3", X86_FEATURE_KAISER
1523 #endif
1525 testl %ebx, %ebx /* swapgs needed? */
1526 jnz nmi_restore
1527 nmi_swapgs:
1528 /* We fixed up CR3 above, so no need to switch it here */
1529 SWAPGS_UNSAFE_STACK
1530 nmi_restore:
1531 RESTORE_EXTRA_REGS
1532 RESTORE_C_REGS
1534 /* Point RSP at the "iret" frame. */
1535 REMOVE_PT_GPREGS_FROM_STACK 6*8
1537 /*
1538 * Clear "NMI executing". Set DF first so that we can easily
1539 * distinguish the remaining code between here and IRET from
1540 * the SYSCALL entry and exit paths. On a native kernel, we
1541 * could just inspect RIP, but, on paravirt kernels,
1542 * INTERRUPT_RETURN can translate into a jump into a
1543 * hypercall page.
1544 */
1545 std
1546 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1548 /*
1549 * INTERRUPT_RETURN reads the "iret" frame and exits the NMI
1550 * stack in a single instruction. We are returning to kernel
1551 * mode, so this cannot result in a fault.
1552 */
1553 INTERRUPT_RETURN
1554 END(nmi)
1556 ENTRY(ignore_sysret)
1557 mov $-ENOSYS, %eax
1558 sysret
1559 END(ignore_sysret)
1561 ENTRY(rewind_stack_do_exit)
1562 /* Prevent any naive code from trying to unwind to our caller. */
1563 xorl %ebp, %ebp
1565 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax
1566 leaq -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%rax), %rsp
1568 call do_exit
1569 1: jmp 1b
1570 END(rewind_stack_do_exit)