2 * Copyright (C) 2013 Broadcom Corporation
3 * Copyright 2013 Linaro Limited
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <linux/of_address.h>
20 /* These are used when a selector or trigger is found to be unneeded */
21 #define selector_clear_exists(sel) ((sel)->width = 0)
22 #define trigger_clear_exists(trig) FLAG_CLEAR(trig, TRIG, EXISTS)
24 /* Validity checking */
26 static bool ccu_data_offsets_valid(struct ccu_data
*ccu
)
28 struct ccu_policy
*ccu_policy
= &ccu
->policy
;
31 limit
= ccu
->range
- sizeof(u32
);
32 limit
= round_down(limit
, sizeof(u32
));
33 if (ccu_policy_exists(ccu_policy
)) {
34 if (ccu_policy
->enable
.offset
> limit
) {
35 pr_err("%s: bad policy enable offset for %s "
36 "(%u > %u)\n", __func__
,
37 ccu
->name
, ccu_policy
->enable
.offset
, limit
);
40 if (ccu_policy
->control
.offset
> limit
) {
41 pr_err("%s: bad policy control offset for %s "
42 "(%u > %u)\n", __func__
,
43 ccu
->name
, ccu_policy
->control
.offset
, limit
);
51 static bool clk_requires_trigger(struct kona_clk
*bcm_clk
)
53 struct peri_clk_data
*peri
= bcm_clk
->u
.peri
;
54 struct bcm_clk_sel
*sel
;
55 struct bcm_clk_div
*div
;
57 if (bcm_clk
->type
!= bcm_clk_peri
)
61 if (sel
->parent_count
&& selector_exists(sel
))
65 if (!divider_exists(div
))
68 /* Fixed dividers don't need triggers */
69 if (!divider_is_fixed(div
))
74 return divider_exists(div
) && !divider_is_fixed(div
);
77 static bool peri_clk_data_offsets_valid(struct kona_clk
*bcm_clk
)
79 struct peri_clk_data
*peri
;
80 struct bcm_clk_policy
*policy
;
81 struct bcm_clk_gate
*gate
;
82 struct bcm_clk_hyst
*hyst
;
83 struct bcm_clk_div
*div
;
84 struct bcm_clk_sel
*sel
;
85 struct bcm_clk_trig
*trig
;
90 BUG_ON(bcm_clk
->type
!= bcm_clk_peri
);
91 peri
= bcm_clk
->u
.peri
;
92 name
= bcm_clk
->init_data
.name
;
93 range
= bcm_clk
->ccu
->range
;
95 limit
= range
- sizeof(u32
);
96 limit
= round_down(limit
, sizeof(u32
));
98 policy
= &peri
->policy
;
99 if (policy_exists(policy
)) {
100 if (policy
->offset
> limit
) {
101 pr_err("%s: bad policy offset for %s (%u > %u)\n",
102 __func__
, name
, policy
->offset
, limit
);
109 if (gate_exists(gate
)) {
110 if (gate
->offset
> limit
) {
111 pr_err("%s: bad gate offset for %s (%u > %u)\n",
112 __func__
, name
, gate
->offset
, limit
);
116 if (hyst_exists(hyst
)) {
117 if (hyst
->offset
> limit
) {
118 pr_err("%s: bad hysteresis offset for %s "
119 "(%u > %u)\n", __func__
,
120 name
, hyst
->offset
, limit
);
124 } else if (hyst_exists(hyst
)) {
125 pr_err("%s: hysteresis but no gate for %s\n", __func__
, name
);
130 if (divider_exists(div
)) {
131 if (div
->u
.s
.offset
> limit
) {
132 pr_err("%s: bad divider offset for %s (%u > %u)\n",
133 __func__
, name
, div
->u
.s
.offset
, limit
);
138 div
= &peri
->pre_div
;
139 if (divider_exists(div
)) {
140 if (div
->u
.s
.offset
> limit
) {
141 pr_err("%s: bad pre-divider offset for %s "
143 __func__
, name
, div
->u
.s
.offset
, limit
);
149 if (selector_exists(sel
)) {
150 if (sel
->offset
> limit
) {
151 pr_err("%s: bad selector offset for %s (%u > %u)\n",
152 __func__
, name
, sel
->offset
, limit
);
158 if (trigger_exists(trig
)) {
159 if (trig
->offset
> limit
) {
160 pr_err("%s: bad trigger offset for %s (%u > %u)\n",
161 __func__
, name
, trig
->offset
, limit
);
166 trig
= &peri
->pre_trig
;
167 if (trigger_exists(trig
)) {
168 if (trig
->offset
> limit
) {
169 pr_err("%s: bad pre-trigger offset for %s (%u > %u)\n",
170 __func__
, name
, trig
->offset
, limit
);
178 /* A bit position must be less than the number of bits in a 32-bit register. */
179 static bool bit_posn_valid(u32 bit_posn
, const char *field_name
,
180 const char *clock_name
)
182 u32 limit
= BITS_PER_BYTE
* sizeof(u32
) - 1;
184 if (bit_posn
> limit
) {
185 pr_err("%s: bad %s bit for %s (%u > %u)\n", __func__
,
186 field_name
, clock_name
, bit_posn
, limit
);
193 * A bitfield must be at least 1 bit wide. Both the low-order and
194 * high-order bits must lie within a 32-bit register. We require
195 * fields to be less than 32 bits wide, mainly because we use
196 * shifting to produce field masks, and shifting a full word width
197 * is not well-defined by the C standard.
199 static bool bitfield_valid(u32 shift
, u32 width
, const char *field_name
,
200 const char *clock_name
)
202 u32 limit
= BITS_PER_BYTE
* sizeof(u32
);
205 pr_err("%s: bad %s field width 0 for %s\n", __func__
,
206 field_name
, clock_name
);
209 if (shift
+ width
> limit
) {
210 pr_err("%s: bad %s for %s (%u + %u > %u)\n", __func__
,
211 field_name
, clock_name
, shift
, width
, limit
);
218 ccu_policy_valid(struct ccu_policy
*ccu_policy
, const char *ccu_name
)
220 struct bcm_lvm_en
*enable
= &ccu_policy
->enable
;
221 struct bcm_policy_ctl
*control
;
223 if (!bit_posn_valid(enable
->bit
, "policy enable", ccu_name
))
226 control
= &ccu_policy
->control
;
227 if (!bit_posn_valid(control
->go_bit
, "policy control GO", ccu_name
))
230 if (!bit_posn_valid(control
->atl_bit
, "policy control ATL", ccu_name
))
233 if (!bit_posn_valid(control
->ac_bit
, "policy control AC", ccu_name
))
239 static bool policy_valid(struct bcm_clk_policy
*policy
, const char *clock_name
)
241 if (!bit_posn_valid(policy
->bit
, "policy", clock_name
))
248 * All gates, if defined, have a status bit, and for hardware-only
249 * gates, that's it. Gates that can be software controlled also
250 * have an enable bit. And a gate that can be hardware or software
251 * controlled will have a hardware/software select bit.
253 static bool gate_valid(struct bcm_clk_gate
*gate
, const char *field_name
,
254 const char *clock_name
)
256 if (!bit_posn_valid(gate
->status_bit
, "gate status", clock_name
))
259 if (gate_is_sw_controllable(gate
)) {
260 if (!bit_posn_valid(gate
->en_bit
, "gate enable", clock_name
))
263 if (gate_is_hw_controllable(gate
)) {
264 if (!bit_posn_valid(gate
->hw_sw_sel_bit
,
270 BUG_ON(!gate_is_hw_controllable(gate
));
276 static bool hyst_valid(struct bcm_clk_hyst
*hyst
, const char *clock_name
)
278 if (!bit_posn_valid(hyst
->en_bit
, "hysteresis enable", clock_name
))
281 if (!bit_posn_valid(hyst
->val_bit
, "hysteresis value", clock_name
))
288 * A selector bitfield must be valid. Its parent_sel array must
289 * also be reasonable for the field.
291 static bool sel_valid(struct bcm_clk_sel
*sel
, const char *field_name
,
292 const char *clock_name
)
294 if (!bitfield_valid(sel
->shift
, sel
->width
, field_name
, clock_name
))
297 if (sel
->parent_count
) {
302 * Make sure the selector field can hold all the
303 * selector values we expect to be able to use. A
304 * clock only needs to have a selector defined if it
305 * has more than one parent. And in that case the
306 * highest selector value will be in the last entry
309 max_sel
= sel
->parent_sel
[sel
->parent_count
- 1];
310 limit
= (1 << sel
->width
) - 1;
311 if (max_sel
> limit
) {
312 pr_err("%s: bad selector for %s "
313 "(%u needs > %u bits)\n",
314 __func__
, clock_name
, max_sel
,
319 pr_warn("%s: ignoring selector for %s (no parents)\n",
320 __func__
, clock_name
);
321 selector_clear_exists(sel
);
322 kfree(sel
->parent_sel
);
323 sel
->parent_sel
= NULL
;
330 * A fixed divider just needs to be non-zero. A variable divider
331 * has to have a valid divider bitfield, and if it has a fraction,
332 * the width of the fraction must not be no more than the width of
333 * the divider as a whole.
335 static bool div_valid(struct bcm_clk_div
*div
, const char *field_name
,
336 const char *clock_name
)
338 if (divider_is_fixed(div
)) {
339 /* Any fixed divider value but 0 is OK */
340 if (div
->u
.fixed
== 0) {
341 pr_err("%s: bad %s fixed value 0 for %s\n", __func__
,
342 field_name
, clock_name
);
347 if (!bitfield_valid(div
->u
.s
.shift
, div
->u
.s
.width
,
348 field_name
, clock_name
))
351 if (divider_has_fraction(div
))
352 if (div
->u
.s
.frac_width
> div
->u
.s
.width
) {
353 pr_warn("%s: bad %s fraction width for %s (%u > %u)\n",
354 __func__
, field_name
, clock_name
,
355 div
->u
.s
.frac_width
, div
->u
.s
.width
);
363 * If a clock has two dividers, the combined number of fractional
364 * bits must be representable in a 32-bit unsigned value. This
365 * is because we scale up a dividend using both dividers before
366 * dividing to improve accuracy, and we need to avoid overflow.
368 static bool kona_dividers_valid(struct kona_clk
*bcm_clk
)
370 struct peri_clk_data
*peri
= bcm_clk
->u
.peri
;
371 struct bcm_clk_div
*div
;
372 struct bcm_clk_div
*pre_div
;
375 BUG_ON(bcm_clk
->type
!= bcm_clk_peri
);
377 if (!divider_exists(&peri
->div
) || !divider_exists(&peri
->pre_div
))
381 pre_div
= &peri
->pre_div
;
382 if (divider_is_fixed(div
) || divider_is_fixed(pre_div
))
385 limit
= BITS_PER_BYTE
* sizeof(u32
);
387 return div
->u
.s
.frac_width
+ pre_div
->u
.s
.frac_width
<= limit
;
391 /* A trigger just needs to represent a valid bit position */
392 static bool trig_valid(struct bcm_clk_trig
*trig
, const char *field_name
,
393 const char *clock_name
)
395 return bit_posn_valid(trig
->bit
, field_name
, clock_name
);
398 /* Determine whether the set of peripheral clock registers are valid. */
400 peri_clk_data_valid(struct kona_clk
*bcm_clk
)
402 struct peri_clk_data
*peri
;
403 struct bcm_clk_policy
*policy
;
404 struct bcm_clk_gate
*gate
;
405 struct bcm_clk_hyst
*hyst
;
406 struct bcm_clk_sel
*sel
;
407 struct bcm_clk_div
*div
;
408 struct bcm_clk_div
*pre_div
;
409 struct bcm_clk_trig
*trig
;
412 BUG_ON(bcm_clk
->type
!= bcm_clk_peri
);
415 * First validate register offsets. This is the only place
416 * where we need something from the ccu, so we do these
419 if (!peri_clk_data_offsets_valid(bcm_clk
))
422 peri
= bcm_clk
->u
.peri
;
423 name
= bcm_clk
->init_data
.name
;
425 policy
= &peri
->policy
;
426 if (policy_exists(policy
) && !policy_valid(policy
, name
))
430 if (gate_exists(gate
) && !gate_valid(gate
, "gate", name
))
434 if (hyst_exists(hyst
) && !hyst_valid(hyst
, name
))
438 if (selector_exists(sel
)) {
439 if (!sel_valid(sel
, "selector", name
))
442 } else if (sel
->parent_count
> 1) {
443 pr_err("%s: multiple parents but no selector for %s\n",
450 pre_div
= &peri
->pre_div
;
451 if (divider_exists(div
)) {
452 if (!div_valid(div
, "divider", name
))
455 if (divider_exists(pre_div
))
456 if (!div_valid(pre_div
, "pre-divider", name
))
458 } else if (divider_exists(pre_div
)) {
459 pr_err("%s: pre-divider but no divider for %s\n", __func__
,
465 if (trigger_exists(trig
)) {
466 if (!trig_valid(trig
, "trigger", name
))
469 if (trigger_exists(&peri
->pre_trig
)) {
470 if (!trig_valid(trig
, "pre-trigger", name
)) {
474 if (!clk_requires_trigger(bcm_clk
)) {
475 pr_warn("%s: ignoring trigger for %s (not needed)\n",
477 trigger_clear_exists(trig
);
479 } else if (trigger_exists(&peri
->pre_trig
)) {
480 pr_err("%s: pre-trigger but no trigger for %s\n", __func__
,
483 } else if (clk_requires_trigger(bcm_clk
)) {
484 pr_err("%s: required trigger missing for %s\n", __func__
,
489 return kona_dividers_valid(bcm_clk
);
492 static bool kona_clk_valid(struct kona_clk
*bcm_clk
)
494 switch (bcm_clk
->type
) {
496 if (!peri_clk_data_valid(bcm_clk
))
500 pr_err("%s: unrecognized clock type (%d)\n", __func__
,
508 * Scan an array of parent clock names to determine whether there
509 * are any entries containing BAD_CLK_NAME. Such entries are
510 * placeholders for non-supported clocks. Keep track of the
511 * position of each clock name in the original array.
513 * Allocates an array of pointers to to hold the names of all
514 * non-null entries in the original array, and returns a pointer to
515 * that array in *names. This will be used for registering the
516 * clock with the common clock code. On successful return,
517 * *count indicates how many entries are in that names array.
519 * If there is more than one entry in the resulting names array,
520 * another array is allocated to record the parent selector value
521 * for each (defined) parent clock. This is the value that
522 * represents this parent clock in the clock's source selector
523 * register. The position of the clock in the original parent array
524 * defines that selector value. The number of entries in this array
525 * is the same as the number of entries in the parent names array.
527 * The array of selector values is returned. If the clock has no
528 * parents, no selector is required and a null pointer is returned.
530 * Returns a null pointer if the clock names array supplied was
531 * null. (This is not an error.)
533 * Returns a pointer-coded error if an error occurs.
535 static u32
*parent_process(const char *clocks
[],
536 u32
*count
, const char ***names
)
538 static const char **parent_names
;
539 static u32
*parent_sel
;
547 *count
= 0; /* In case of early return */
553 * Count the number of names in the null-terminated array,
554 * and find out how many of those are actually clock names.
556 for (clock
= clocks
; *clock
; clock
++)
557 if (*clock
== BAD_CLK_NAME
)
559 orig_count
= (u32
)(clock
- clocks
);
560 parent_count
= orig_count
- bad_count
;
562 /* If all clocks are unsupported, we treat it as no clock */
566 /* Avoid exceeding our parent clock limit */
567 if (parent_count
> PARENT_COUNT_MAX
) {
568 pr_err("%s: too many parents (%u > %u)\n", __func__
,
569 parent_count
, PARENT_COUNT_MAX
);
570 return ERR_PTR(-EINVAL
);
574 * There is one parent name for each defined parent clock.
575 * We also maintain an array containing the selector value
576 * for each defined clock. If there's only one clock, the
577 * selector is not required, but we allocate space for the
578 * array anyway to keep things simple.
580 parent_names
= kmalloc_array(parent_count
, sizeof(*parent_names
),
583 pr_err("%s: error allocating %u parent names\n", __func__
,
585 return ERR_PTR(-ENOMEM
);
588 /* There is at least one parent, so allocate a selector array */
589 parent_sel
= kmalloc_array(parent_count
, sizeof(*parent_sel
),
592 pr_err("%s: error allocating %u parent selectors\n", __func__
,
596 return ERR_PTR(-ENOMEM
);
599 /* Now fill in the parent names and selector arrays */
600 for (i
= 0, j
= 0; i
< orig_count
; i
++) {
601 if (clocks
[i
] != BAD_CLK_NAME
) {
602 parent_names
[j
] = clocks
[i
];
607 *names
= parent_names
;
608 *count
= parent_count
;
614 clk_sel_setup(const char **clocks
, struct bcm_clk_sel
*sel
,
615 struct clk_init_data
*init_data
)
617 const char **parent_names
= NULL
;
618 u32 parent_count
= 0;
622 * If a peripheral clock has multiple parents, the value
623 * used by the hardware to select that parent is represented
624 * by the parent clock's position in the "clocks" list. Some
625 * values don't have defined or supported clocks; these will
626 * have BAD_CLK_NAME entries in the parents[] array. The
627 * list is terminated by a NULL entry.
629 * We need to supply (only) the names of defined parent
630 * clocks when registering a clock though, so we use an
631 * array of parent selector values to map between the
632 * indexes the common clock code uses and the selector
635 parent_sel
= parent_process(clocks
, &parent_count
, &parent_names
);
636 if (IS_ERR(parent_sel
)) {
637 int ret
= PTR_ERR(parent_sel
);
639 pr_err("%s: error processing parent clocks for %s (%d)\n",
640 __func__
, init_data
->name
, ret
);
645 init_data
->parent_names
= parent_names
;
646 init_data
->num_parents
= parent_count
;
648 sel
->parent_count
= parent_count
;
649 sel
->parent_sel
= parent_sel
;
654 static void clk_sel_teardown(struct bcm_clk_sel
*sel
,
655 struct clk_init_data
*init_data
)
657 kfree(sel
->parent_sel
);
658 sel
->parent_sel
= NULL
;
659 sel
->parent_count
= 0;
661 init_data
->num_parents
= 0;
662 kfree(init_data
->parent_names
);
663 init_data
->parent_names
= NULL
;
666 static void peri_clk_teardown(struct peri_clk_data
*data
,
667 struct clk_init_data
*init_data
)
669 clk_sel_teardown(&data
->sel
, init_data
);
673 * Caller is responsible for freeing the parent_names[] and
674 * parent_sel[] arrays in the peripheral clock's "data" structure
675 * that can be assigned if the clock has one or more parent clocks
676 * associated with it.
679 peri_clk_setup(struct peri_clk_data
*data
, struct clk_init_data
*init_data
)
681 init_data
->flags
= CLK_IGNORE_UNUSED
;
683 return clk_sel_setup(data
->clocks
, &data
->sel
, init_data
);
686 static void bcm_clk_teardown(struct kona_clk
*bcm_clk
)
688 switch (bcm_clk
->type
) {
690 peri_clk_teardown(bcm_clk
->u
.data
, &bcm_clk
->init_data
);
695 bcm_clk
->u
.data
= NULL
;
696 bcm_clk
->type
= bcm_clk_none
;
699 static void kona_clk_teardown(struct clk_hw
*hw
)
701 struct kona_clk
*bcm_clk
;
706 clk_hw_unregister(hw
);
708 bcm_clk
= to_kona_clk(hw
);
709 bcm_clk_teardown(bcm_clk
);
712 static int kona_clk_setup(struct kona_clk
*bcm_clk
)
715 struct clk_init_data
*init_data
= &bcm_clk
->init_data
;
717 switch (bcm_clk
->type
) {
719 ret
= peri_clk_setup(bcm_clk
->u
.data
, init_data
);
724 pr_err("%s: clock type %d invalid for %s\n", __func__
,
725 (int)bcm_clk
->type
, init_data
->name
);
729 /* Make sure everything makes sense before we set it up */
730 if (!kona_clk_valid(bcm_clk
)) {
731 pr_err("%s: clock data invalid for %s\n", __func__
,
737 bcm_clk
->hw
.init
= init_data
;
738 ret
= clk_hw_register(NULL
, &bcm_clk
->hw
);
740 pr_err("%s: error registering clock %s (%d)\n", __func__
,
741 init_data
->name
, ret
);
747 bcm_clk_teardown(bcm_clk
);
752 static void ccu_clks_teardown(struct ccu_data
*ccu
)
756 for (i
= 0; i
< ccu
->clk_num
; i
++)
757 kona_clk_teardown(&ccu
->kona_clks
[i
].hw
);
760 static void kona_ccu_teardown(struct ccu_data
*ccu
)
765 of_clk_del_provider(ccu
->node
); /* safe if never added */
766 ccu_clks_teardown(ccu
);
767 of_node_put(ccu
->node
);
773 static bool ccu_data_valid(struct ccu_data
*ccu
)
775 struct ccu_policy
*ccu_policy
;
777 if (!ccu_data_offsets_valid(ccu
))
780 ccu_policy
= &ccu
->policy
;
781 if (ccu_policy_exists(ccu_policy
))
782 if (!ccu_policy_valid(ccu_policy
, ccu
->name
))
788 static struct clk_hw
*
789 of_clk_kona_onecell_get(struct of_phandle_args
*clkspec
, void *data
)
791 struct ccu_data
*ccu
= data
;
792 unsigned int idx
= clkspec
->args
[0];
794 if (idx
>= ccu
->clk_num
) {
795 pr_err("%s: invalid index %u\n", __func__
, idx
);
796 return ERR_PTR(-EINVAL
);
799 return &ccu
->kona_clks
[idx
].hw
;
803 * Set up a CCU. Call the provided ccu_clks_setup callback to
804 * initialize the array of clocks provided by the CCU.
806 void __init
kona_dt_ccu_setup(struct ccu_data
*ccu
,
807 struct device_node
*node
)
809 struct resource res
= { 0 };
810 resource_size_t range
;
814 ret
= of_address_to_resource(node
, 0, &res
);
816 pr_err("%s: no valid CCU registers found for %s\n", __func__
,
821 range
= resource_size(&res
);
822 if (range
> (resource_size_t
)U32_MAX
) {
823 pr_err("%s: address range too large for %s\n", __func__
,
828 ccu
->range
= (u32
)range
;
830 if (!ccu_data_valid(ccu
)) {
831 pr_err("%s: ccu data not valid for %s\n", __func__
, node
->name
);
835 ccu
->base
= ioremap(res
.start
, ccu
->range
);
837 pr_err("%s: unable to map CCU registers for %s\n", __func__
,
841 ccu
->node
= of_node_get(node
);
844 * Set up each defined kona clock and save the result in
845 * the clock framework clock array (in ccu->data). Then
846 * register as a provider for these clocks.
848 for (i
= 0; i
< ccu
->clk_num
; i
++) {
849 if (!ccu
->kona_clks
[i
].ccu
)
851 kona_clk_setup(&ccu
->kona_clks
[i
]);
854 ret
= of_clk_add_hw_provider(node
, of_clk_kona_onecell_get
, ccu
);
856 pr_err("%s: error adding ccu %s as provider (%d)\n", __func__
,
861 if (!kona_ccu_init(ccu
))
862 pr_err("Broadcom %s initialization had errors\n", node
->name
);
866 kona_ccu_teardown(ccu
);
867 pr_err("Broadcom %s setup aborted\n", node
->name
);