x86/mm: Add TLB purge to free pmd/pte page interfaces
[linux/fpc-iii.git] / drivers / spi / spi-st-ssc4.c
blobe54b59638458232bf576b4e71b3f0e3450b384df
1 /*
2 * Copyright (c) 2008-2014 STMicroelectronics Limited
4 * Author: Angus Clark <Angus.Clark@st.com>
5 * Patrice Chotard <patrice.chotard@st.com>
6 * Lee Jones <lee.jones@linaro.org>
8 * SPI master mode controller driver, used in STMicroelectronics devices.
10 * May be copied or modified under the terms of the GNU General Public
11 * License Version 2.0 only. See linux/COPYING for more information.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/platform_device.h>
21 #include <linux/of.h>
22 #include <linux/of_gpio.h>
23 #include <linux/of_irq.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/spi_bitbang.h>
28 /* SSC registers */
29 #define SSC_BRG 0x000
30 #define SSC_TBUF 0x004
31 #define SSC_RBUF 0x008
32 #define SSC_CTL 0x00C
33 #define SSC_IEN 0x010
34 #define SSC_I2C 0x018
36 /* SSC Control */
37 #define SSC_CTL_DATA_WIDTH_9 0x8
38 #define SSC_CTL_DATA_WIDTH_MSK 0xf
39 #define SSC_CTL_BM 0xf
40 #define SSC_CTL_HB BIT(4)
41 #define SSC_CTL_PH BIT(5)
42 #define SSC_CTL_PO BIT(6)
43 #define SSC_CTL_SR BIT(7)
44 #define SSC_CTL_MS BIT(8)
45 #define SSC_CTL_EN BIT(9)
46 #define SSC_CTL_LPB BIT(10)
47 #define SSC_CTL_EN_TX_FIFO BIT(11)
48 #define SSC_CTL_EN_RX_FIFO BIT(12)
49 #define SSC_CTL_EN_CLST_RX BIT(13)
51 /* SSC Interrupt Enable */
52 #define SSC_IEN_TEEN BIT(2)
54 #define FIFO_SIZE 8
56 struct spi_st {
57 /* SSC SPI Controller */
58 void __iomem *base;
59 struct clk *clk;
60 struct device *dev;
62 /* SSC SPI current transaction */
63 const u8 *tx_ptr;
64 u8 *rx_ptr;
65 u16 bytes_per_word;
66 unsigned int words_remaining;
67 unsigned int baud;
68 struct completion done;
71 /* Load the TX FIFO */
72 static void ssc_write_tx_fifo(struct spi_st *spi_st)
74 unsigned int count, i;
75 uint32_t word = 0;
77 if (spi_st->words_remaining > FIFO_SIZE)
78 count = FIFO_SIZE;
79 else
80 count = spi_st->words_remaining;
82 for (i = 0; i < count; i++) {
83 if (spi_st->tx_ptr) {
84 if (spi_st->bytes_per_word == 1) {
85 word = *spi_st->tx_ptr++;
86 } else {
87 word = *spi_st->tx_ptr++;
88 word = *spi_st->tx_ptr++ | (word << 8);
91 writel_relaxed(word, spi_st->base + SSC_TBUF);
95 /* Read the RX FIFO */
96 static void ssc_read_rx_fifo(struct spi_st *spi_st)
98 unsigned int count, i;
99 uint32_t word = 0;
101 if (spi_st->words_remaining > FIFO_SIZE)
102 count = FIFO_SIZE;
103 else
104 count = spi_st->words_remaining;
106 for (i = 0; i < count; i++) {
107 word = readl_relaxed(spi_st->base + SSC_RBUF);
109 if (spi_st->rx_ptr) {
110 if (spi_st->bytes_per_word == 1) {
111 *spi_st->rx_ptr++ = (uint8_t)word;
112 } else {
113 *spi_st->rx_ptr++ = (word >> 8);
114 *spi_st->rx_ptr++ = word & 0xff;
118 spi_st->words_remaining -= count;
121 static int spi_st_transfer_one(struct spi_master *master,
122 struct spi_device *spi, struct spi_transfer *t)
124 struct spi_st *spi_st = spi_master_get_devdata(master);
125 uint32_t ctl = 0;
127 /* Setup transfer */
128 spi_st->tx_ptr = t->tx_buf;
129 spi_st->rx_ptr = t->rx_buf;
131 if (spi->bits_per_word > 8) {
133 * Anything greater than 8 bits-per-word requires 2
134 * bytes-per-word in the RX/TX buffers
136 spi_st->bytes_per_word = 2;
137 spi_st->words_remaining = t->len / 2;
139 } else if (spi->bits_per_word == 8 && !(t->len & 0x1)) {
141 * If transfer is even-length, and 8 bits-per-word, then
142 * implement as half-length 16 bits-per-word transfer
144 spi_st->bytes_per_word = 2;
145 spi_st->words_remaining = t->len / 2;
147 /* Set SSC_CTL to 16 bits-per-word */
148 ctl = readl_relaxed(spi_st->base + SSC_CTL);
149 writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL);
151 readl_relaxed(spi_st->base + SSC_RBUF);
153 } else {
154 spi_st->bytes_per_word = 1;
155 spi_st->words_remaining = t->len;
158 reinit_completion(&spi_st->done);
160 /* Start transfer by writing to the TX FIFO */
161 ssc_write_tx_fifo(spi_st);
162 writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN);
164 /* Wait for transfer to complete */
165 wait_for_completion(&spi_st->done);
167 /* Restore SSC_CTL if necessary */
168 if (ctl)
169 writel_relaxed(ctl, spi_st->base + SSC_CTL);
171 spi_finalize_current_transfer(spi->master);
173 return t->len;
176 static void spi_st_cleanup(struct spi_device *spi)
178 gpio_free(spi->cs_gpio);
181 /* the spi->mode bits understood by this driver: */
182 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH)
183 static int spi_st_setup(struct spi_device *spi)
185 struct spi_st *spi_st = spi_master_get_devdata(spi->master);
186 u32 spi_st_clk, sscbrg, var;
187 u32 hz = spi->max_speed_hz;
188 int cs = spi->cs_gpio;
189 int ret;
191 if (!hz) {
192 dev_err(&spi->dev, "max_speed_hz unspecified\n");
193 return -EINVAL;
196 if (!gpio_is_valid(cs)) {
197 dev_err(&spi->dev, "%d is not a valid gpio\n", cs);
198 return -EINVAL;
201 ret = gpio_request(cs, dev_name(&spi->dev));
202 if (ret) {
203 dev_err(&spi->dev, "could not request gpio:%d\n", cs);
204 return ret;
207 ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH);
208 if (ret)
209 goto out_free_gpio;
211 spi_st_clk = clk_get_rate(spi_st->clk);
213 /* Set SSC_BRF */
214 sscbrg = spi_st_clk / (2 * hz);
215 if (sscbrg < 0x07 || sscbrg > BIT(16)) {
216 dev_err(&spi->dev,
217 "baudrate %d outside valid range %d\n", sscbrg, hz);
218 ret = -EINVAL;
219 goto out_free_gpio;
222 spi_st->baud = spi_st_clk / (2 * sscbrg);
223 if (sscbrg == BIT(16)) /* 16-bit counter wraps */
224 sscbrg = 0x0;
226 writel_relaxed(sscbrg, spi_st->base + SSC_BRG);
228 dev_dbg(&spi->dev,
229 "setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
230 hz, spi_st->baud, sscbrg);
232 /* Set SSC_CTL and enable SSC */
233 var = readl_relaxed(spi_st->base + SSC_CTL);
234 var |= SSC_CTL_MS;
236 if (spi->mode & SPI_CPOL)
237 var |= SSC_CTL_PO;
238 else
239 var &= ~SSC_CTL_PO;
241 if (spi->mode & SPI_CPHA)
242 var |= SSC_CTL_PH;
243 else
244 var &= ~SSC_CTL_PH;
246 if ((spi->mode & SPI_LSB_FIRST) == 0)
247 var |= SSC_CTL_HB;
248 else
249 var &= ~SSC_CTL_HB;
251 if (spi->mode & SPI_LOOP)
252 var |= SSC_CTL_LPB;
253 else
254 var &= ~SSC_CTL_LPB;
256 var &= ~SSC_CTL_DATA_WIDTH_MSK;
257 var |= (spi->bits_per_word - 1);
259 var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
260 var |= SSC_CTL_EN;
262 writel_relaxed(var, spi_st->base + SSC_CTL);
264 /* Clear the status register */
265 readl_relaxed(spi_st->base + SSC_RBUF);
267 return 0;
269 out_free_gpio:
270 gpio_free(cs);
271 return ret;
274 /* Interrupt fired when TX shift register becomes empty */
275 static irqreturn_t spi_st_irq(int irq, void *dev_id)
277 struct spi_st *spi_st = (struct spi_st *)dev_id;
279 /* Read RX FIFO */
280 ssc_read_rx_fifo(spi_st);
282 /* Fill TX FIFO */
283 if (spi_st->words_remaining) {
284 ssc_write_tx_fifo(spi_st);
285 } else {
286 /* TX/RX complete */
287 writel_relaxed(0x0, spi_st->base + SSC_IEN);
289 * read SSC_IEN to ensure that this bit is set
290 * before re-enabling interrupt
292 readl(spi_st->base + SSC_IEN);
293 complete(&spi_st->done);
296 return IRQ_HANDLED;
299 static int spi_st_probe(struct platform_device *pdev)
301 struct device_node *np = pdev->dev.of_node;
302 struct spi_master *master;
303 struct resource *res;
304 struct spi_st *spi_st;
305 int irq, ret = 0;
306 u32 var;
308 master = spi_alloc_master(&pdev->dev, sizeof(*spi_st));
309 if (!master)
310 return -ENOMEM;
312 master->dev.of_node = np;
313 master->mode_bits = MODEBITS;
314 master->setup = spi_st_setup;
315 master->cleanup = spi_st_cleanup;
316 master->transfer_one = spi_st_transfer_one;
317 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
318 master->auto_runtime_pm = true;
319 master->bus_num = pdev->id;
320 spi_st = spi_master_get_devdata(master);
322 spi_st->clk = devm_clk_get(&pdev->dev, "ssc");
323 if (IS_ERR(spi_st->clk)) {
324 dev_err(&pdev->dev, "Unable to request clock\n");
325 ret = PTR_ERR(spi_st->clk);
326 goto put_master;
329 ret = clk_prepare_enable(spi_st->clk);
330 if (ret)
331 goto put_master;
333 init_completion(&spi_st->done);
335 /* Get resources */
336 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
337 spi_st->base = devm_ioremap_resource(&pdev->dev, res);
338 if (IS_ERR(spi_st->base)) {
339 ret = PTR_ERR(spi_st->base);
340 goto clk_disable;
343 /* Disable I2C and Reset SSC */
344 writel_relaxed(0x0, spi_st->base + SSC_I2C);
345 var = readw_relaxed(spi_st->base + SSC_CTL);
346 var |= SSC_CTL_SR;
347 writel_relaxed(var, spi_st->base + SSC_CTL);
349 udelay(1);
350 var = readl_relaxed(spi_st->base + SSC_CTL);
351 var &= ~SSC_CTL_SR;
352 writel_relaxed(var, spi_st->base + SSC_CTL);
354 /* Set SSC into slave mode before reconfiguring PIO pins */
355 var = readl_relaxed(spi_st->base + SSC_CTL);
356 var &= ~SSC_CTL_MS;
357 writel_relaxed(var, spi_st->base + SSC_CTL);
359 irq = irq_of_parse_and_map(np, 0);
360 if (!irq) {
361 dev_err(&pdev->dev, "IRQ missing or invalid\n");
362 ret = -EINVAL;
363 goto clk_disable;
366 ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0,
367 pdev->name, spi_st);
368 if (ret) {
369 dev_err(&pdev->dev, "Failed to request irq %d\n", irq);
370 goto clk_disable;
373 /* by default the device is on */
374 pm_runtime_set_active(&pdev->dev);
375 pm_runtime_enable(&pdev->dev);
377 platform_set_drvdata(pdev, master);
379 ret = devm_spi_register_master(&pdev->dev, master);
380 if (ret) {
381 dev_err(&pdev->dev, "Failed to register master\n");
382 goto clk_disable;
385 return 0;
387 clk_disable:
388 clk_disable_unprepare(spi_st->clk);
389 put_master:
390 spi_master_put(master);
391 return ret;
394 static int spi_st_remove(struct platform_device *pdev)
396 struct spi_master *master = platform_get_drvdata(pdev);
397 struct spi_st *spi_st = spi_master_get_devdata(master);
399 clk_disable_unprepare(spi_st->clk);
401 pinctrl_pm_select_sleep_state(&pdev->dev);
403 return 0;
406 #ifdef CONFIG_PM
407 static int spi_st_runtime_suspend(struct device *dev)
409 struct spi_master *master = dev_get_drvdata(dev);
410 struct spi_st *spi_st = spi_master_get_devdata(master);
412 writel_relaxed(0, spi_st->base + SSC_IEN);
413 pinctrl_pm_select_sleep_state(dev);
415 clk_disable_unprepare(spi_st->clk);
417 return 0;
420 static int spi_st_runtime_resume(struct device *dev)
422 struct spi_master *master = dev_get_drvdata(dev);
423 struct spi_st *spi_st = spi_master_get_devdata(master);
424 int ret;
426 ret = clk_prepare_enable(spi_st->clk);
427 pinctrl_pm_select_default_state(dev);
429 return ret;
431 #endif
433 #ifdef CONFIG_PM_SLEEP
434 static int spi_st_suspend(struct device *dev)
436 struct spi_master *master = dev_get_drvdata(dev);
437 int ret;
439 ret = spi_master_suspend(master);
440 if (ret)
441 return ret;
443 return pm_runtime_force_suspend(dev);
446 static int spi_st_resume(struct device *dev)
448 struct spi_master *master = dev_get_drvdata(dev);
449 int ret;
451 ret = spi_master_resume(master);
452 if (ret)
453 return ret;
455 return pm_runtime_force_resume(dev);
457 #endif
459 static const struct dev_pm_ops spi_st_pm = {
460 SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume)
461 SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL)
464 static const struct of_device_id stm_spi_match[] = {
465 { .compatible = "st,comms-ssc4-spi", },
468 MODULE_DEVICE_TABLE(of, stm_spi_match);
470 static struct platform_driver spi_st_driver = {
471 .driver = {
472 .name = "spi-st",
473 .pm = &spi_st_pm,
474 .of_match_table = of_match_ptr(stm_spi_match),
476 .probe = spi_st_probe,
477 .remove = spi_st_remove,
479 module_platform_driver(spi_st_driver);
481 MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
482 MODULE_DESCRIPTION("STM SSC SPI driver");
483 MODULE_LICENSE("GPL v2");