drivers/pinctrl/freescale/pinctrl-imx1-core.c

   1 /*
   2  * Core driver for the imx pin controller in imx1/21/27
   3  *
   4  * Copyright (C) 2013 Pengutronix
   5  * Author: Markus Pargmann <mpa@pengutronix.de>
   6  *
   7  * Based on pinctrl-imx.c:
   8  *      Author: Dong Aisheng <dong.aisheng@linaro.org>
   9  *      Copyright (C) 2012 Freescale Semiconductor, Inc.
  10  *      Copyright (C) 2012 Linaro Ltd.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  */
  17
  18 #include <linux/bitops.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/pinctrl/machine.h>
  25 #include <linux/pinctrl/pinconf.h>
  26 #include <linux/pinctrl/pinctrl.h>
  27 #include <linux/pinctrl/pinmux.h>
  28 #include <linux/slab.h>
  29
  30 #include "../core.h"
  31 #include "pinctrl-imx1.h"
  32
  33 struct imx1_pinctrl {
  34         struct device *dev;
  35         struct pinctrl_dev *pctl;
  36         void __iomem *base;
  37         const struct imx1_pinctrl_soc_info *info;
  38 };
  39
  40 /*
  41  * MX1 register offsets
  42  */
  43
  44 #define MX1_DDIR 0x00
  45 #define MX1_OCR 0x04
  46 #define MX1_ICONFA 0x0c
  47 #define MX1_ICONFB 0x14
  48 #define MX1_GIUS 0x20
  49 #define MX1_GPR 0x38
  50 #define MX1_PUEN 0x40
  51
  52 #define MX1_PORT_STRIDE 0x100
  53
  54
  55 /*
  56  * MUX_ID format defines
  57  */
  58 #define MX1_MUX_FUNCTION(val) (BIT(0) & val)
  59 #define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
  60 #define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
  61 #define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
  62 #define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
  63 #define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
  64
  65
  66 /*
  67  * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
  68  * control register are seperated into function, output configuration, input
  69  * configuration A, input configuration B, GPIO in use and data direction.
  70  *
  71  * Those controls that are represented by 1 bit have a direct mapping between
  72  * bit position and pin id. If they are represented by 2 bit, the lower 16 pins
  73  * are in the first register and the upper 16 pins in the second (next)
  74  * register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
  75  */
  76
  77 /*
  78  * Calculates the register offset from a pin_id
  79  */
  80 static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
  81 {
  82         unsigned int port = pin_id / 32;
  83         return ipctl->base + port * MX1_PORT_STRIDE;
  84 }
  85
  86 /*
  87  * Write to a register with 2 bits per pin. The function will automatically
  88  * use the next register if the pin is managed in the second register.
  89  */
  90 static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
  91                 u32 value, u32 reg_offset)
  92 {
  93         void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
  94         int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
  95         int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
  96         u32 old_val;
  97         u32 new_val;
  98
  99         /* Use the next register if the pin's port pin number is >=16 */
 100         if (pin_id % 32 >= 16)
 101                 reg += 0x04;
 102
 103         dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
 104                         reg, offset, value);
 105
 106         /* Get current state of pins */
 107         old_val = readl(reg);
 108         old_val &= mask;
 109
 110         new_val = value & 0x3; /* Make sure value is really 2 bit */
 111         new_val <<= offset;
 112         new_val |= old_val;/* Set new state for pin_id */
 113
 114         writel(new_val, reg);
 115 }
 116
 117 static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
 118                 u32 value, u32 reg_offset)
 119 {
 120         void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
 121         int offset = pin_id % 32;
 122         int mask = ~BIT_MASK(offset);
 123         u32 old_val;
 124         u32 new_val;
 125
 126         /* Get current state of pins */
 127         old_val = readl(reg);
 128         old_val &= mask;
 129
 130         new_val = value & 0x1; /* Make sure value is really 1 bit */
 131         new_val <<= offset;
 132         new_val |= old_val;/* Set new state for pin_id */
 133
 134         writel(new_val, reg);
 135 }
 136
 137 static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
 138                 u32 reg_offset)
 139 {
 140         void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
 141         int offset = (pin_id % 16) * 2;
 142
 143         /* Use the next register if the pin's port pin number is >=16 */
 144         if (pin_id % 32 >= 16)
 145                 reg += 0x04;
 146
 147         return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
 148 }
 149
 150 static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
 151                 u32 reg_offset)
 152 {
 153         void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
 154         int offset = pin_id % 32;
 155
 156         return !!(readl(reg) & BIT(offset));
 157 }
 158
 159 static inline const struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
 160                                 const struct imx1_pinctrl_soc_info *info,
 161                                 const char *name)
 162 {
 163         const struct imx1_pin_group *grp = NULL;
 164         int i;
 165
 166         for (i = 0; i < info->ngroups; i++) {
 167                 if (!strcmp(info->groups[i].name, name)) {
 168                         grp = &info->groups[i];
 169                         break;
 170                 }
 171         }
 172
 173         return grp;
 174 }
 175
 176 static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
 177 {
 178         struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 179         const struct imx1_pinctrl_soc_info *info = ipctl->info;
 180
 181         return info->ngroups;
 182 }
 183
 184 static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
 185                                        unsigned selector)
 186 {
 187         struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 188         const struct imx1_pinctrl_soc_info *info = ipctl->info;
 189
 190         return info->groups[selector].name;
 191 }
 192
 193 static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 194                                const unsigned int **pins,
 195                                unsigned *npins)
 196 {
 197         struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 198         const struct imx1_pinctrl_soc_info *info = ipctl->info;
 199
 200         if (selector >= info->ngroups)
 201                 return -EINVAL;
 202
 203         *pins = info->groups[selector].pin_ids;
 204         *npins = info->groups[selector].npins;
 205
 206         return 0;
 207 }
 208
 209 static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 210                    unsigned offset)
 211 {
 212         struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 213
 214         seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
 215                         imx1_read_bit(ipctl, offset, MX1_GIUS),
 216                         imx1_read_bit(ipctl, offset, MX1_GPR),
 217                         imx1_read_bit(ipctl, offset, MX1_DDIR),
 218                         imx1_read_2bit(ipctl, offset, MX1_OCR),
 219                         imx1_read_2bit(ipctl, offset, MX1_ICONFA),
 220                         imx1_read_2bit(ipctl, offset, MX1_ICONFB));
 221 }
 222
 223 static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
 224                         struct device_node *np,
 225                         struct pinctrl_map **map, unsigned *num_maps)
 226 {
 227         struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 228         const struct imx1_pinctrl_soc_info *info = ipctl->info;
 229         const struct imx1_pin_group *grp;
 230         struct pinctrl_map *new_map;
 231         struct device_node *parent;
 232         int map_num = 1;
 233         int i, j;
 234
 235         /*
 236          * first find the group of this node and check if we need create
 237          * config maps for pins
 238          */
 239         grp = imx1_pinctrl_find_group_by_name(info, np->name);
 240         if (!grp) {
 241                 dev_err(info->dev, "unable to find group for node %s\n",
 242                         np->name);
 243                 return -EINVAL;
 244         }
 245
 246         for (i = 0; i < grp->npins; i++)
 247                 map_num++;
 248
 249         new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
 250         if (!new_map)
 251                 return -ENOMEM;
 252
 253         *map = new_map;
 254         *num_maps = map_num;
 255
 256         /* create mux map */
 257         parent = of_get_parent(np);
 258         if (!parent) {
 259                 kfree(new_map);
 260                 return -EINVAL;
 261         }
 262         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 263         new_map[0].data.mux.function = parent->name;
 264         new_map[0].data.mux.group = np->name;
 265         of_node_put(parent);
 266
 267         /* create config map */
 268         new_map++;
 269         for (i = j = 0; i < grp->npins; i++) {
 270                 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
 271                 new_map[j].data.configs.group_or_pin =
 272                                 pin_get_name(pctldev, grp->pins[i].pin_id);
 273                 new_map[j].data.configs.configs = &grp->pins[i].config;
 274                 new_map[j].data.configs.num_configs = 1;
 275                 j++;
 276         }
 277
 278         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 279                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 280
 281         return 0;
 282 }
 283
 284 static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
 285                                 struct pinctrl_map *map, unsigned num_maps)
 286 {
 287         kfree(map);
 288 }
 289
 290 static const struct pinctrl_ops imx1_pctrl_ops = {
 291         .get_groups_count = imx1_get_groups_count,
 292         .get_group_name = imx1_get_group_name,
 293         .get_group_pins = imx1_get_group_pins,
 294         .pin_dbg_show = imx1_pin_dbg_show,
 295         .dt_node_to_map = imx1_dt_node_to_map,
 296         .dt_free_map = imx1_dt_free_map,
 297
 298 };
 299
 300 static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 301                         unsigned group)
 302 {
 303         struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 304         const struct imx1_pinctrl_soc_info *info = ipctl->info;
 305         const struct imx1_pin *pins;
 306         unsigned int npins;
 307         int i;
 308
 309         /*
 310          * Configure the mux mode for each pin in the group for a specific
 311          * function.
 312          */
 313         pins = info->groups[group].pins;
 314         npins = info->groups[group].npins;
 315
 316         WARN_ON(!pins || !npins);
 317
 318         dev_dbg(ipctl->dev, "enable function %s group %s\n",
 319                 info->functions[selector].name, info->groups[group].name);
 320
 321         for (i = 0; i < npins; i++) {
 322                 unsigned int mux = pins[i].mux_id;
 323                 unsigned int pin_id = pins[i].pin_id;
 324                 unsigned int afunction = MX1_MUX_FUNCTION(mux);
 325                 unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
 326                 unsigned int direction = MX1_MUX_DIR(mux);
 327                 unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
 328                 unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
 329                 unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
 330
 331                 dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
 332                                 __func__, pin_id, afunction, gpio_in_use,
 333                                 direction, gpio_oconf, gpio_iconfa,
 334                                 gpio_iconfb);
 335
 336                 imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
 337                 imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
 338
 339                 if (gpio_in_use) {
 340                         imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
 341                         imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
 342                                         MX1_ICONFA);
 343                         imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
 344                                         MX1_ICONFB);
 345                 } else {
 346                         imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
 347                 }
 348         }
 349
 350         return 0;
 351 }
 352
 353 static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 354 {
 355         struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 356         const struct imx1_pinctrl_soc_info *info = ipctl->info;
 357
 358         return info->nfunctions;
 359 }
 360
 361 static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
 362                                           unsigned selector)
 363 {
 364         struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 365         const struct imx1_pinctrl_soc_info *info = ipctl->info;
 366
 367         return info->functions[selector].name;
 368 }
 369
 370 static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 371                                const char * const **groups,
 372                                unsigned * const num_groups)
 373 {
 374         struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 375         const struct imx1_pinctrl_soc_info *info = ipctl->info;
 376
 377         *groups = info->functions[selector].groups;
 378         *num_groups = info->functions[selector].num_groups;
 379
 380         return 0;
 381 }
 382
 383 static const struct pinmux_ops imx1_pmx_ops = {
 384         .get_functions_count = imx1_pmx_get_funcs_count,
 385         .get_function_name = imx1_pmx_get_func_name,
 386         .get_function_groups = imx1_pmx_get_groups,
 387         .set_mux = imx1_pmx_set,
 388 };
 389
 390 static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
 391                              unsigned pin_id, unsigned long *config)
 392 {
 393         struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 394
 395         *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
 396
 397         return 0;
 398 }
 399
 400 static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
 401                              unsigned pin_id, unsigned long *configs,
 402                              unsigned num_configs)
 403 {
 404         struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 405         int i;
 406
 407         for (i = 0; i != num_configs; ++i) {
 408                 imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
 409
 410                 dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
 411                         pin_desc_get(pctldev, pin_id)->name);
 412         }
 413
 414         return 0;
 415 }
 416
 417 static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 418                                    struct seq_file *s, unsigned pin_id)
 419 {
 420         unsigned long config;
 421
 422         imx1_pinconf_get(pctldev, pin_id, &config);
 423         seq_printf(s, "0x%lx", config);
 424 }
 425
 426 static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 427                                          struct seq_file *s, unsigned group)
 428 {
 429         struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 430         const struct imx1_pinctrl_soc_info *info = ipctl->info;
 431         struct imx1_pin_group *grp;
 432         unsigned long config;
 433         const char *name;
 434         int i, ret;
 435
 436         if (group > info->ngroups)
 437                 return;
 438
 439         seq_puts(s, "\n");
 440         grp = &info->groups[group];
 441         for (i = 0; i < grp->npins; i++) {
 442                 name = pin_get_name(pctldev, grp->pins[i].pin_id);
 443                 ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
 444                 if (ret)
 445                         return;
 446                 seq_printf(s, "%s: 0x%lx", name, config);
 447         }
 448 }
 449
 450 static const struct pinconf_ops imx1_pinconf_ops = {
 451         .pin_config_get = imx1_pinconf_get,
 452         .pin_config_set = imx1_pinconf_set,
 453         .pin_config_dbg_show = imx1_pinconf_dbg_show,
 454         .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
 455 };
 456
 457 static struct pinctrl_desc imx1_pinctrl_desc = {
 458         .pctlops = &imx1_pctrl_ops,
 459         .pmxops = &imx1_pmx_ops,
 460         .confops = &imx1_pinconf_ops,
 461         .owner = THIS_MODULE,
 462 };
 463
 464 static int imx1_pinctrl_parse_groups(struct device_node *np,
 465                                     struct imx1_pin_group *grp,
 466                                     struct imx1_pinctrl_soc_info *info,
 467                                     u32 index)
 468 {
 469         int size;
 470         const __be32 *list;
 471         int i;
 472
 473         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 474
 475         /* Initialise group */
 476         grp->name = np->name;
 477
 478         /*
 479          * the binding format is fsl,pins = <PIN MUX_ID CONFIG>
 480          */
 481         list = of_get_property(np, "fsl,pins", &size);
 482         /* we do not check return since it's safe node passed down */
 483         if (!size || size % 12) {
 484                 dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n",
 485                                 np->name);
 486                 return -EINVAL;
 487         }
 488
 489         grp->npins = size / 12;
 490         grp->pins = devm_kzalloc(info->dev,
 491                         grp->npins * sizeof(struct imx1_pin), GFP_KERNEL);
 492         grp->pin_ids = devm_kzalloc(info->dev,
 493                         grp->npins * sizeof(unsigned int), GFP_KERNEL);
 494
 495         if (!grp->pins || !grp->pin_ids)
 496                 return -ENOMEM;
 497
 498         for (i = 0; i < grp->npins; i++) {
 499                 grp->pins[i].pin_id = be32_to_cpu(*list++);
 500                 grp->pins[i].mux_id = be32_to_cpu(*list++);
 501                 grp->pins[i].config = be32_to_cpu(*list++);
 502
 503                 grp->pin_ids[i] = grp->pins[i].pin_id;
 504         }
 505
 506         return 0;
 507 }
 508
 509 static int imx1_pinctrl_parse_functions(struct device_node *np,
 510                                        struct imx1_pinctrl_soc_info *info,
 511                                        u32 index)
 512 {
 513         struct device_node *child;
 514         struct imx1_pmx_func *func;
 515         struct imx1_pin_group *grp;
 516         int ret;
 517         static u32 grp_index;
 518         u32 i = 0;
 519
 520         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 521
 522         func = &info->functions[index];
 523
 524         /* Initialise function */
 525         func->name = np->name;
 526         func->num_groups = of_get_child_count(np);
 527         if (func->num_groups == 0)
 528                 return -EINVAL;
 529
 530         func->groups = devm_kzalloc(info->dev,
 531                         func->num_groups * sizeof(char *), GFP_KERNEL);
 532
 533         if (!func->groups)
 534                 return -ENOMEM;
 535
 536         for_each_child_of_node(np, child) {
 537                 func->groups[i] = child->name;
 538                 grp = &info->groups[grp_index++];
 539                 ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
 540                 if (ret == -ENOMEM) {
 541                         of_node_put(child);
 542                         return ret;
 543                 }
 544         }
 545
 546         return 0;
 547 }
 548
 549 static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
 550                 struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
 551 {
 552         struct device_node *np = pdev->dev.of_node;
 553         struct device_node *child;
 554         int ret;
 555         u32 nfuncs = 0;
 556         u32 ngroups = 0;
 557         u32 ifunc = 0;
 558
 559         if (!np)
 560                 return -ENODEV;
 561
 562         for_each_child_of_node(np, child) {
 563                 ++nfuncs;
 564                 ngroups += of_get_child_count(child);
 565         }
 566
 567         if (!nfuncs) {
 568                 dev_err(&pdev->dev, "No pin functions defined\n");
 569                 return -EINVAL;
 570         }
 571
 572         info->nfunctions = nfuncs;
 573         info->functions = devm_kzalloc(&pdev->dev,
 574                         nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL);
 575
 576         info->ngroups = ngroups;
 577         info->groups = devm_kzalloc(&pdev->dev,
 578                         ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL);
 579
 580
 581         if (!info->functions || !info->groups)
 582                 return -ENOMEM;
 583
 584         for_each_child_of_node(np, child) {
 585                 ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
 586                 if (ret == -ENOMEM) {
 587                         of_node_put(child);
 588                         return -ENOMEM;
 589                 }
 590         }
 591
 592         return 0;
 593 }
 594
 595 int imx1_pinctrl_core_probe(struct platform_device *pdev,
 596                       struct imx1_pinctrl_soc_info *info)
 597 {
 598         struct imx1_pinctrl *ipctl;
 599         struct resource *res;
 600         struct pinctrl_desc *pctl_desc;
 601         int ret;
 602
 603         if (!info || !info->pins || !info->npins) {
 604                 dev_err(&pdev->dev, "wrong pinctrl info\n");
 605                 return -EINVAL;
 606         }
 607         info->dev = &pdev->dev;
 608
 609         /* Create state holders etc for this driver */
 610         ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
 611         if (!ipctl)
 612                 return -ENOMEM;
 613
 614         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 615         if (!res)
 616                 return -ENOENT;
 617
 618         ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start,
 619                         resource_size(res));
 620         if (!ipctl->base)
 621                 return -ENOMEM;
 622
 623         pctl_desc = &imx1_pinctrl_desc;
 624         pctl_desc->name = dev_name(&pdev->dev);
 625         pctl_desc->pins = info->pins;
 626         pctl_desc->npins = info->npins;
 627
 628         ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
 629         if (ret) {
 630                 dev_err(&pdev->dev, "fail to probe dt properties\n");
 631                 return ret;
 632         }
 633
 634         ipctl->info = info;
 635         ipctl->dev = info->dev;
 636         platform_set_drvdata(pdev, ipctl);
 637         ipctl->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, ipctl);
 638         if (IS_ERR(ipctl->pctl)) {
 639                 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
 640                 return PTR_ERR(ipctl->pctl);
 641         }
 642
 643         ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
 644         if (ret) {
 645                 pinctrl_unregister(ipctl->pctl);
 646                 dev_err(&pdev->dev, "Failed to populate subdevices\n");
 647                 return ret;
 648         }
 649
 650         dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
 651
 652         return 0;
 653 }