arch/blackfin/mach-bf561/include/mach/irq.h

   1 /*
   2  * Copyright 2005-2008 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #ifndef _BF561_IRQ_H_
   8 #define _BF561_IRQ_H_
   9
  10 #include <mach-common/irq.h>
  11
  12 #define NR_PERI_INTS            (2 * 32)
  13
  14 #define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
  15 #define IRQ_DMA1_ERROR          BFIN_IRQ(1)     /* DMA1   Error (general) */
  16 #define IRQ_DMA_ERROR           IRQ_DMA1_ERROR  /* DMA1   Error (general) */
  17 #define IRQ_DMA2_ERROR          BFIN_IRQ(2)     /* DMA2   Error (general) */
  18 #define IRQ_IMDMA_ERROR         BFIN_IRQ(3)     /* IMDMA  Error Interrupt */
  19 #define IRQ_PPI1_ERROR          BFIN_IRQ(4)     /* PPI1   Error Interrupt */
  20 #define IRQ_PPI_ERROR           IRQ_PPI1_ERROR  /* PPI1   Error Interrupt */
  21 #define IRQ_PPI2_ERROR          BFIN_IRQ(5)     /* PPI2   Error Interrupt */
  22 #define IRQ_SPORT0_ERROR        BFIN_IRQ(6)     /* SPORT0 Error Interrupt */
  23 #define IRQ_SPORT1_ERROR        BFIN_IRQ(7)     /* SPORT1 Error Interrupt */
  24 #define IRQ_SPI_ERROR           BFIN_IRQ(8)     /* SPI    Error Interrupt */
  25 #define IRQ_UART_ERROR          BFIN_IRQ(9)     /* UART   Error Interrupt */
  26 #define IRQ_RESERVED_ERROR      BFIN_IRQ(10)    /* Reversed */
  27 #define IRQ_DMA1_0              BFIN_IRQ(11)    /* DMA1 0  Interrupt(PPI1) */
  28 #define IRQ_PPI                 IRQ_DMA1_0      /* DMA1 0  Interrupt(PPI1) */
  29 #define IRQ_PPI0                IRQ_DMA1_0      /* DMA1 0  Interrupt(PPI1) */
  30 #define IRQ_DMA1_1              BFIN_IRQ(12)    /* DMA1 1  Interrupt(PPI2) */
  31 #define IRQ_PPI1                IRQ_DMA1_1      /* DMA1 1  Interrupt(PPI2) */
  32 #define IRQ_DMA1_2              BFIN_IRQ(13)    /* DMA1 2  Interrupt */
  33 #define IRQ_DMA1_3              BFIN_IRQ(14)    /* DMA1 3  Interrupt */
  34 #define IRQ_DMA1_4              BFIN_IRQ(15)    /* DMA1 4  Interrupt */
  35 #define IRQ_DMA1_5              BFIN_IRQ(16)    /* DMA1 5  Interrupt */
  36 #define IRQ_DMA1_6              BFIN_IRQ(17)    /* DMA1 6  Interrupt */
  37 #define IRQ_DMA1_7              BFIN_IRQ(18)    /* DMA1 7  Interrupt */
  38 #define IRQ_DMA1_8              BFIN_IRQ(19)    /* DMA1 8  Interrupt */
  39 #define IRQ_DMA1_9              BFIN_IRQ(20)    /* DMA1 9  Interrupt */
  40 #define IRQ_DMA1_10             BFIN_IRQ(21)    /* DMA1 10 Interrupt */
  41 #define IRQ_DMA1_11             BFIN_IRQ(22)    /* DMA1 11 Interrupt */
  42 #define IRQ_DMA2_0              BFIN_IRQ(23)    /* DMA2 0  (SPORT0 RX) */
  43 #define IRQ_SPORT0_RX           IRQ_DMA2_0      /* DMA2 0  (SPORT0 RX) */
  44 #define IRQ_DMA2_1              BFIN_IRQ(24)    /* DMA2 1  (SPORT0 TX) */
  45 #define IRQ_SPORT0_TX           IRQ_DMA2_1      /* DMA2 1  (SPORT0 TX) */
  46 #define IRQ_DMA2_2              BFIN_IRQ(25)    /* DMA2 2  (SPORT1 RX) */
  47 #define IRQ_SPORT1_RX           IRQ_DMA2_2      /* DMA2 2  (SPORT1 RX) */
  48 #define IRQ_DMA2_3              BFIN_IRQ(26)    /* DMA2 3  (SPORT2 TX) */
  49 #define IRQ_SPORT1_TX           IRQ_DMA2_3      /* DMA2 3  (SPORT2 TX) */
  50 #define IRQ_DMA2_4              BFIN_IRQ(27)    /* DMA2 4  (SPI) */
  51 #define IRQ_SPI                 IRQ_DMA2_4      /* DMA2 4  (SPI) */
  52 #define IRQ_DMA2_5              BFIN_IRQ(28)    /* DMA2 5  (UART RX) */
  53 #define IRQ_UART_RX             IRQ_DMA2_5      /* DMA2 5  (UART RX) */
  54 #define IRQ_DMA2_6              BFIN_IRQ(29)    /* DMA2 6  (UART TX) */
  55 #define IRQ_UART_TX             IRQ_DMA2_6      /* DMA2 6  (UART TX) */
  56 #define IRQ_DMA2_7              BFIN_IRQ(30)    /* DMA2 7  Interrupt */
  57 #define IRQ_DMA2_8              BFIN_IRQ(31)    /* DMA2 8  Interrupt */
  58 #define IRQ_DMA2_9              BFIN_IRQ(32)    /* DMA2 9  Interrupt */
  59 #define IRQ_DMA2_10             BFIN_IRQ(33)    /* DMA2 10 Interrupt */
  60 #define IRQ_DMA2_11             BFIN_IRQ(34)    /* DMA2 11 Interrupt */
  61 #define IRQ_TIMER0              BFIN_IRQ(35)    /* TIMER 0  Interrupt */
  62 #define IRQ_TIMER1              BFIN_IRQ(36)    /* TIMER 1  Interrupt */
  63 #define IRQ_TIMER2              BFIN_IRQ(37)    /* TIMER 2  Interrupt */
  64 #define IRQ_TIMER3              BFIN_IRQ(38)    /* TIMER 3  Interrupt */
  65 #define IRQ_TIMER4              BFIN_IRQ(39)    /* TIMER 4  Interrupt */
  66 #define IRQ_TIMER5              BFIN_IRQ(40)    /* TIMER 5  Interrupt */
  67 #define IRQ_TIMER6              BFIN_IRQ(41)    /* TIMER 6  Interrupt */
  68 #define IRQ_TIMER7              BFIN_IRQ(42)    /* TIMER 7  Interrupt */
  69 #define IRQ_TIMER8              BFIN_IRQ(43)    /* TIMER 8  Interrupt */
  70 #define IRQ_TIMER9              BFIN_IRQ(44)    /* TIMER 9  Interrupt */
  71 #define IRQ_TIMER10             BFIN_IRQ(45)    /* TIMER 10 Interrupt */
  72 #define IRQ_TIMER11             BFIN_IRQ(46)    /* TIMER 11 Interrupt */
  73 #define IRQ_PROG0_INTA          BFIN_IRQ(47)    /* Programmable Flags0 A (8) */
  74 #define IRQ_PROG_INTA           IRQ_PROG0_INTA  /* Programmable Flags0 A (8) */
  75 #define IRQ_PROG0_INTB          BFIN_IRQ(48)    /* Programmable Flags0 B (8) */
  76 #define IRQ_PROG_INTB           IRQ_PROG0_INTB  /* Programmable Flags0 B (8) */
  77 #define IRQ_PROG1_INTA          BFIN_IRQ(49)    /* Programmable Flags1 A (8) */
  78 #define IRQ_PROG1_INTB          BFIN_IRQ(50)    /* Programmable Flags1 B (8) */
  79 #define IRQ_PROG2_INTA          BFIN_IRQ(51)    /* Programmable Flags2 A (8) */
  80 #define IRQ_PROG2_INTB          BFIN_IRQ(52)    /* Programmable Flags2 B (8) */
  81 #define IRQ_DMA1_WRRD0          BFIN_IRQ(53)    /* MDMA1 0 write/read INT */
  82 #define IRQ_DMA_WRRD0           IRQ_DMA1_WRRD0  /* MDMA1 0 write/read INT */
  83 #define IRQ_MEM_DMA0            IRQ_DMA1_WRRD0
  84 #define IRQ_DMA1_WRRD1          BFIN_IRQ(54)    /* MDMA1 1 write/read INT */
  85 #define IRQ_DMA_WRRD1           IRQ_DMA1_WRRD1  /* MDMA1 1 write/read INT */
  86 #define IRQ_MEM_DMA1            IRQ_DMA1_WRRD1
  87 #define IRQ_DMA2_WRRD0          BFIN_IRQ(55)    /* MDMA2 0 write/read INT */
  88 #define IRQ_MEM_DMA2            IRQ_DMA2_WRRD0
  89 #define IRQ_DMA2_WRRD1          BFIN_IRQ(56)    /* MDMA2 1 write/read INT */
  90 #define IRQ_MEM_DMA3            IRQ_DMA2_WRRD1
  91 #define IRQ_IMDMA_WRRD0         BFIN_IRQ(57)    /* IMDMA 0 write/read INT */
  92 #define IRQ_IMEM_DMA0           IRQ_IMDMA_WRRD0
  93 #define IRQ_IMDMA_WRRD1         BFIN_IRQ(58)    /* IMDMA 1 write/read INT */
  94 #define IRQ_IMEM_DMA1           IRQ_IMDMA_WRRD1
  95 #define IRQ_WATCH               BFIN_IRQ(59)    /* Watch Dog Timer */
  96 #define IRQ_RESERVED_1          BFIN_IRQ(60)    /* Reserved interrupt */
  97 #define IRQ_RESERVED_2          BFIN_IRQ(61)    /* Reserved interrupt */
  98 #define IRQ_SUPPLE_0            BFIN_IRQ(62)    /* Supplemental interrupt 0 */
  99 #define IRQ_SUPPLE_1            BFIN_IRQ(63)    /* supplemental interrupt 1 */
 100
 101 #define SYS_IRQS                71
 102
 103 #define IRQ_PF0                 73
 104 #define IRQ_PF1                 74
 105 #define IRQ_PF2                 75
 106 #define IRQ_PF3                 76
 107 #define IRQ_PF4                 77
 108 #define IRQ_PF5                 78
 109 #define IRQ_PF6                 79
 110 #define IRQ_PF7                 80
 111 #define IRQ_PF8                 81
 112 #define IRQ_PF9                 82
 113 #define IRQ_PF10                83
 114 #define IRQ_PF11                84
 115 #define IRQ_PF12                85
 116 #define IRQ_PF13                86
 117 #define IRQ_PF14                87
 118 #define IRQ_PF15                88
 119 #define IRQ_PF16                89
 120 #define IRQ_PF17                90
 121 #define IRQ_PF18                91
 122 #define IRQ_PF19                92
 123 #define IRQ_PF20                93
 124 #define IRQ_PF21                94
 125 #define IRQ_PF22                95
 126 #define IRQ_PF23                96
 127 #define IRQ_PF24                97
 128 #define IRQ_PF25                98
 129 #define IRQ_PF26                99
 130 #define IRQ_PF27                100
 131 #define IRQ_PF28                101
 132 #define IRQ_PF29                102
 133 #define IRQ_PF30                103
 134 #define IRQ_PF31                104
 135 #define IRQ_PF32                105
 136 #define IRQ_PF33                106
 137 #define IRQ_PF34                107
 138 #define IRQ_PF35                108
 139 #define IRQ_PF36                109
 140 #define IRQ_PF37                110
 141 #define IRQ_PF38                111
 142 #define IRQ_PF39                112
 143 #define IRQ_PF40                113
 144 #define IRQ_PF41                114
 145 #define IRQ_PF42                115
 146 #define IRQ_PF43                116
 147 #define IRQ_PF44                117
 148 #define IRQ_PF45                118
 149 #define IRQ_PF46                119
 150 #define IRQ_PF47                120
 151
 152 #define GPIO_IRQ_BASE           IRQ_PF0
 153
 154 #define NR_MACH_IRQS            (IRQ_PF47 + 1)
 155
 156 /* IAR0 BIT FIELDS */
 157 #define IRQ_PLL_WAKEUP_POS      0
 158 #define IRQ_DMA1_ERROR_POS      4
 159 #define IRQ_DMA2_ERROR_POS      8
 160 #define IRQ_IMDMA_ERROR_POS     12
 161 #define IRQ_PPI0_ERROR_POS      16
 162 #define IRQ_PPI1_ERROR_POS      20
 163 #define IRQ_SPORT0_ERROR_POS    24
 164 #define IRQ_SPORT1_ERROR_POS    28
 165
 166 /* IAR1 BIT FIELDS */
 167 #define IRQ_SPI_ERROR_POS       0
 168 #define IRQ_UART_ERROR_POS      4
 169 #define IRQ_RESERVED_ERROR_POS  8
 170 #define IRQ_DMA1_0_POS          12
 171 #define IRQ_DMA1_1_POS          16
 172 #define IRQ_DMA1_2_POS          20
 173 #define IRQ_DMA1_3_POS          24
 174 #define IRQ_DMA1_4_POS          28
 175
 176 /* IAR2 BIT FIELDS */
 177 #define IRQ_DMA1_5_POS          0
 178 #define IRQ_DMA1_6_POS          4
 179 #define IRQ_DMA1_7_POS          8
 180 #define IRQ_DMA1_8_POS          12
 181 #define IRQ_DMA1_9_POS          16
 182 #define IRQ_DMA1_10_POS         20
 183 #define IRQ_DMA1_11_POS         24
 184 #define IRQ_DMA2_0_POS          28
 185
 186 /* IAR3 BIT FIELDS */
 187 #define IRQ_DMA2_1_POS          0
 188 #define IRQ_DMA2_2_POS          4
 189 #define IRQ_DMA2_3_POS          8
 190 #define IRQ_DMA2_4_POS          12
 191 #define IRQ_DMA2_5_POS          16
 192 #define IRQ_DMA2_6_POS          20
 193 #define IRQ_DMA2_7_POS          24
 194 #define IRQ_DMA2_8_POS          28
 195
 196 /* IAR4 BIT FIELDS */
 197 #define IRQ_DMA2_9_POS          0
 198 #define IRQ_DMA2_10_POS         4
 199 #define IRQ_DMA2_11_POS         8
 200 #define IRQ_TIMER0_POS          12
 201 #define IRQ_TIMER1_POS          16
 202 #define IRQ_TIMER2_POS          20
 203 #define IRQ_TIMER3_POS          24
 204 #define IRQ_TIMER4_POS          28
 205
 206 /* IAR5 BIT FIELDS */
 207 #define IRQ_TIMER5_POS          0
 208 #define IRQ_TIMER6_POS          4
 209 #define IRQ_TIMER7_POS          8
 210 #define IRQ_TIMER8_POS          12
 211 #define IRQ_TIMER9_POS          16
 212 #define IRQ_TIMER10_POS         20
 213 #define IRQ_TIMER11_POS         24
 214 #define IRQ_PROG0_INTA_POS      28
 215
 216 /* IAR6 BIT FIELDS */
 217 #define IRQ_PROG0_INTB_POS      0
 218 #define IRQ_PROG1_INTA_POS      4
 219 #define IRQ_PROG1_INTB_POS      8
 220 #define IRQ_PROG2_INTA_POS      12
 221 #define IRQ_PROG2_INTB_POS      16
 222 #define IRQ_DMA1_WRRD0_POS      20
 223 #define IRQ_DMA1_WRRD1_POS      24
 224 #define IRQ_DMA2_WRRD0_POS      28
 225
 226 /* IAR7 BIT FIELDS */
 227 #define IRQ_DMA2_WRRD1_POS      0
 228 #define IRQ_IMDMA_WRRD0_POS     4
 229 #define IRQ_IMDMA_WRRD1_POS     8
 230 #define IRQ_WDTIMER_POS         12
 231 #define IRQ_RESERVED_1_POS      16
 232 #define IRQ_RESERVED_2_POS      20
 233 #define IRQ_SUPPLE_0_POS        24
 234 #define IRQ_SUPPLE_1_POS        28
 235
 236 #endif