arch/blackfin/mach-bf561/include/mach/mem_map.h

   1 /*
   2  * BF561 memory map
   3  *
   4  * Copyright 2004-2009 Analog Devices Inc.
   5  * Licensed under the GPL-2 or later.
   6  */
   7
   8 #ifndef __BFIN_MACH_MEM_MAP_H__
   9 #define __BFIN_MACH_MEM_MAP_H__
  10
  11 #ifndef __BFIN_MEM_MAP_H__
  12 # error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
  13 #endif
  14
  15 /* Async Memory Banks */
  16 #define ASYNC_BANK3_BASE        0x2C000000       /* Async Bank 3 */
  17 #define ASYNC_BANK3_SIZE        0x04000000      /* 64M */
  18 #define ASYNC_BANK2_BASE        0x28000000       /* Async Bank 2 */
  19 #define ASYNC_BANK2_SIZE        0x04000000      /* 64M */
  20 #define ASYNC_BANK1_BASE        0x24000000       /* Async Bank 1 */
  21 #define ASYNC_BANK1_SIZE        0x04000000      /* 64M */
  22 #define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
  23 #define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
  24
  25 /* Boot ROM Memory */
  26
  27 #define BOOT_ROM_START          0xEF000000
  28 #define BOOT_ROM_LENGTH         0x800
  29
  30 /* Level 1 Memory */
  31
  32 #ifdef CONFIG_BFIN_ICACHE
  33 #define BFIN_ICACHESIZE (16*1024)
  34 #else
  35 #define BFIN_ICACHESIZE (0*1024)
  36 #endif
  37
  38 /* Memory Map for ADSP-BF561 processors */
  39
  40 #define COREA_L1_CODE_START       0xFFA00000
  41 #define COREA_L1_DATA_A_START     0xFF800000
  42 #define COREA_L1_DATA_B_START     0xFF900000
  43 #define COREB_L1_CODE_START       0xFF600000
  44 #define COREB_L1_DATA_A_START     0xFF400000
  45 #define COREB_L1_DATA_B_START     0xFF500000
  46
  47 #define L1_CODE_START       COREA_L1_CODE_START
  48 #define L1_DATA_A_START     COREA_L1_DATA_A_START
  49 #define L1_DATA_B_START     COREA_L1_DATA_B_START
  50
  51 #define L1_CODE_LENGTH      0x4000
  52
  53 #ifdef CONFIG_BFIN_DCACHE
  54
  55 #ifdef CONFIG_BFIN_DCACHE_BANKA
  56 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
  57 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
  58 #define L1_DATA_B_LENGTH      0x8000
  59 #define BFIN_DCACHESIZE (16*1024)
  60 #define BFIN_DSUPBANKS  1
  61 #else
  62 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
  63 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
  64 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
  65 #define BFIN_DCACHESIZE (32*1024)
  66 #define BFIN_DSUPBANKS  2
  67 #endif
  68
  69 #else
  70 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
  71 #define L1_DATA_A_LENGTH      0x8000
  72 #define L1_DATA_B_LENGTH      0x8000
  73 #define BFIN_DCACHESIZE (0*1024)
  74 #define BFIN_DSUPBANKS  0
  75 #endif /*CONFIG_BFIN_DCACHE*/
  76
  77 /*
  78  * If we are in SMP mode, then the cache settings of Core B will match
  79  * the settings of Core A.  If we aren't, then we assume Core B is not
  80  * using any cache.  This allows the rest of the kernel to work with
  81  * the core in either mode as we are only loading user code into it and
  82  * it is the user's problem to make sure they aren't doing something
  83  * stupid there.
  84  *
  85  * Note that we treat the L1 code region as a contiguous blob to make
  86  * the rest of the kernel simpler.  Easier to check one region than a
  87  * bunch of small ones.  Again, possible misbehavior here is the fault
  88  * of the user -- don't try to use memory that doesn't exist.
  89  */
  90 #ifdef CONFIG_SMP
  91 # define COREB_L1_CODE_LENGTH     L1_CODE_LENGTH
  92 # define COREB_L1_DATA_A_LENGTH   L1_DATA_A_LENGTH
  93 # define COREB_L1_DATA_B_LENGTH   L1_DATA_B_LENGTH
  94 #else
  95 # define COREB_L1_CODE_LENGTH     0x14000
  96 # define COREB_L1_DATA_A_LENGTH   0x8000
  97 # define COREB_L1_DATA_B_LENGTH   0x8000
  98 #endif
  99
 100 /* Level 2 Memory */
 101 #define L2_START                0xFEB00000
 102 #define L2_LENGTH               0x20000
 103
 104 /* Scratch Pad Memory */
 105
 106 #define COREA_L1_SCRATCH_START  0xFFB00000
 107 #define COREB_L1_SCRATCH_START  0xFF700000
 108
 109 #ifdef CONFIG_SMP
 110
 111 /*
 112  * The following macros both return the address of the PDA for the
 113  * current core.
 114  *
 115  * In its first safe (and hairy) form, the macro neither clobbers any
 116  * register aside of the output Preg, nor uses the stack, since it
 117  * could be called with an invalid stack pointer, or the current stack
 118  * space being uncovered by any CPLB (e.g. early exception handling).
 119  *
 120  * The constraints on the second form are a bit relaxed, and the code
 121  * is allowed to use the specified Dreg for determining the PDA
 122  * address to be returned into Preg.
 123  */
 124 # define GET_PDA_SAFE(preg)             \
 125         preg.l = lo(DSPID);             \
 126         preg.h = hi(DSPID);             \
 127         preg = [preg];                  \
 128         preg = preg << 2;               \
 129         preg = preg << 2;               \
 130         preg = preg << 2;               \
 131         preg = preg << 2;               \
 132         preg = preg << 2;               \
 133         preg = preg << 2;               \
 134         preg = preg << 2;               \
 135         preg = preg << 2;               \
 136         preg = preg << 2;               \
 137         preg = preg << 2;               \
 138         preg = preg << 2;               \
 139         preg = preg << 2;               \
 140         if cc jump 2f;                  \
 141         cc = preg == 0x0;               \
 142         preg.l = _cpu_pda;              \
 143         preg.h = _cpu_pda;              \
 144         if !cc jump 3f;                 \
 145 1:                                      \
 146         /* preg = 0x0; */               \
 147         cc = !cc; /* restore cc to 0 */ \
 148         jump 4f;                        \
 149 2:                                      \
 150         cc = preg == 0x0;               \
 151         preg.l = _cpu_pda;              \
 152         preg.h = _cpu_pda;              \
 153         if cc jump 4f;                  \
 154         /* preg = 0x1000000; */         \
 155         cc = !cc; /* restore cc to 1 */ \
 156 3:                                      \
 157         preg = [preg];                  \
 158 4:
 159
 160 # define GET_PDA(preg, dreg)            \
 161         preg.l = lo(DSPID);             \
 162         preg.h = hi(DSPID);             \
 163         dreg = [preg];                  \
 164         preg.l = _cpu_pda;              \
 165         preg.h = _cpu_pda;              \
 166         cc = bittst(dreg, 0);           \
 167         if !cc jump 1f;                 \
 168         preg = [preg];                  \
 169 1:                                      \
 170
 171 # define GET_CPUID(preg, dreg)          \
 172         preg.l = lo(DSPID);             \
 173         preg.h = hi(DSPID);             \
 174         dreg = [preg];                  \
 175         dreg = ROT dreg BY -1;          \
 176         dreg = CC;
 177
 178 # ifndef __ASSEMBLY__
 179
 180 #  include <asm/processor.h>
 181
 182 static inline unsigned long get_l1_scratch_start_cpu(int cpu)
 183 {
 184         return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
 185 }
 186 static inline unsigned long get_l1_code_start_cpu(int cpu)
 187 {
 188         return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
 189 }
 190 static inline unsigned long get_l1_data_a_start_cpu(int cpu)
 191 {
 192         return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
 193 }
 194 static inline unsigned long get_l1_data_b_start_cpu(int cpu)
 195 {
 196         return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
 197 }
 198
 199 static inline unsigned long get_l1_scratch_start(void)
 200 {
 201         return get_l1_scratch_start_cpu(blackfin_core_id());
 202 }
 203 static inline unsigned long get_l1_code_start(void)
 204 {
 205         return get_l1_code_start_cpu(blackfin_core_id());
 206 }
 207 static inline unsigned long get_l1_data_a_start(void)
 208 {
 209         return get_l1_data_a_start_cpu(blackfin_core_id());
 210 }
 211 static inline unsigned long get_l1_data_b_start(void)
 212 {
 213         return get_l1_data_b_start_cpu(blackfin_core_id());
 214 }
 215
 216 # endif /* __ASSEMBLY__ */
 217 #endif /* CONFIG_SMP */
 218
 219 #endif